* Start using tablegen'd instruction descriptions

* Fix bug in the createNOP method, which was not marking the operands of the
  generated XCHG as useanddef.  I don't think this method is actually used,
  so it wasn't breaking anything, but it should be fixed anyway...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7539 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index b03a12078dea16c89e8da40858b0be09c2577847..6988415933887a7ad72181cf00c2084876766ef5 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -8,31 +8,7 @@
 #include "X86.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 
-#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES)
-#define IMPREGSLIST(NAME, ...) \
-  static const unsigned NAME[] = { __VA_ARGS__ };
-#include "X86InstrInfo.def"
-
-
-// X86Insts - Turn the InstrInfo.def file into a bunch of instruction
-// descriptors
-//
-static const TargetInstrDescriptor X86Insts[] = {
-#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPUSES, IMPDEFS)   \
-             { NAME,                    \
-               -1, /* Always vararg */  \
-               ((TSFLAGS) & X86II::Void) ? -1 : 0,  /* Result is in 0 */ \
-               0,                                   /* maxImmedConst field */\
-               false,                               /* immedIsSignExtended */\
-               0,                                   /* numDelaySlots */\
-               0,                                   /* latency */\
-               0,                                   /* schedClass */\
-               FLAGS,                               /* Flags */\
-               TSFLAGS,                             /* TSFlags */\
-               IMPUSES,                             /* ImplicitUses */\
-               IMPDEFS },                           /* ImplicitDefs */
-#include "X86InstrInfo.def"
-};
+#include "X86GenInstrInfo.inc"
 
 X86InstrInfo::X86InstrInfo()
   : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
@@ -44,7 +20,8 @@ X86InstrInfo::X86InstrInfo()
 // another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
 //
 MachineInstr* X86InstrInfo::createNOPinstr() const {
-  return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX).addReg(X86::AX);
+  return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MOTy::UseAndDef)
+                                  .addReg(X86::AX, MOTy::UseAndDef);
 }
 
 
@@ -54,28 +31,14 @@ MachineInstr* X86InstrInfo::createNOPinstr() const {
 //
 bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
   // Make sure the instruction is EXACTLY `xchg ax, ax'
-  if (MI.getOpcode() == X86::XCHGrr16 && MI.getNumOperands() == 2) {
+  if (MI.getOpcode() == X86::XCHGrr16) {
     const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
     if (op0.isMachineRegister() && op0.getMachineRegNum() == X86::AX &&
-        op1.isMachineRegister() && op1.getMachineRegNum() == X86::AX)
-    {
+        op1.isMachineRegister() && op1.getMachineRegNum() == X86::AX) {
       return true;
     }
   }
+  // FIXME: there are several NOOP instructions, we should check for them here.
   return false;
 }
 
-
-static unsigned char BaseOpcodes[] = {
-#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) BASEOPCODE,
-#include "X86InstrInfo.def"
-};
-
-// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
-// specified opcode number.
-//
-unsigned char X86InstrInfo::getBaseOpcodeFor(unsigned Opcode) const {
-  assert(Opcode < sizeof(BaseOpcodes)/sizeof(BaseOpcodes[0]) &&
-         "Opcode out of range!");
-  return BaseOpcodes[Opcode];
-}