Start using tablegenerated instruction descriptions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7538 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/Makefile b/lib/Target/X86/Makefile
index 80ace9804a1f794e12d263f3496ca07e9b90c35b..ff4ab7c0194811ec6759a3cb6a732a840c4746c6 100644 (file)
--- a/lib/Target/X86/Makefile
+++ b/lib/Target/X86/Makefile
@@ -2,20 +2,26 @@ LEVEL = ../../..
 LIBRARYNAME = x86
 include $(LEVEL)/Makefile.common
 
-
-
 # Make sure that tblgen is run, first thing.
-$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc X86GenRegisterInfo.inc
+$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
+                 X86GenRegisterInfo.inc X86GenInstrNames.inc \
+                 X86GenInstrInfo.inc
 
-X86GenRegisterNames.inc:  $(wildcard *.td) $(TBLGEN)
+X86GenRegisterNames.inc:  X86.td X86RegisterInfo.td $(TBLGEN)
        $(TBLGEN) X86.td -gen-register-enums -o $@
 
-X86GenRegisterInfo.h.inc: $(wildcard *.td) $(TBLGEN)
+X86GenRegisterInfo.h.inc: X86.td X86RegisterInfo.td $(TBLGEN)
        $(TBLGEN) X86.td -gen-register-desc-header -o $@
 
-X86GenRegisterInfo.inc: $(wildcard *.td) $(TBLGEN)
+X86GenRegisterInfo.inc: X86.td X86RegisterInfo.td $(TBLGEN)
        $(TBLGEN) X86.td -gen-register-desc -o $@
 
+X86GenInstrNames.inc: X86.td X86InstrInfo.td $(TBLGEN)
+       $(TBLGEN) X86.td -gen-instr-enums -o $@
+
+X86GenInstrInfo.inc: X86.td X86InstrInfo.td $(TBLGEN)
+       $(TBLGEN) X86.td -gen-instr-desc -o $@
+
 clean::
        $(VERB) rm -f *.inc