xmm0 variable blends

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46931 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 3d70985c96dec480ad64f14d863f568cf76e245d..83e446c75f9f49591a2306714c7c12e548985015 100644 (file)
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -3223,7 +3223,7 @@ let isTwoAddress = 1 in {
     def rri : SS4AI<opc, MRMSrcReg, (outs VR128:$dst),
                     (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
                     !strconcat(OpcodeStr, 
-                     "\t{$$src3, src2, $dst|$dst, $src2, $src3}"),
+                     "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
                     [(set VR128:$dst, 
                       (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
                     OpSize {
@@ -3232,7 +3232,7 @@ let isTwoAddress = 1 in {
     def rmi : SS4AI<opc, MRMSrcMem, (outs VR128:$dst),
                     (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
                     !strconcat(OpcodeStr,
-                     "\t{$$src3, src2, $dst|$dst, $src2, $src3}"),
+                     "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
                     [(set VR128:$dst,
                       (IntId128 VR128:$src1,
                        (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
@@ -3254,6 +3254,31 @@ defm MPSADBW      : SS41I_binop_rmi_int<0x42, "mpsadbw",
                                         int_x86_sse41_mpsadbw, 0>;
 
 
+/// SS41I_binop_rmi_int - SSE 4.1 binary operator with immediate
+let isTwoAddress = 1 in {
+  multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
+    def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
+                    (ins VR128:$src1, VR128:$src2),
+                    !strconcat(OpcodeStr, 
+                     "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
+                    [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
+                    OpSize;
+
+    def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
+                    (ins VR128:$src1, i128mem:$src2),
+                    !strconcat(OpcodeStr,
+                     "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
+                    [(set VR128:$dst,
+                      (IntId VR128:$src1,
+                       (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
+  }
+}
+
+defm BLENDVPD     : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
+defm BLENDVPS     : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
+defm PBLENDVB     : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
+
+
 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
   def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                  !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),