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DE66EF7008ABEE5F00323D32 /* Sparc */,
DE66F09308ABEE6000323D32 /* X86 */,
- DE66EF1008ABEE5E00323D32 /* MRegisterInfo.cpp */,
+ DE66EF1008ABEE5E00323D32 /* TargetRegisterInfo.cpp */,
CF9BCD1508C75070001E7011 /* SubtargetFeature.cpp */,
DE66F08A08ABEE6000323D32 /* Target.td */,
CF47BD860AAF487E00A8B13E /* TargetAsmInfo.cpp */,
DE66F29F08ABF03200323D32 /* Target */ = {
isa = PBXGroup;
children = (
- DE66F2A008ABF03200323D32 /* MRegisterInfo.h */,
+ DE66F2A008ABF03200323D32 /* TargetRegisterInfo.h */,
CF9BCD0808C74DE0001E7011 /* SubtargetFeature.h */,
CF47BD380AAF40BC00A8B13E /* TargetAsmInfo.h */,
DE66F2A108ABF03200323D32 /* TargetData.h */,
<li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
<li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
<li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
- <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
+ <li><a href="#targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a></li>
<li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
<li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
<li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
<!-- ======================================================================= -->
<div class="doc_subsection">
- <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
+ <a name="targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a>
</div>
<div class="doc_text">
-<p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
-<tt>TargetRegisterInfo</tt>) is used to describe the register file of the
-target and any interactions between the registers.</p>
+<p>The <tt>TargetRegisterInfo</tt> class is used to describe the register
+file of the target and any interactions between the registers.</p>
<p>Registers in the code generator are represented in the code generator by
unsigned integers. Physical registers (those that actually exist in the target
(used to indicate whether one register overlaps with another).
</p>
-<p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
-exposes a set of processor specific register classes (instances of the
+<p>In addition to the per-register description, the <tt>TargetRegisterInfo</tt>
+class exposes a set of processor specific register classes (instances of the
<tt>TargetRegisterClass</tt> class). Each register class contains sets of
registers that have the same properties (for example, they are all 32-bit
integer registers). Each SSA virtual register created by the instruction
marked as <i>aliased</i> in LLVM. Given a particular architecture, you
can check which registers are aliased by inspecting its
<tt>RegisterInfo.td</tt> file. Moreover, the method
-<tt>MRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
+<tt>TargetRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
all the physical registers aliased to the register <tt>p_reg</tt>.</p>
<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
bool RegMapping_Fer::compatible_class(MachineFunction &mf,
unsigned v_reg,
unsigned p_reg) {
- assert(MRegisterInfo::isPhysicalRegister(p_reg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &&
"Target register must be physical");
const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
return trc->contains(p_reg);
number. The smallest virtual register is normally assigned the number
1024. This may change, so, in order to know which is the first virtual
register, you should access
-<tt>MRegisterInfo::FirstVirtualRegister</tt>. Any register whose
+<tt>TargetRegisterInfo::FirstVirtualRegister</tt>. Any register whose
number is greater than or equal to
-<tt>MRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
+<tt>TargetRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
register. Whereas physical registers are statically defined in a
<tt>TargetRegisterInfo.td</tt> file and cannot be created by the
application developer, that is not the case with virtual registers.
<p>There are two ways to map virtual registers to physical registers (or to
memory slots). The first way, that we will call <i>direct mapping</i>,
-is based on the use of methods of the classes <tt>MRegisterInfo</tt>,
+is based on the use of methods of the classes <tt>TargetRegisterInfo</tt>,
and <tt>MachineOperand</tt>. The second way, that we will call
<i>indirect mapping</i>, relies on the <tt>VirtRegMap</tt> class in
order to insert loads and stores sending and getting values to and from
memory. To assign a physical register to a virtual register present in
a given operand, use <tt>MachineOperand::setReg(p_reg)</tt>. To insert
a store instruction, use
-<tt>MRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a load
-instruction, use <tt>MRegisterInfo::loadRegFromStackSlot</tt>.</p>
+<tt>TargetRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a load
+instruction, use <tt>TargetRegisterInfo::loadRegFromStackSlot</tt>.</p>
<p>The indirect mapping shields the application developer from the
complexities of inserting load and store instructions. In order to map
</div>
<p>Instructions can be folded with the
-<tt>MRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
+<tt>TargetRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
taken when folding instructions; a folded instruction can be quite
different from the original instruction. See
<tt>LiveIntervals::addIntervalsForSpills</tt> in
<li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
the register set and register classes</li>
<li>Implement a subclass of <tt><a
- href="CodeGenerator.html#mregisterinfo">MRegisterInfo</a></tt></li>
+ href="CodeGenerator.html#targetregisterinfo">TargetRegisterInfo</a></tt></li>
</ul></li>
<li>Describe the instruction set.
<ul>
#include "llvm/CodeGen/ValueTypes.h"
namespace llvm {
- class MRegisterInfo;
+ class TargetRegisterInfo;
class TargetMachine;
class CCState;
class SDNode;
unsigned CallingConv;
bool IsVarArg;
const TargetMachine &TM;
- const MRegisterInfo &MRI;
+ const TargetRegisterInfo &TRI;
SmallVector<CCValAssign, 16> &Locs;
unsigned StackOffset;
namespace llvm {
class MachineInstr;
- class MRegisterInfo;
+ class TargetRegisterInfo;
struct LiveInterval;
/// VNInfo - If the value number definition is undefined (e.g. phi
return beginNumber() < other.beginNumber();
}
- void print(std::ostream &OS, const MRegisterInfo *MRI = 0) const;
- void print(std::ostream *OS, const MRegisterInfo *MRI = 0) const {
- if (OS) print(*OS, MRI);
+ void print(std::ostream &OS, const TargetRegisterInfo *TRI = 0) const;
+ void print(std::ostream *OS, const TargetRegisterInfo *TRI = 0) const {
+ if (OS) print(*OS, TRI);
}
void dump() const;
class LiveVariables;
class MachineLoopInfo;
- class MRegisterInfo;
+ class TargetRegisterInfo;
class MachineRegisterInfo;
class TargetInstrInfo;
class TargetRegisterClass;
class LiveIntervals : public MachineFunctionPass {
MachineFunction* mf_;
const TargetMachine* tm_;
- const MRegisterInfo* mri_;
+ const TargetRegisterInfo* tri_;
const TargetInstrInfo* tii_;
LiveVariables* lv_;
namespace llvm {
-class MRegisterInfo;
+class TargetRegisterInfo;
class LiveVariables : public MachineFunctionPass {
public:
private: // Intermediate data structures
MachineFunction *MF;
- const MRegisterInfo *RegInfo;
+ const TargetRegisterInfo *RegInfo;
// PhysRegInfo - Keep track of which instruction was the last def/use of a
// physical register. This is a purely local property, because all physical
/// MMI - This field is set (via setMachineModuleInfo) by a module info
/// consumer (ex. DwarfWriter) to indicate that frame layout information
/// should be acquired. Typically, it's the responsibility of the target's
- /// MRegisterInfo prologue/epilogue emitting code to inform MachineModuleInfo
- /// of frame layouts.
+ /// TargetRegisterInfo prologue/epilogue emitting code to inform
+ /// MachineModuleInfo of frame layouts.
MachineModuleInfo *MMI;
/// TargetFrameInfo - Target information about frame layout.
CSInfo = CSI;
}
- /// getMachineModuleInfo - Used by a prologue/epilogue emitter (MRegisterInfo)
- /// to provide frame layout information.
+ /// getMachineModuleInfo - Used by a prologue/epilogue
+ /// emitter (TargetRegisterInfo) to provide frame layout information.
MachineModuleInfo *getMachineModuleInfo() const { return MMI; }
/// setMachineModuleInfo - Used by a meta info consumer (DwarfWriter) to
namespace llvm {
class TargetInstrDesc;
-class MRegisterInfo;
+class TargetRegisterInfo;
template <typename T> struct ilist_traits;
template <typename T> struct ilist;
/// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
/// add a implicit operand if it's not found. Returns true if the operand
/// exists / is added.
- bool addRegisterKilled(unsigned IncomingReg, const MRegisterInfo *RegInfo,
+ bool addRegisterKilled(unsigned IncomingReg,
+ const TargetRegisterInfo *RegInfo,
bool AddIfNotFound = false);
/// addRegisterDead - We have determined MI defined a register without a use.
/// Look for the operand that defines it and mark it as IsDead. If
/// AddIfNotFound is true, add a implicit operand if it's not found. Returns
/// true if the operand exists / is added.
- bool addRegisterDead(unsigned IncomingReg, const MRegisterInfo *RegInfo,
+ bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
bool AddIfNotFound = false);
/// copyKillDeadInfo - copies killed/dead information from one instr to another
void copyKillDeadInfo(MachineInstr *OldMI,
- const MRegisterInfo *RegInfo);
+ const TargetRegisterInfo *RegInfo);
//
// Debugging support
public:
enum {
// The target register number for an abstract frame pointer. The value is
- // an arbitrary value greater than MRegisterInfo::FirstVirtualRegister.
+ // an arbitrary value greater than TargetRegisterInfo::FirstVirtualRegister.
VirtualFP = ~0U
};
MachineLocation()
#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/iterator"
#include <vector>
class MachineRegisterInfo {
/// VRegInfo - Information we keep for each virtual register. The entries in
/// this vector are actually converted to vreg numbers by adding the
- /// MRegisterInfo::FirstVirtualRegister delta to their index.
+ /// TargetRegisterInfo::FirstVirtualRegister delta to their index.
///
/// Each element in this list contains the register class of the vreg and the
/// start of the use/def list for the register.
MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
public:
- explicit MachineRegisterInfo(const MRegisterInfo &MRI);
+ explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
~MachineRegisterInfo();
//===--------------------------------------------------------------------===//
/// getRegUseDefListHead - Return the head pointer for the register use/def
/// list for the specified virtual or physical register.
MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
- if (RegNo < MRegisterInfo::FirstVirtualRegister)
+ if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
return PhysRegUseDefLists[RegNo];
- RegNo -= MRegisterInfo::FirstVirtualRegister;
+ RegNo -= TargetRegisterInfo::FirstVirtualRegister;
return VRegInfo[RegNo].second;
}
MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
- if (RegNo < MRegisterInfo::FirstVirtualRegister)
+ if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
return PhysRegUseDefLists[RegNo];
- RegNo -= MRegisterInfo::FirstVirtualRegister;
+ RegNo -= TargetRegisterInfo::FirstVirtualRegister;
return VRegInfo[RegNo].second;
}
/// getRegClass - Return the register class of the specified virtual register.
const TargetRegisterClass *getRegClass(unsigned Reg) {
- Reg -= MRegisterInfo::FirstVirtualRegister;
+ Reg -= TargetRegisterInfo::FirstVirtualRegister;
assert(Reg < VRegInfo.size() && "Invalid vreg!");
return VRegInfo[Reg].first;
}
/// getLastVirtReg - Return the highest currently assigned virtual register.
///
unsigned getLastVirtReg() const {
- return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1;
+ return VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
}
/// getVRegDef - Return the machine instr that defines the specified virtual
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/Debug.h"
#ifndef LLVM_CODEGEN_REGISTER_COALESCER_H
class AnalysisUsage;
class LiveIntervals;
class MachineInstr;
- class MRegisterInfo;
+ class TargetRegisterInfo;
/// An abstract interface for register coalescers. Coalescers must
/// implement this interface to be part of the coalescer analysis
namespace llvm {
-class MRegisterInfo;
+class TargetRegisterInfo;
class TargetInstrInfo;
class TargetRegisterClass;
}
private:
- const MRegisterInfo *RegInfo;
+ const TargetRegisterInfo *RegInfo;
const TargetInstrInfo *TII;
/// CalleeSavedrRegs - A bitvector of callee saved registers for the target.
class MachineModuleInfo;
class MachineRegisterInfo;
class MachineInstr;
- class MRegisterInfo;
+ class TargetRegisterInfo;
class SelectionDAG;
class SelectionDAGISel;
class TargetInstrInfo;
MachineBasicBlock *BB; // Current basic block
const TargetMachine &TM; // Target processor
const TargetInstrInfo *TII; // Target instruction information
- const MRegisterInfo *MRI; // Target processor register info
+ const TargetRegisterInfo *TRI; // Target processor register info
MachineFunction *MF; // Machine function
MachineRegisterInfo &RegInfo; // Virtual/real register map
MachineConstantPool *ConstPool; // Target constant pool
+++ /dev/null
-//===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes an abstract interface used to get information about a
-// target machines register file. This information is used for a variety of
-// purposed, especially register allocation.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_MREGISTERINFO_H
-#define LLVM_TARGET_MREGISTERINFO_H
-
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/ValueTypes.h"
-#include <cassert>
-#include <functional>
-
-namespace llvm {
-
-class BitVector;
-class MachineFunction;
-class MachineInstr;
-class MachineMove;
-class RegScavenger;
-class SDNode;
-class SelectionDAG;
-class TargetRegisterClass;
-class Type;
-
-/// TargetRegisterDesc - This record contains all of the information known about
-/// a particular register. The AliasSet field (if not null) contains a pointer
-/// to a Zero terminated array of registers that this register aliases. This is
-/// needed for architectures like X86 which have AL alias AX alias EAX.
-/// Registers that this does not apply to simply should set this to null.
-/// The SubRegs field is a zero terminated array of registers that are
-/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
-/// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate
-/// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH,
-/// AL which are immediate sub-registers of AX. The SuperRegs field is a zero
-/// terminated array of registers that are super-registers of the specific
-/// register, e.g. RAX, EAX, are super-registers of AX.
-///
-struct TargetRegisterDesc {
- const char *Name; // Assembly language name for the register
- const unsigned *AliasSet; // Register Alias Set, described above
- const unsigned *SubRegs; // Sub-register set, described above
- const unsigned *ImmSubRegs; // Immediate sub-register set, described above
- const unsigned *SuperRegs; // Super-register set, described above
-};
-
-class TargetRegisterClass {
-public:
- typedef const unsigned* iterator;
- typedef const unsigned* const_iterator;
-
- typedef const MVT::ValueType* vt_iterator;
- typedef const TargetRegisterClass* const * sc_iterator;
-private:
- unsigned ID;
- bool isSubClass;
- const vt_iterator VTs;
- const sc_iterator SubClasses;
- const sc_iterator SuperClasses;
- const sc_iterator SubRegClasses;
- const sc_iterator SuperRegClasses;
- const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
- const int CopyCost;
- const iterator RegsBegin, RegsEnd;
-public:
- TargetRegisterClass(unsigned id,
- const MVT::ValueType *vts,
- const TargetRegisterClass * const *subcs,
- const TargetRegisterClass * const *supcs,
- const TargetRegisterClass * const *subregcs,
- const TargetRegisterClass * const *superregcs,
- unsigned RS, unsigned Al, int CC,
- iterator RB, iterator RE)
- : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
- SubRegClasses(subregcs), SuperRegClasses(superregcs),
- RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
- virtual ~TargetRegisterClass() {} // Allow subclasses
-
- /// getID() - Return the register class ID number.
- ///
- unsigned getID() const { return ID; }
-
- /// begin/end - Return all of the registers in this class.
- ///
- iterator begin() const { return RegsBegin; }
- iterator end() const { return RegsEnd; }
-
- /// getNumRegs - Return the number of registers in this class.
- ///
- unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
-
- /// getRegister - Return the specified register in the class.
- ///
- unsigned getRegister(unsigned i) const {
- assert(i < getNumRegs() && "Register number out of range!");
- return RegsBegin[i];
- }
-
- /// contains - Return true if the specified register is included in this
- /// register class.
- bool contains(unsigned Reg) const {
- for (iterator I = begin(), E = end(); I != E; ++I)
- if (*I == Reg) return true;
- return false;
- }
-
- /// hasType - return true if this TargetRegisterClass has the ValueType vt.
- ///
- bool hasType(MVT::ValueType vt) const {
- for(int i = 0; VTs[i] != MVT::Other; ++i)
- if (VTs[i] == vt)
- return true;
- return false;
- }
-
- /// vt_begin / vt_end - Loop over all of the value types that can be
- /// represented by values in this register class.
- vt_iterator vt_begin() const {
- return VTs;
- }
-
- vt_iterator vt_end() const {
- vt_iterator I = VTs;
- while (*I != MVT::Other) ++I;
- return I;
- }
-
- /// hasSubClass - return true if the specified TargetRegisterClass is a
- /// sub-register class of this TargetRegisterClass.
- bool hasSubClass(const TargetRegisterClass *cs) const {
- for (int i = 0; SubClasses[i] != NULL; ++i)
- if (SubClasses[i] == cs)
- return true;
- return false;
- }
-
- /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
- /// this register class.
- sc_iterator subclasses_begin() const {
- return SubClasses;
- }
-
- sc_iterator subclasses_end() const {
- sc_iterator I = SubClasses;
- while (*I != NULL) ++I;
- return I;
- }
-
- /// hasSuperClass - return true if the specified TargetRegisterClass is a
- /// super-register class of this TargetRegisterClass.
- bool hasSuperClass(const TargetRegisterClass *cs) const {
- for (int i = 0; SuperClasses[i] != NULL; ++i)
- if (SuperClasses[i] == cs)
- return true;
- return false;
- }
-
- /// superclasses_begin / superclasses_end - Loop over all of the super-classes
- /// of this register class.
- sc_iterator superclasses_begin() const {
- return SuperClasses;
- }
-
- sc_iterator superclasses_end() const {
- sc_iterator I = SuperClasses;
- while (*I != NULL) ++I;
- return I;
- }
-
- /// hasSubRegClass - return true if the specified TargetRegisterClass is a
- /// class of a sub-register class for this TargetRegisterClass.
- bool hasSubRegClass(const TargetRegisterClass *cs) const {
- for (int i = 0; SubRegClasses[i] != NULL; ++i)
- if (SubRegClasses[i] == cs)
- return true;
- return false;
- }
-
- /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
- /// class of a sub-register class for this TargetRegisterClass.
- bool hasClassForSubReg(unsigned SubReg) const {
- --SubReg;
- for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
- if (i == SubReg)
- return true;
- return false;
- }
-
- /// getClassForSubReg - return theTargetRegisterClass for the sub-register
- /// at idx for this TargetRegisterClass.
- sc_iterator getClassForSubReg(unsigned SubReg) const {
- --SubReg;
- for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
- if (i == SubReg)
- return &SubRegClasses[i];
- assert(0 && "Invalid subregister index for register class");
- return NULL;
- }
-
- /// subregclasses_begin / subregclasses_end - Loop over all of
- /// the subregister classes of this register class.
- sc_iterator subregclasses_begin() const {
- return SubRegClasses;
- }
-
- sc_iterator subregclasses_end() const {
- sc_iterator I = SubRegClasses;
- while (*I != NULL) ++I;
- return I;
- }
-
- /// superregclasses_begin / superregclasses_end - Loop over all of
- /// the superregister classes of this register class.
- sc_iterator superregclasses_begin() const {
- return SuperRegClasses;
- }
-
- sc_iterator superregclasses_end() const {
- sc_iterator I = SuperRegClasses;
- while (*I != NULL) ++I;
- return I;
- }
-
- /// allocation_order_begin/end - These methods define a range of registers
- /// which specify the registers in this class that are valid to register
- /// allocate, and the preferred order to allocate them in. For example,
- /// callee saved registers should be at the end of the list, because it is
- /// cheaper to allocate caller saved registers.
- ///
- /// These methods take a MachineFunction argument, which can be used to tune
- /// the allocatable registers based on the characteristics of the function.
- /// One simple example is that the frame pointer register can be used if
- /// frame-pointer-elimination is performed.
- ///
- /// By default, these methods return all registers in the class.
- ///
- virtual iterator allocation_order_begin(const MachineFunction &MF) const {
- return begin();
- }
- virtual iterator allocation_order_end(const MachineFunction &MF) const {
- return end();
- }
-
-
-
- /// getSize - Return the size of the register in bytes, which is also the size
- /// of a stack slot allocated to hold a spilled copy of this register.
- unsigned getSize() const { return RegSize; }
-
- /// getAlignment - Return the minimum required alignment for a register of
- /// this class.
- unsigned getAlignment() const { return Alignment; }
-
- /// getCopyCost - Return the cost of copying a value between two registers in
- /// this class.
- int getCopyCost() const { return CopyCost; }
-};
-
-
-/// MRegisterInfo base class - We assume that the target defines a static array
-/// of TargetRegisterDesc objects that represent all of the machine registers
-/// that the target has. As such, we simply have to track a pointer to this
-/// array so that we can turn register number into a register descriptor.
-///
-class MRegisterInfo {
-public:
- typedef const TargetRegisterClass * const * regclass_iterator;
-private:
- const TargetRegisterDesc *Desc; // Pointer to the descriptor array
- unsigned NumRegs; // Number of entries in the array
-
- regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
-
- int CallFrameSetupOpcode, CallFrameDestroyOpcode;
-protected:
- MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
- regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
- int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
- virtual ~MRegisterInfo();
-public:
-
- enum { // Define some target independent constants
- /// NoRegister - This physical register is not a real target register. It
- /// is useful as a sentinal.
- NoRegister = 0,
-
- /// FirstVirtualRegister - This is the first register number that is
- /// considered to be a 'virtual' register, which is part of the SSA
- /// namespace. This must be the same for all targets, which means that each
- /// target is limited to 1024 registers.
- FirstVirtualRegister = 1024
- };
-
- /// isPhysicalRegister - Return true if the specified register number is in
- /// the physical register namespace.
- static bool isPhysicalRegister(unsigned Reg) {
- assert(Reg && "this is not a register!");
- return Reg < FirstVirtualRegister;
- }
-
- /// isVirtualRegister - Return true if the specified register number is in
- /// the virtual register namespace.
- static bool isVirtualRegister(unsigned Reg) {
- assert(Reg && "this is not a register!");
- return Reg >= FirstVirtualRegister;
- }
-
- /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
- /// register of the given type.
- const TargetRegisterClass *getPhysicalRegisterRegClass(MVT::ValueType VT,
- unsigned Reg) const;
-
- /// getAllocatableSet - Returns a bitset indexed by register number
- /// indicating if a register is allocatable or not. If a register class is
- /// specified, returns the subset for the class.
- BitVector getAllocatableSet(MachineFunction &MF,
- const TargetRegisterClass *RC = NULL) const;
-
- const TargetRegisterDesc &operator[](unsigned RegNo) const {
- assert(RegNo < NumRegs &&
- "Attempting to access record for invalid register number!");
- return Desc[RegNo];
- }
-
- /// Provide a get method, equivalent to [], but more useful if we have a
- /// pointer to this object.
- ///
- const TargetRegisterDesc &get(unsigned RegNo) const {
- return operator[](RegNo);
- }
-
- /// getAliasSet - Return the set of registers aliased by the specified
- /// register, or a null list of there are none. The list returned is zero
- /// terminated.
- ///
- const unsigned *getAliasSet(unsigned RegNo) const {
- return get(RegNo).AliasSet;
- }
-
- /// getSubRegisters - Return the set of registers that are sub-registers of
- /// the specified register, or a null list of there are none. The list
- /// returned is zero terminated.
- ///
- const unsigned *getSubRegisters(unsigned RegNo) const {
- return get(RegNo).SubRegs;
- }
-
- /// getImmediateSubRegisters - Return the set of registers that are immediate
- /// sub-registers of the specified register, or a null list of there are none.
- /// The list returned is zero terminated.
- ///
- const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
- return get(RegNo).ImmSubRegs;
- }
-
- /// getSuperRegisters - Return the set of registers that are super-registers
- /// of the specified register, or a null list of there are none. The list
- /// returned is zero terminated.
- ///
- const unsigned *getSuperRegisters(unsigned RegNo) const {
- return get(RegNo).SuperRegs;
- }
-
- /// getName - Return the symbolic target specific name for the specified
- /// physical register.
- const char *getName(unsigned RegNo) const {
- return get(RegNo).Name;
- }
-
- /// getNumRegs - Return the number of registers this target has (useful for
- /// sizing arrays holding per register information)
- unsigned getNumRegs() const {
- return NumRegs;
- }
-
- /// areAliases - Returns true if the two registers alias each other, false
- /// otherwise
- bool areAliases(unsigned regA, unsigned regB) const {
- for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
- if (*Alias == regB) return true;
- return false;
- }
-
- /// regsOverlap - Returns true if the two registers are equal or alias each
- /// other. The registers may be virtual register.
- bool regsOverlap(unsigned regA, unsigned regB) const {
- if (regA == regB)
- return true;
-
- if (isVirtualRegister(regA) || isVirtualRegister(regB))
- return false;
- return areAliases(regA, regB);
- }
-
- /// isSubRegister - Returns true if regB is a sub-register of regA.
- ///
- bool isSubRegister(unsigned regA, unsigned regB) const {
- for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
- if (*SR == regB) return true;
- return false;
- }
-
- /// isSuperRegister - Returns true if regB is a super-register of regA.
- ///
- bool isSuperRegister(unsigned regA, unsigned regB) const {
- for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
- if (*SR == regB) return true;
- return false;
- }
-
- /// getCalleeSavedRegs - Return a null-terminated list of all of the
- /// callee saved registers on this target. The register should be in the
- /// order of desired callee-save stack frame offset. The first register is
- /// closed to the incoming stack pointer if stack grows down, and vice versa.
- virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
- const = 0;
-
- /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
- /// register classes to spill each callee saved register with. The order and
- /// length of this list match the getCalleeSaveRegs() list.
- virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
- const MachineFunction *MF) const =0;
-
- /// getReservedRegs - Returns a bitset indexed by physical register number
- /// indicating if a register is a special register that has particular uses
- /// and should be considered unavailable at all times, e.g. SP, RA. This is
- /// used by register scavenger to determine what registers are free.
- virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
-
- /// getSubReg - Returns the physical register number of sub-register "Index"
- /// for physical register RegNo.
- virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
-
- //===--------------------------------------------------------------------===//
- // Register Class Information
- //
-
- /// Register class iterators
- ///
- regclass_iterator regclass_begin() const { return RegClassBegin; }
- regclass_iterator regclass_end() const { return RegClassEnd; }
-
- unsigned getNumRegClasses() const {
- return regclass_end()-regclass_begin();
- }
-
- /// getRegClass - Returns the register class associated with the enumeration
- /// value. See class TargetOperandInfo.
- const TargetRegisterClass *getRegClass(unsigned i) const {
- assert(i <= getNumRegClasses() && "Register Class ID out of range");
- return i ? RegClassBegin[i - 1] : NULL;
- }
-
- //===--------------------------------------------------------------------===//
- // Interfaces used by the register allocator and stack frame
- // manipulation passes to move data around between registers,
- // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
- //
-
- /// getCrossCopyRegClass - Returns a legal register class to copy a register
- /// in the specified class to or from. Returns NULL if it is possible to copy
- /// between a two registers of the specified class.
- virtual const TargetRegisterClass *
- getCrossCopyRegClass(const TargetRegisterClass *RC) const {
- return NULL;
- }
-
- /// reMaterialize - Re-issue the specified 'original' instruction at the
- /// specific location targeting a new destination register.
- virtual void reMaterialize(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg,
- const MachineInstr *Orig) const = 0;
-
- /// targetHandlesStackFrameRounding - Returns true if the target is
- /// responsible for rounding up the stack frame (probably at emitPrologue
- /// time).
- virtual bool targetHandlesStackFrameRounding() const {
- return false;
- }
-
- /// requiresRegisterScavenging - returns true if the target requires (and can
- /// make use of) the register scavenger.
- virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
- return false;
- }
-
- /// hasFP - Return true if the specified function should have a dedicated
- /// frame pointer register. For most targets this is true only if the function
- /// has variable sized allocas or if frame pointer elimination is disabled.
- virtual bool hasFP(const MachineFunction &MF) const = 0;
-
- // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
- // not required, we reserve argument space for call sites in the function
- // immediately on entry to the current function. This eliminates the need for
- // add/sub sp brackets around call sites. Returns true if the call frame is
- // included as part of the stack frame.
- virtual bool hasReservedCallFrame(MachineFunction &MF) const {
- return !hasFP(MF);
- }
-
- /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
- /// frame setup/destroy instructions if they exist (-1 otherwise). Some
- /// targets use pseudo instructions in order to abstract away the difference
- /// between operating with a frame pointer and operating without, through the
- /// use of these two instructions.
- ///
- int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
- int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
-
-
- /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
- /// code insertion to eliminate call frame setup and destroy pseudo
- /// instructions (but only if the Target is using them). It is responsible
- /// for eliminating these instructions, replacing them with concrete
- /// instructions. This method need only be implemented if using call frame
- /// setup/destroy pseudo instructions.
- ///
- virtual void
- eliminateCallFramePseudoInstr(MachineFunction &MF,
- MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI) const {
- assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
- "eliminateCallFramePseudoInstr must be implemented if using"
- " call frame setup/destroy pseudo instructions!");
- assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
- }
-
- /// processFunctionBeforeCalleeSavedScan - This method is called immediately
- /// before PrologEpilogInserter scans the physical registers used to determine
- /// what callee saved registers should be spilled. This method is optional.
- virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
- RegScavenger *RS = NULL) const {
-
- }
-
- /// processFunctionBeforeFrameFinalized - This method is called immediately
- /// before the specified functions frame layout (MF.getFrameInfo()) is
- /// finalized. Once the frame is finalized, MO_FrameIndex operands are
- /// replaced with direct constants. This method is optional.
- ///
- virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
- }
-
- /// eliminateFrameIndex - This method must be overriden to eliminate abstract
- /// frame indices from instructions which may use them. The instruction
- /// referenced by the iterator contains an MO_FrameIndex operand which must be
- /// eliminated by this method. This method may modify or replace the
- /// specified instruction, as long as it keeps the iterator pointing the the
- /// finished product. SPAdj is the SP adjustment due to call frame setup
- /// instruction. The return value is the number of instructions added to
- /// (negative if removed from) the basic block.
- ///
- virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
- int SPAdj, RegScavenger *RS=NULL) const = 0;
-
- /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
- /// the function. The return value is the number of instructions
- /// added to (negative if removed from) the basic block (entry for prologue).
- ///
- virtual void emitPrologue(MachineFunction &MF) const = 0;
- virtual void emitEpilogue(MachineFunction &MF,
- MachineBasicBlock &MBB) const = 0;
-
- //===--------------------------------------------------------------------===//
- /// Debug information queries.
-
- /// getDwarfRegNum - Map a target register to an equivalent dwarf register
- /// number. Returns -1 if there is no equivalent value. The second
- /// parameter allows targets to use different numberings for EH info and
- /// deubgging info.
- virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
-
- /// getFrameRegister - This method should return the register used as a base
- /// for values allocated in the current stack frame.
- virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
-
- /// getFrameIndexOffset - Returns the displacement from the frame register to
- /// the stack frame of the specified index.
- virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
-
- /// getRARegister - This method should return the register where the return
- /// address can be found.
- virtual unsigned getRARegister() const = 0;
-
- /// getInitialFrameState - Returns a list of machine moves that are assumed
- /// on entry to all functions. Note that LabelID is ignored (assumed to be
- /// the beginning of the function.)
- virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
-};
-
-// This is useful when building IndexedMaps keyed on virtual registers
-struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
- unsigned operator()(unsigned Reg) const {
- return Reg - MRegisterInfo::FirstVirtualRegister;
- }
-};
-
-} // End llvm namespace
-
-#endif
class TargetLowering;
class TargetFrameInfo;
class MachineCodeEmitter;
-class MRegisterInfo;
+class TargetRegisterInfo;
class Module;
class FunctionPassManager;
class PassManager;
/// not, return null. This is kept separate from RegInfo until RegInfo has
/// details of graph coloring register allocation removed from it.
///
- virtual const MRegisterInfo *getRegisterInfo() const { return 0; }
+ virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
/// getJITInfo - If this target supports a JIT, return information for it,
/// otherwise return null.
--- /dev/null
+//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes an abstract interface used to get information about a
+// target machines register file. This information is used for a variety of
+// purposed, especially register allocation.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TARGET_TARGETREGISTERINFO_H
+#define LLVM_TARGET_TARGETREGISTERINFO_H
+
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/ValueTypes.h"
+#include <cassert>
+#include <functional>
+
+namespace llvm {
+
+class BitVector;
+class MachineFunction;
+class MachineInstr;
+class MachineMove;
+class RegScavenger;
+class SDNode;
+class SelectionDAG;
+class TargetRegisterClass;
+class Type;
+
+/// TargetRegisterDesc - This record contains all of the information known about
+/// a particular register. The AliasSet field (if not null) contains a pointer
+/// to a Zero terminated array of registers that this register aliases. This is
+/// needed for architectures like X86 which have AL alias AX alias EAX.
+/// Registers that this does not apply to simply should set this to null.
+/// The SubRegs field is a zero terminated array of registers that are
+/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
+/// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate
+/// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH,
+/// AL which are immediate sub-registers of AX. The SuperRegs field is a zero
+/// terminated array of registers that are super-registers of the specific
+/// register, e.g. RAX, EAX, are super-registers of AX.
+///
+struct TargetRegisterDesc {
+ const char *Name; // Assembly language name for the register
+ const unsigned *AliasSet; // Register Alias Set, described above
+ const unsigned *SubRegs; // Sub-register set, described above
+ const unsigned *ImmSubRegs; // Immediate sub-register set, described above
+ const unsigned *SuperRegs; // Super-register set, described above
+};
+
+class TargetRegisterClass {
+public:
+ typedef const unsigned* iterator;
+ typedef const unsigned* const_iterator;
+
+ typedef const MVT::ValueType* vt_iterator;
+ typedef const TargetRegisterClass* const * sc_iterator;
+private:
+ unsigned ID;
+ bool isSubClass;
+ const vt_iterator VTs;
+ const sc_iterator SubClasses;
+ const sc_iterator SuperClasses;
+ const sc_iterator SubRegClasses;
+ const sc_iterator SuperRegClasses;
+ const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
+ const int CopyCost;
+ const iterator RegsBegin, RegsEnd;
+public:
+ TargetRegisterClass(unsigned id,
+ const MVT::ValueType *vts,
+ const TargetRegisterClass * const *subcs,
+ const TargetRegisterClass * const *supcs,
+ const TargetRegisterClass * const *subregcs,
+ const TargetRegisterClass * const *superregcs,
+ unsigned RS, unsigned Al, int CC,
+ iterator RB, iterator RE)
+ : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
+ SubRegClasses(subregcs), SuperRegClasses(superregcs),
+ RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
+ virtual ~TargetRegisterClass() {} // Allow subclasses
+
+ /// getID() - Return the register class ID number.
+ ///
+ unsigned getID() const { return ID; }
+
+ /// begin/end - Return all of the registers in this class.
+ ///
+ iterator begin() const { return RegsBegin; }
+ iterator end() const { return RegsEnd; }
+
+ /// getNumRegs - Return the number of registers in this class.
+ ///
+ unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
+
+ /// getRegister - Return the specified register in the class.
+ ///
+ unsigned getRegister(unsigned i) const {
+ assert(i < getNumRegs() && "Register number out of range!");
+ return RegsBegin[i];
+ }
+
+ /// contains - Return true if the specified register is included in this
+ /// register class.
+ bool contains(unsigned Reg) const {
+ for (iterator I = begin(), E = end(); I != E; ++I)
+ if (*I == Reg) return true;
+ return false;
+ }
+
+ /// hasType - return true if this TargetRegisterClass has the ValueType vt.
+ ///
+ bool hasType(MVT::ValueType vt) const {
+ for(int i = 0; VTs[i] != MVT::Other; ++i)
+ if (VTs[i] == vt)
+ return true;
+ return false;
+ }
+
+ /// vt_begin / vt_end - Loop over all of the value types that can be
+ /// represented by values in this register class.
+ vt_iterator vt_begin() const {
+ return VTs;
+ }
+
+ vt_iterator vt_end() const {
+ vt_iterator I = VTs;
+ while (*I != MVT::Other) ++I;
+ return I;
+ }
+
+ /// hasSubClass - return true if the specified TargetRegisterClass is a
+ /// sub-register class of this TargetRegisterClass.
+ bool hasSubClass(const TargetRegisterClass *cs) const {
+ for (int i = 0; SubClasses[i] != NULL; ++i)
+ if (SubClasses[i] == cs)
+ return true;
+ return false;
+ }
+
+ /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
+ /// this register class.
+ sc_iterator subclasses_begin() const {
+ return SubClasses;
+ }
+
+ sc_iterator subclasses_end() const {
+ sc_iterator I = SubClasses;
+ while (*I != NULL) ++I;
+ return I;
+ }
+
+ /// hasSuperClass - return true if the specified TargetRegisterClass is a
+ /// super-register class of this TargetRegisterClass.
+ bool hasSuperClass(const TargetRegisterClass *cs) const {
+ for (int i = 0; SuperClasses[i] != NULL; ++i)
+ if (SuperClasses[i] == cs)
+ return true;
+ return false;
+ }
+
+ /// superclasses_begin / superclasses_end - Loop over all of the super-classes
+ /// of this register class.
+ sc_iterator superclasses_begin() const {
+ return SuperClasses;
+ }
+
+ sc_iterator superclasses_end() const {
+ sc_iterator I = SuperClasses;
+ while (*I != NULL) ++I;
+ return I;
+ }
+
+ /// hasSubRegClass - return true if the specified TargetRegisterClass is a
+ /// class of a sub-register class for this TargetRegisterClass.
+ bool hasSubRegClass(const TargetRegisterClass *cs) const {
+ for (int i = 0; SubRegClasses[i] != NULL; ++i)
+ if (SubRegClasses[i] == cs)
+ return true;
+ return false;
+ }
+
+ /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
+ /// class of a sub-register class for this TargetRegisterClass.
+ bool hasClassForSubReg(unsigned SubReg) const {
+ --SubReg;
+ for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
+ if (i == SubReg)
+ return true;
+ return false;
+ }
+
+ /// getClassForSubReg - return theTargetRegisterClass for the sub-register
+ /// at idx for this TargetRegisterClass.
+ sc_iterator getClassForSubReg(unsigned SubReg) const {
+ --SubReg;
+ for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
+ if (i == SubReg)
+ return &SubRegClasses[i];
+ assert(0 && "Invalid subregister index for register class");
+ return NULL;
+ }
+
+ /// subregclasses_begin / subregclasses_end - Loop over all of
+ /// the subregister classes of this register class.
+ sc_iterator subregclasses_begin() const {
+ return SubRegClasses;
+ }
+
+ sc_iterator subregclasses_end() const {
+ sc_iterator I = SubRegClasses;
+ while (*I != NULL) ++I;
+ return I;
+ }
+
+ /// superregclasses_begin / superregclasses_end - Loop over all of
+ /// the superregister classes of this register class.
+ sc_iterator superregclasses_begin() const {
+ return SuperRegClasses;
+ }
+
+ sc_iterator superregclasses_end() const {
+ sc_iterator I = SuperRegClasses;
+ while (*I != NULL) ++I;
+ return I;
+ }
+
+ /// allocation_order_begin/end - These methods define a range of registers
+ /// which specify the registers in this class that are valid to register
+ /// allocate, and the preferred order to allocate them in. For example,
+ /// callee saved registers should be at the end of the list, because it is
+ /// cheaper to allocate caller saved registers.
+ ///
+ /// These methods take a MachineFunction argument, which can be used to tune
+ /// the allocatable registers based on the characteristics of the function.
+ /// One simple example is that the frame pointer register can be used if
+ /// frame-pointer-elimination is performed.
+ ///
+ /// By default, these methods return all registers in the class.
+ ///
+ virtual iterator allocation_order_begin(const MachineFunction &MF) const {
+ return begin();
+ }
+ virtual iterator allocation_order_end(const MachineFunction &MF) const {
+ return end();
+ }
+
+
+
+ /// getSize - Return the size of the register in bytes, which is also the size
+ /// of a stack slot allocated to hold a spilled copy of this register.
+ unsigned getSize() const { return RegSize; }
+
+ /// getAlignment - Return the minimum required alignment for a register of
+ /// this class.
+ unsigned getAlignment() const { return Alignment; }
+
+ /// getCopyCost - Return the cost of copying a value between two registers in
+ /// this class.
+ int getCopyCost() const { return CopyCost; }
+};
+
+
+/// TargetRegisterInfo base class - We assume that the target defines a static
+/// array of TargetRegisterDesc objects that represent all of the machine
+/// registers that the target has. As such, we simply have to track a pointer
+/// to this array so that we can turn register number into a register
+/// descriptor.
+///
+class TargetRegisterInfo {
+public:
+ typedef const TargetRegisterClass * const * regclass_iterator;
+private:
+ const TargetRegisterDesc *Desc; // Pointer to the descriptor array
+ unsigned NumRegs; // Number of entries in the array
+
+ regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
+
+ int CallFrameSetupOpcode, CallFrameDestroyOpcode;
+protected:
+ TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
+ regclass_iterator RegClassBegin,
+ regclass_iterator RegClassEnd,
+ int CallFrameSetupOpcode = -1,
+ int CallFrameDestroyOpcode = -1);
+ virtual ~TargetRegisterInfo();
+public:
+
+ enum { // Define some target independent constants
+ /// NoRegister - This physical register is not a real target register. It
+ /// is useful as a sentinal.
+ NoRegister = 0,
+
+ /// FirstVirtualRegister - This is the first register number that is
+ /// considered to be a 'virtual' register, which is part of the SSA
+ /// namespace. This must be the same for all targets, which means that each
+ /// target is limited to 1024 registers.
+ FirstVirtualRegister = 1024
+ };
+
+ /// isPhysicalRegister - Return true if the specified register number is in
+ /// the physical register namespace.
+ static bool isPhysicalRegister(unsigned Reg) {
+ assert(Reg && "this is not a register!");
+ return Reg < FirstVirtualRegister;
+ }
+
+ /// isVirtualRegister - Return true if the specified register number is in
+ /// the virtual register namespace.
+ static bool isVirtualRegister(unsigned Reg) {
+ assert(Reg && "this is not a register!");
+ return Reg >= FirstVirtualRegister;
+ }
+
+ /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
+ /// register of the given type.
+ const TargetRegisterClass *getPhysicalRegisterRegClass(MVT::ValueType VT,
+ unsigned Reg) const;
+
+ /// getAllocatableSet - Returns a bitset indexed by register number
+ /// indicating if a register is allocatable or not. If a register class is
+ /// specified, returns the subset for the class.
+ BitVector getAllocatableSet(MachineFunction &MF,
+ const TargetRegisterClass *RC = NULL) const;
+
+ const TargetRegisterDesc &operator[](unsigned RegNo) const {
+ assert(RegNo < NumRegs &&
+ "Attempting to access record for invalid register number!");
+ return Desc[RegNo];
+ }
+
+ /// Provide a get method, equivalent to [], but more useful if we have a
+ /// pointer to this object.
+ ///
+ const TargetRegisterDesc &get(unsigned RegNo) const {
+ return operator[](RegNo);
+ }
+
+ /// getAliasSet - Return the set of registers aliased by the specified
+ /// register, or a null list of there are none. The list returned is zero
+ /// terminated.
+ ///
+ const unsigned *getAliasSet(unsigned RegNo) const {
+ return get(RegNo).AliasSet;
+ }
+
+ /// getSubRegisters - Return the set of registers that are sub-registers of
+ /// the specified register, or a null list of there are none. The list
+ /// returned is zero terminated.
+ ///
+ const unsigned *getSubRegisters(unsigned RegNo) const {
+ return get(RegNo).SubRegs;
+ }
+
+ /// getImmediateSubRegisters - Return the set of registers that are immediate
+ /// sub-registers of the specified register, or a null list of there are none.
+ /// The list returned is zero terminated.
+ ///
+ const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
+ return get(RegNo).ImmSubRegs;
+ }
+
+ /// getSuperRegisters - Return the set of registers that are super-registers
+ /// of the specified register, or a null list of there are none. The list
+ /// returned is zero terminated.
+ ///
+ const unsigned *getSuperRegisters(unsigned RegNo) const {
+ return get(RegNo).SuperRegs;
+ }
+
+ /// getName - Return the symbolic target specific name for the specified
+ /// physical register.
+ const char *getName(unsigned RegNo) const {
+ return get(RegNo).Name;
+ }
+
+ /// getNumRegs - Return the number of registers this target has (useful for
+ /// sizing arrays holding per register information)
+ unsigned getNumRegs() const {
+ return NumRegs;
+ }
+
+ /// areAliases - Returns true if the two registers alias each other, false
+ /// otherwise
+ bool areAliases(unsigned regA, unsigned regB) const {
+ for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
+ if (*Alias == regB) return true;
+ return false;
+ }
+
+ /// regsOverlap - Returns true if the two registers are equal or alias each
+ /// other. The registers may be virtual register.
+ bool regsOverlap(unsigned regA, unsigned regB) const {
+ if (regA == regB)
+ return true;
+
+ if (isVirtualRegister(regA) || isVirtualRegister(regB))
+ return false;
+ return areAliases(regA, regB);
+ }
+
+ /// isSubRegister - Returns true if regB is a sub-register of regA.
+ ///
+ bool isSubRegister(unsigned regA, unsigned regB) const {
+ for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
+ if (*SR == regB) return true;
+ return false;
+ }
+
+ /// isSuperRegister - Returns true if regB is a super-register of regA.
+ ///
+ bool isSuperRegister(unsigned regA, unsigned regB) const {
+ for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
+ if (*SR == regB) return true;
+ return false;
+ }
+
+ /// getCalleeSavedRegs - Return a null-terminated list of all of the
+ /// callee saved registers on this target. The register should be in the
+ /// order of desired callee-save stack frame offset. The first register is
+ /// closed to the incoming stack pointer if stack grows down, and vice versa.
+ virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
+ const = 0;
+
+ /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
+ /// register classes to spill each callee saved register with. The order and
+ /// length of this list match the getCalleeSaveRegs() list.
+ virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
+ const MachineFunction *MF) const =0;
+
+ /// getReservedRegs - Returns a bitset indexed by physical register number
+ /// indicating if a register is a special register that has particular uses
+ /// and should be considered unavailable at all times, e.g. SP, RA. This is
+ /// used by register scavenger to determine what registers are free.
+ virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
+
+ /// getSubReg - Returns the physical register number of sub-register "Index"
+ /// for physical register RegNo.
+ virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
+
+ //===--------------------------------------------------------------------===//
+ // Register Class Information
+ //
+
+ /// Register class iterators
+ ///
+ regclass_iterator regclass_begin() const { return RegClassBegin; }
+ regclass_iterator regclass_end() const { return RegClassEnd; }
+
+ unsigned getNumRegClasses() const {
+ return regclass_end()-regclass_begin();
+ }
+
+ /// getRegClass - Returns the register class associated with the enumeration
+ /// value. See class TargetOperandInfo.
+ const TargetRegisterClass *getRegClass(unsigned i) const {
+ assert(i <= getNumRegClasses() && "Register Class ID out of range");
+ return i ? RegClassBegin[i - 1] : NULL;
+ }
+
+ //===--------------------------------------------------------------------===//
+ // Interfaces used by the register allocator and stack frame
+ // manipulation passes to move data around between registers,
+ // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
+ //
+
+ /// getCrossCopyRegClass - Returns a legal register class to copy a register
+ /// in the specified class to or from. Returns NULL if it is possible to copy
+ /// between a two registers of the specified class.
+ virtual const TargetRegisterClass *
+ getCrossCopyRegClass(const TargetRegisterClass *RC) const {
+ return NULL;
+ }
+
+ /// reMaterialize - Re-issue the specified 'original' instruction at the
+ /// specific location targeting a new destination register.
+ virtual void reMaterialize(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg,
+ const MachineInstr *Orig) const = 0;
+
+ /// targetHandlesStackFrameRounding - Returns true if the target is
+ /// responsible for rounding up the stack frame (probably at emitPrologue
+ /// time).
+ virtual bool targetHandlesStackFrameRounding() const {
+ return false;
+ }
+
+ /// requiresRegisterScavenging - returns true if the target requires (and can
+ /// make use of) the register scavenger.
+ virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
+ return false;
+ }
+
+ /// hasFP - Return true if the specified function should have a dedicated
+ /// frame pointer register. For most targets this is true only if the function
+ /// has variable sized allocas or if frame pointer elimination is disabled.
+ virtual bool hasFP(const MachineFunction &MF) const = 0;
+
+ // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
+ // not required, we reserve argument space for call sites in the function
+ // immediately on entry to the current function. This eliminates the need for
+ // add/sub sp brackets around call sites. Returns true if the call frame is
+ // included as part of the stack frame.
+ virtual bool hasReservedCallFrame(MachineFunction &MF) const {
+ return !hasFP(MF);
+ }
+
+ /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
+ /// frame setup/destroy instructions if they exist (-1 otherwise). Some
+ /// targets use pseudo instructions in order to abstract away the difference
+ /// between operating with a frame pointer and operating without, through the
+ /// use of these two instructions.
+ ///
+ int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
+ int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
+
+
+ /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
+ /// code insertion to eliminate call frame setup and destroy pseudo
+ /// instructions (but only if the Target is using them). It is responsible
+ /// for eliminating these instructions, replacing them with concrete
+ /// instructions. This method need only be implemented if using call frame
+ /// setup/destroy pseudo instructions.
+ ///
+ virtual void
+ eliminateCallFramePseudoInstr(MachineFunction &MF,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const {
+ assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
+ "eliminateCallFramePseudoInstr must be implemented if using"
+ " call frame setup/destroy pseudo instructions!");
+ assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
+ }
+
+ /// processFunctionBeforeCalleeSavedScan - This method is called immediately
+ /// before PrologEpilogInserter scans the physical registers used to determine
+ /// what callee saved registers should be spilled. This method is optional.
+ virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
+ RegScavenger *RS = NULL) const {
+
+ }
+
+ /// processFunctionBeforeFrameFinalized - This method is called immediately
+ /// before the specified functions frame layout (MF.getFrameInfo()) is
+ /// finalized. Once the frame is finalized, MO_FrameIndex operands are
+ /// replaced with direct constants. This method is optional.
+ ///
+ virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
+ }
+
+ /// eliminateFrameIndex - This method must be overriden to eliminate abstract
+ /// frame indices from instructions which may use them. The instruction
+ /// referenced by the iterator contains an MO_FrameIndex operand which must be
+ /// eliminated by this method. This method may modify or replace the
+ /// specified instruction, as long as it keeps the iterator pointing the the
+ /// finished product. SPAdj is the SP adjustment due to call frame setup
+ /// instruction. The return value is the number of instructions added to
+ /// (negative if removed from) the basic block.
+ ///
+ virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
+ int SPAdj, RegScavenger *RS=NULL) const = 0;
+
+ /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
+ /// the function. The return value is the number of instructions
+ /// added to (negative if removed from) the basic block (entry for prologue).
+ ///
+ virtual void emitPrologue(MachineFunction &MF) const = 0;
+ virtual void emitEpilogue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const = 0;
+
+ //===--------------------------------------------------------------------===//
+ /// Debug information queries.
+
+ /// getDwarfRegNum - Map a target register to an equivalent dwarf register
+ /// number. Returns -1 if there is no equivalent value. The second
+ /// parameter allows targets to use different numberings for EH info and
+ /// deubgging info.
+ virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
+
+ /// getFrameRegister - This method should return the register used as a base
+ /// for values allocated in the current stack frame.
+ virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
+
+ /// getFrameIndexOffset - Returns the displacement from the frame register to
+ /// the stack frame of the specified index.
+ virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
+
+ /// getRARegister - This method should return the register where the return
+ /// address can be found.
+ virtual unsigned getRARegister() const = 0;
+
+ /// getInitialFrameState - Returns a list of machine moves that are assumed
+ /// on entry to all functions. Note that LabelID is ignored (assumed to be
+ /// the beginning of the function.)
+ virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
+};
+
+// This is useful when building IndexedMaps keyed on virtual registers
+struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
+ unsigned operator()(unsigned Reg) const {
+ return Reg - TargetRegisterInfo::FirstVirtualRegister;
+ }
+};
+
+} // End llvm namespace
+
+#endif
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/ADT/Statistic.h"
MachineBasicBlock::iterator BBI1);
std::vector<std::pair<unsigned,MachineBasicBlock*> > MergePotentials;
- const MRegisterInfo *RegInfo;
+ const TargetRegisterInfo *RegInfo;
RegScavenger *RS;
// Branch optzn.
bool OptimizeBranches(MachineFunction &MF);
#include "llvm/Support/Mangler.h"
#include "llvm/System/Path.h"
#include "llvm/Target/TargetAsmInfo.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
const TargetData *TD;
/// RI - Register Information.
- const MRegisterInfo *RI;
+ const TargetRegisterInfo *RI;
/// M - Current module.
///
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/Streams.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <ostream>
using namespace llvm;
cerr << *this << "\n";
}
-void LiveInterval::print(std::ostream &OS, const MRegisterInfo *MRI) const {
- if (MRI && MRegisterInfo::isPhysicalRegister(reg))
- OS << MRI->getName(reg);
+void LiveInterval::print(std::ostream &OS,
+ const TargetRegisterInfo *TRI) const {
+ if (TRI && TargetRegisterInfo::isPhysicalRegister(reg))
+ OS << TRI->getName(reg);
else
OS << "%reg" << reg;
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CommandLine.h"
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
mf_ = &fn;
tm_ = &fn.getTarget();
- mri_ = tm_->getRegisterInfo();
+ tri_ = tm_->getRegisterInfo();
tii_ = tm_->getInstrInfo();
lv_ = &getAnalysis<LiveVariables>();
- allocatableRegs_ = mri_->getAllocatableSet(fn);
+ allocatableRegs_ = tri_->getAllocatableSet(fn);
// Number MachineInstrs and MachineBasicBlocks.
// Initialize MBB indexes to a sentinal.
DOUT << "********** INTERVALS **********\n";
for (iterator I = begin(), E = end(); I != E; ++I) {
- I->second.print(DOUT, mri_);
+ I->second.print(DOUT, tri_);
DOUT << "\n";
}
void LiveIntervals::print(std::ostream &O, const Module* ) const {
O << "********** INTERVALS **********\n";
for (const_iterator I = begin(), E = end(); I != E; ++I) {
- I->second.print(DOUT, mri_);
+ I->second.print(DOUT, tri_);
DOUT << "\n";
}
unsigned PhysReg = mop.getReg();
if (PhysReg == 0 || PhysReg == li.reg)
continue;
- if (MRegisterInfo::isVirtualRegister(PhysReg)) {
+ if (TargetRegisterInfo::isVirtualRegister(PhysReg)) {
if (!vrm.hasPhys(PhysReg))
continue;
PhysReg = vrm.getPhys(PhysReg);
}
- if (PhysReg && mri_->regsOverlap(PhysReg, reg))
+ if (PhysReg && tri_->regsOverlap(PhysReg, reg))
return true;
}
}
}
void LiveIntervals::printRegName(unsigned reg) const {
- if (MRegisterInfo::isPhysicalRegister(reg))
- cerr << mri_->getName(reg);
+ if (TargetRegisterInfo::isPhysicalRegister(reg))
+ cerr << tri_->getName(reg);
else
cerr << "%reg" << reg;
}
interval.addRange(LiveRange(RedefIndex, RedefIndex+1, OldValNo));
DOUT << " RESULT: ";
- interval.print(DOUT, mri_);
+ interval.print(DOUT, tri_);
} else {
// Otherwise, this must be because of phi elimination. If this is the
unsigned Start = getMBBStartIdx(Killer->getParent());
unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
DOUT << " Removing [" << Start << "," << End << "] from: ";
- interval.print(DOUT, mri_); DOUT << "\n";
+ interval.print(DOUT, tri_); DOUT << "\n";
interval.removeRange(Start, End);
interval.addKill(VNI, Start);
VNI->hasPHIKill = true;
- DOUT << " RESULT: "; interval.print(DOUT, mri_);
+ DOUT << " RESULT: "; interval.print(DOUT, tri_);
// Replace the interval with one of a NEW value number. Note that this
// value number isn't actually defined by an instruction, weird huh? :)
DOUT << " replace range with " << LR;
interval.addRange(LR);
interval.addKill(LR.valno, End);
- DOUT << " RESULT: "; interval.print(DOUT, mri_);
+ DOUT << " RESULT: "; interval.print(DOUT, tri_);
}
// In the case of PHI elimination, each variable definition is only
MachineBasicBlock::iterator MI,
unsigned MIIdx,
unsigned reg) {
- if (MRegisterInfo::isVirtualRegister(reg))
+ if (TargetRegisterInfo::isVirtualRegister(reg))
handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
else if (allocatableRegs_[reg]) {
unsigned SrcReg, DstReg;
SrcReg = 0;
handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
// Def of a register also defines its sub-registers.
- for (const unsigned* AS = mri_->getSubRegisters(reg); *AS; ++AS)
+ for (const unsigned* AS = tri_->getSubRegisters(reg); *AS; ++AS)
// Avoid processing some defs more than once.
if (!MI->findRegisterDefOperand(*AS))
handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
LE = MBB->livein_end(); LI != LE; ++LI) {
handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
// Multiple live-ins can alias the same register.
- for (const unsigned* AS = mri_->getSubRegisters(*LI); *AS; ++AS)
+ for (const unsigned* AS = tri_->getSubRegisters(*LI); *AS; ++AS)
if (!hasInterval(*AS))
handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS),
true);
LiveInterval LiveIntervals::createInterval(unsigned reg) {
- float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
+ float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
HUGE_VALF : 0.0F;
return LiveInterval(reg, Weight);
}
if (lv_)
lv_->instructionChanged(MI, fmi);
else
- fmi->copyKillDeadInfo(MI, mri_);
+ fmi->copyKillDeadInfo(MI, tri_);
MachineBasicBlock &MBB = *MI->getParent();
if (isSS && !mf_->getFrameInfo()->isImmutableObjectIndex(Slot))
vrm.virtFolded(Reg, MI, fmi, (VirtRegMap::ModRef)MRInfo);
continue;
unsigned Reg = mop.getReg();
unsigned RegI = Reg;
- if (Reg == 0 || MRegisterInfo::isPhysicalRegister(Reg))
+ if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg))
continue;
if (Reg != li.reg)
continue;
if (!MOj.isRegister())
continue;
unsigned RegJ = MOj.getReg();
- if (RegJ == 0 || MRegisterInfo::isPhysicalRegister(RegJ))
+ if (RegJ == 0 || TargetRegisterInfo::isPhysicalRegister(RegJ))
continue;
if (RegJ == RegI) {
Ops.push_back(j);
}
DOUT << "\t\t\t\tAdded new interval: ";
- nI.print(DOUT, mri_);
+ nI.print(DOUT, tri_);
DOUT << '\n';
}
return CanFold;
"attempt to spill already spilled interval!");
DOUT << "\t\t\t\tadding intervals for spills for interval: ";
- li.print(DOUT, mri_);
+ li.print(DOUT, tri_);
DOUT << '\n';
// Each bit specify whether it a spill is required in the MBB.
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/DepthFirstIterator.h"
}
LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
- assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
+ assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
"getVarInfo: not a virtual register!");
- RegIdx -= MRegisterInfo::FirstVirtualRegister;
+ RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
if (RegIdx >= VirtRegInfo.size()) {
if (RegIdx >= 2*VirtRegInfo.size())
VirtRegInfo.resize(RegIdx*2);
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isKill()) {
if ((MO.getReg() == Reg) ||
- (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- MRegisterInfo::isPhysicalRegister(Reg) &&
+ (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ TargetRegisterInfo::isPhysicalRegister(Reg) &&
RegInfo->isSubRegister(MO.getReg(), Reg)))
return true;
}
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDead()) {
if ((MO.getReg() == Reg) ||
- (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- MRegisterInfo::isPhysicalRegister(Reg) &&
+ (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ TargetRegisterInfo::isPhysicalRegister(Reg) &&
RegInfo->isSubRegister(MO.getReg(), Reg)))
return true;
}
// Mark live-in registers as live-in.
for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
EE = MBB->livein_end(); II != EE; ++II) {
- assert(MRegisterInfo::isPhysicalRegister(*II) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
"Cannot have a live-in virtual register!");
HandlePhysRegDef(*II, 0);
}
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isUse() && MO.getReg()) {
- if (MRegisterInfo::isVirtualRegister(MO.getReg())){
+ if (TargetRegisterInfo::isVirtualRegister(MO.getReg())){
HandleVirtRegUse(MO.getReg(), MBB, MI);
- } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ } else if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
!ReservedRegisters[MO.getReg()]) {
HandlePhysRegUse(MO.getReg(), MI);
}
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDef() && MO.getReg()) {
- if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
VarInfo &VRInfo = getVarInfo(MO.getReg());
if (VRInfo.AliveBlocks.none())
// If vr is not alive in any block, then defaults to dead.
VRInfo.Kills.push_back(MI);
- } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ } else if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
!ReservedRegisters[MO.getReg()]) {
HandlePhysRegDef(MO.getReg(), MI);
}
for (MachineRegisterInfo::liveout_iterator
I = MF->getRegInfo().liveout_begin(),
E = MF->getRegInfo().liveout_end(); I != E; ++I) {
- assert(MRegisterInfo::isPhysicalRegister(*I) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
"Cannot have a live-in virtual register!");
HandlePhysRegUse(*I, Ret);
// Add live-out registers as implicit uses.
for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) {
if (VirtRegInfo[i].Kills[j] == MRI.getVRegDef(i +
- MRegisterInfo::FirstVirtualRegister))
+ TargetRegisterInfo::FirstVirtualRegister))
VirtRegInfo[i].Kills[j]->addRegisterDead(i +
- MRegisterInfo::FirstVirtualRegister,
+ TargetRegisterInfo::FirstVirtualRegister,
RegInfo);
else
VirtRegInfo[i].Kills[j]->addRegisterKilled(i +
- MRegisterInfo::FirstVirtualRegister,
+ TargetRegisterInfo::FirstVirtualRegister,
RegInfo);
}
for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = OldMI->getOperand(i);
if (MO.isRegister() && MO.getReg() &&
- MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
VarInfo &VI = getVarInfo(Reg);
if (MO.isDef()) {
if (MO.isRegister() && MO.isKill()) {
MO.setIsKill(false);
unsigned Reg = MO.getReg();
- if (MRegisterInfo::isVirtualRegister(Reg)) {
+ if (TargetRegisterInfo::isVirtualRegister(Reg)) {
bool removed = getVarInfo(Reg).removeKill(MI);
assert(removed && "kill not in register's VarInfo?");
}
if (MO.isRegister() && MO.isDead()) {
MO.setIsDead(false);
unsigned Reg = MO.getReg();
- if (MRegisterInfo::isVirtualRegister(Reg)) {
+ if (TargetRegisterInfo::isVirtualRegister(Reg)) {
bool removed = getVarInfo(Reg).removeKill(MI);
assert(removed && "kill not in register's VarInfo?");
}
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
// Returns the Register Class of a physical register.
static const TargetRegisterClass *getPhysicalRegisterRegClass(
- const MRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI,
unsigned reg) {
- assert(MRegisterInfo::isPhysicalRegister(reg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(reg) &&
"reg must be a physical register");
// Pick the register class of the right type that contains this physreg.
- for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
- E = MRI.regclass_end(); I != E; ++I)
+ for (TargetRegisterInfo::regclass_iterator I = TRI.regclass_begin(),
+ E = TRI.regclass_end(); I != E; ++I)
if ((*I)->contains(reg))
return *I;
assert(false && "Couldn't find the register class");
bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
- const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
+ const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
unsigned SuperReg = MI->getOperand(1).getReg();
unsigned SubIdx = MI->getOperand(2).getImm();
- assert(MRegisterInfo::isPhysicalRegister(SuperReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
"Extract supperg source must be a physical register");
- unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx);
+ unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
unsigned DstReg = MI->getOperand(0).getReg();
DOUT << "subreg: CONVERTING: " << *MI;
if (SrcReg != DstReg) {
const TargetRegisterClass *TRC = 0;
- if (MRegisterInfo::isPhysicalRegister(DstReg)) {
- TRC = getPhysicalRegisterRegClass(MRI, DstReg);
+ if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
+ TRC = getPhysicalRegisterRegClass(TRI, DstReg);
} else {
TRC = MF.getRegInfo().getRegClass(DstReg);
}
- assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
+ assert(TRC == getPhysicalRegisterRegClass(TRI, SrcReg) &&
"Extract subreg and Dst must be of same register class");
TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
- const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
+ const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
unsigned DstReg = 0;
unsigned SrcReg = 0;
assert(0 && "Malformed extract_subreg");
assert(SubIdx != 0 && "Invalid index for extract_subreg");
- unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx);
+ unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
- assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
"Insert superreg source must be in a physical register");
- assert(MRegisterInfo::isPhysicalRegister(DstReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
"Insert destination must be in a physical register");
- assert(MRegisterInfo::isPhysicalRegister(InsReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
"Inserted value must be in a physical register");
DOUT << "subreg: CONVERTING: " << *MI;
// of the destination, we copy the subreg into the source
// However, this is only safe if the insert instruction is the kill
// of the source register
- bool revCopyOrder = MRI.isSubRegister(DstReg, InsReg);
+ bool revCopyOrder = TRI.isSubRegister(DstReg, InsReg);
if (revCopyOrder && InsReg != DstSubReg) {
if (MI->getOperand(1).isKill()) {
- DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
+ DstSubReg = TRI.getSubReg(SrcReg, SubIdx);
// Insert sub-register copy
const TargetRegisterClass *TRC1 = 0;
- if (MRegisterInfo::isPhysicalRegister(InsReg)) {
- TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
+ if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
+ TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
} else {
TRC1 = MF.getRegInfo().getRegClass(InsReg);
}
if (SrcReg != DstReg) {
// Insert super-register copy
const TargetRegisterClass *TRC0 = 0;
- if (MRegisterInfo::isPhysicalRegister(DstReg)) {
- TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
+ if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
+ TRC0 = getPhysicalRegisterRegClass(TRI, DstReg);
} else {
TRC0 = MF.getRegInfo().getRegClass(DstReg);
}
- assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
+ assert(TRC0 == getPhysicalRegisterRegClass(TRI, SrcReg) &&
"Insert superreg and Dst must be of same register class");
TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
if (!revCopyOrder && InsReg != DstSubReg) {
// Insert sub-register copy
const TargetRegisterClass *TRC1 = 0;
- if (MRegisterInfo::isPhysicalRegister(InsReg)) {
- TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
+ if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
+ TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
} else {
TRC1 = MF.getRegInfo().getRegClass(InsReg);
}
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/BasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetInstrDesc.h"
#include "llvm/Target/TargetMachine.h"
}
static inline void OutputReg(std::ostream &os, unsigned RegNo,
- const MRegisterInfo *MRI = 0) {
- if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
- if (MRI)
- os << " %" << MRI->get(RegNo).Name;
+ const TargetRegisterInfo *TRI = 0) {
+ if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo)) {
+ if (TRI)
+ os << " %" << TRI->get(RegNo).Name;
else
os << " %mreg(" << RegNo << ")";
} else
if (isLandingPad()) OS << ", EH LANDING PAD";
OS << ":\n";
- const MRegisterInfo *MRI = MF->getTarget().getRegisterInfo();
+ const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
if (!livein_empty()) {
OS << "Live Ins:";
for (const_livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
- OutputReg(OS, *I, MRI);
+ OutputReg(OS, *I, TRI);
OS << "\n";
}
// Print the preds of this block according to the CFG.
// Print Constant Pool
getConstantPool()->print(OS);
- const MRegisterInfo *MRI = getTarget().getRegisterInfo();
+ const TargetRegisterInfo *TRI = getTarget().getRegisterInfo();
if (!RegInfo->livein_empty()) {
OS << "Live Ins:";
for (MachineRegisterInfo::livein_iterator
I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
- if (MRI)
- OS << " " << MRI->getName(I->first);
+ if (TRI)
+ OS << " " << TRI->getName(I->first);
else
OS << " Reg #" << I->first;
OS << "Live Outs:";
for (MachineRegisterInfo::liveout_iterator
I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I)
- if (MRI)
- OS << " " << MRI->getName(*I);
+ if (TRI)
+ OS << " " << TRI->getName(*I);
else
OS << " Reg #" << *I;
OS << "\n";
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetInstrDesc.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/LeakDetector.h"
#include "llvm/Support/Streams.h"
#include <ostream>
void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
switch (getType()) {
case MachineOperand::MO_Register:
- if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
+ if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
OS << "%reg" << getReg();
} else {
// If the instruction is embedded into a basic block, we can find the
}
bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
- const MRegisterInfo *RegInfo,
+ const TargetRegisterInfo *RegInfo,
bool AddIfNotFound) {
bool Found = false;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MO.setIsKill();
Found = true;
break;
- } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
- MRegisterInfo::isPhysicalRegister(IncomingReg) &&
+ } else if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
+ TargetRegisterInfo::isPhysicalRegister(IncomingReg) &&
RegInfo->isSuperRegister(IncomingReg, Reg) &&
MO.isKill())
// A super-register kill already exists.
}
bool MachineInstr::addRegisterDead(unsigned IncomingReg,
- const MRegisterInfo *RegInfo,
+ const TargetRegisterInfo *RegInfo,
bool AddIfNotFound) {
bool Found = false;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MO.setIsDead();
Found = true;
break;
- } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
- MRegisterInfo::isPhysicalRegister(IncomingReg) &&
+ } else if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
+ TargetRegisterInfo::isPhysicalRegister(IncomingReg) &&
RegInfo->isSuperRegister(IncomingReg, Reg) &&
MO.isDead())
// There exists a super-register that's marked dead.
/// copyKillDeadInfo - copies killed/dead information from one instr to another
void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
- const MRegisterInfo *RegInfo) {
+ const TargetRegisterInfo *RegInfo) {
// If the instruction defines any virtual registers, update the VarInfo,
// kill and dead information for the instruction.
for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = OldMI->getOperand(i);
if (MO.isRegister() && MO.getReg() &&
- MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (MO.isDef()) {
if (MO.isDead()) {
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/SmallVector.h"
if (I.getDesc().getImplicitUses()) {
DOUT << " * Instruction has implicit uses:\n";
- const MRegisterInfo *MRI = TM->getRegisterInfo();
+ const TargetRegisterInfo *TRI = TM->getRegisterInfo();
for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
*ImpUses; ++ImpUses)
- DOUT << " -> " << MRI->getName(*ImpUses) << "\n";
+ DOUT << " -> " << TRI->getName(*ImpUses) << "\n";
}
if (I.getDesc().getImplicitDefs()) {
DOUT << " * Instruction has implicit defines:\n";
- const MRegisterInfo *MRI = TM->getRegisterInfo();
+ const TargetRegisterInfo *TRI = TM->getRegisterInfo();
for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
*ImpDefs; ++ImpDefs)
- DOUT << " -> " << MRI->getName(*ImpDefs) << "\n";
+ DOUT << " -> " << TRI->getName(*ImpDefs) << "\n";
}
//if (TII->hasUnmodelledSideEffects(&I))
unsigned Reg = MO.getReg();
// Don't hoist instructions that access physical registers.
- if (!MRegisterInfo::isVirtualRegister(Reg))
+ if (!TargetRegisterInfo::isVirtualRegister(Reg))
return false;
assert(RegInfo->getVRegDef(Reg)&&"Machine instr not mapped for this vreg?");
#include "llvm/CodeGen/MachineRegisterInfo.h"
using namespace llvm;
-MachineRegisterInfo::MachineRegisterInfo(const MRegisterInfo &MRI) {
+MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
VRegInfo.reserve(256);
- UsedPhysRegs.resize(MRI.getNumRegs());
+ UsedPhysRegs.resize(TRI.getNumRegs());
// Create the physreg use/def lists.
- PhysRegUseDefLists = new MachineOperand*[MRI.getNumRegs()];
- memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*MRI.getNumRegs());
+ PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
+ memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
}
MachineRegisterInfo::~MachineRegisterInfo() {
/// register or null if none is found. This assumes that the code is in SSA
/// form, so there should only be one definition.
MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
- assert(Reg-MRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
+ assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
"Invalid vreg!");
for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
// Since we are in SSA form, we can stop at the first definition.
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/SmallVector.h"
/// occur in blocks dominated by the specified block.
bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
MachineBasicBlock *MBB) const {
- assert(MRegisterInfo::isVirtualRegister(Reg) && "Only makes sense for vregs");
+ assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
+ "Only makes sense for vregs");
for (MachineRegisterInfo::reg_iterator I = RegInfo->reg_begin(Reg),
E = RegInfo->reg_end(); I != E; ++I) {
if (I.getOperand().isDef()) continue; // ignore def.
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
- if (MRegisterInfo::isPhysicalRegister(Reg)) {
+ if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
// If this is a physical register use, we can't move it. If it is a def,
// we can move it, but only if the def is dead.
if (MO.isUse() || !MO.isDead())
std::set<MachineBasicBlock*> MBBsInsertedInto;
for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) {
unsigned SrcReg = MPhi->getOperand(i-1).getReg();
- assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
"Machine PHI Operands must all be virtual registers!");
// Get the MachineBasicBlock equivalent of the BasicBlock that is the
#ifndef LLVM_CODEGEN_PHYSREGTRACKER_H
#define LLVM_CODEGEN_PHYSREGTRACKER_H
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
namespace llvm {
class PhysRegTracker {
- const MRegisterInfo* mri_;
+ const TargetRegisterInfo* tri_;
std::vector<unsigned> regUse_;
public:
- explicit PhysRegTracker(const MRegisterInfo& mri)
- : mri_(&mri),
- regUse_(mri_->getNumRegs(), 0) {
+ explicit PhysRegTracker(const TargetRegisterInfo& tri)
+ : tri_(&tri),
+ regUse_(tri_->getNumRegs(), 0) {
}
PhysRegTracker(const PhysRegTracker& rhs)
- : mri_(rhs.mri_),
+ : tri_(rhs.tri_),
regUse_(rhs.regUse_) {
}
const PhysRegTracker& operator=(const PhysRegTracker& rhs) {
- mri_ = rhs.mri_;
+ tri_ = rhs.tri_;
regUse_ = rhs.regUse_;
return *this;
}
void addRegUse(unsigned physReg) {
- assert(MRegisterInfo::isPhysicalRegister(physReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
"should be physical register!");
++regUse_[physReg];
- for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as)
+ for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
++regUse_[*as];
}
void delRegUse(unsigned physReg) {
- assert(MRegisterInfo::isPhysicalRegister(physReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
"should be physical register!");
assert(regUse_[physReg] != 0);
--regUse_[physReg];
- for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
+ for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
assert(regUse_[*as] != 0);
--regUse_[*as];
}
}
bool isRegAvail(unsigned physReg) const {
- assert(MRegisterInfo::isPhysicalRegister(physReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
"should be physical register!");
return regUse_[physReg] == 0;
}
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Compiler.h"
/// frame indexes with appropriate references.
///
bool runOnMachineFunction(MachineFunction &Fn) {
- const MRegisterInfo *MRI = Fn.getTarget().getRegisterInfo();
- RS = MRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
+ const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
+ RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
// Get MachineModuleInfo so that we can track the construction of the
// frame.
// Allow the target machine to make some adjustments to the function
// e.g. UsedPhysRegs before calculateCalleeSavedRegisters.
- MRI->processFunctionBeforeCalleeSavedScan(Fn, RS);
+ TRI->processFunctionBeforeCalleeSavedScan(Fn, RS);
// Scan the function for modified callee saved registers and insert spill
// code for any callee saved registers that are modified. Also calculate
/// instructions.
///
void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
- const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
+ const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
// Get the callee saved register list...
// Make sure the special register scavenging spill slot is closest to the
// frame pointer if a frame pointer is required.
- const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
+ const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
if (RS && RegInfo->hasFP(Fn)) {
int SFI = RS->getScavengingFrameIndex();
if (SFI >= 0) {
const TargetMachine &TM = Fn.getTarget();
assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
- const MRegisterInfo &MRI = *TM.getRegisterInfo();
+ const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
const TargetFrameInfo *TFI = TM.getFrameInfo();
bool StackGrowsDown =
TFI->getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
- int FrameSetupOpcode = MRI.getCallFrameSetupOpcode();
- int FrameDestroyOpcode = MRI.getCallFrameDestroyOpcode();
+ int FrameSetupOpcode = TRI.getCallFrameSetupOpcode();
+ int FrameDestroyOpcode = TRI.getCallFrameDestroyOpcode();
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
int SPAdj = 0; // SP offset due to call frame setup / destroy.
Size = -Size;
SPAdj += Size;
MachineBasicBlock::iterator PrevI = prior(I);
- MRI.eliminateCallFramePseudoInstr(Fn, *BB, I);
+ TRI.eliminateCallFramePseudoInstr(Fn, *BB, I);
// Visit the instructions created by eliminateCallFramePseudoInstr().
I = next(PrevI);
MI = NULL;
if (MI->getOperand(i).isFrameIndex()) {
// If this instruction has a FrameIndex operand, we need to use that
// target machine register info object to eliminate it.
- MRI.eliminateFrameIndex(MI, SPAdj, RS);
+ TRI.eliminateFrameIndex(MI, SPAdj, RS);
// Revisit the instruction in full. Some instructions (e.g. inline
// asm instructions) can have multiple frame indices.
/// RegInfo - For dealing with machine register info (aliases, folds
/// etc)
- const MRegisterInfo *RegInfo;
+ const TargetRegisterInfo *RegInfo;
typedef SmallVector<unsigned, 2> VRegTimes;
/// markVirtRegModified - Lets us flip bits in the VirtRegModified bitset
///
void markVirtRegModified(unsigned Reg, bool Val = true) {
- assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
- Reg -= MRegisterInfo::FirstVirtualRegister;
+ assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
+ Reg -= TargetRegisterInfo::FirstVirtualRegister;
if (VirtRegModified.size() <= Reg)
VirtRegModified.resize(Reg+1);
VirtRegModified[Reg] = Val;
/// isVirtRegModified - Lets us query the VirtRegModified bitset
///
bool isVirtRegModified(unsigned Reg) const {
- assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
- assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
+ assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
+ assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
&& "Illegal virtual register!");
- return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister];
+ return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
}
public:
MachineOperand& MO = MI->getOperand(i);
// look for vreg reads..
if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
- MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
// ..and add them to the read table.
VRegTimes* &Times = VRegReadTable[MO.getReg()];
if(!VRegReadTable[MO.getReg()]) {
MachineOperand& MO = MI->getOperand(i);
// here we are looking for only used operands (never def&use)
if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
- MRegisterInfo::isVirtualRegister(MO.getReg()))
+ TargetRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i);
}
for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
unsigned VirtReg = Kills[i];
unsigned PhysReg = VirtReg;
- if (MRegisterInfo::isVirtualRegister(VirtReg)) {
+ if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
// If the virtual register was never materialized into a register, it
// might not be in the map, but it won't hurt to zero it out anyway.
unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
- MRegisterInfo::isPhysicalRegister(MO.getReg())) {
+ TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
// These are extra physical register defs when a sub-register
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDef() && MO.getReg() &&
- MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned DestVirtReg = MO.getReg();
unsigned DestPhysReg;
for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
unsigned VirtReg = DeadDefs[i];
unsigned PhysReg = VirtReg;
- if (MRegisterInfo::isVirtualRegister(VirtReg)) {
+ if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
PhysReg = PhysRegSlot;
assert(PhysReg != 0);
Virt2PhysRegMap.grow(MF->getRegInfo().getLastVirtReg());
StackSlotForVirtReg.grow(MF->getRegInfo().getLastVirtReg());
VirtRegModified.resize(MF->getRegInfo().getLastVirtReg() -
- MRegisterInfo::FirstVirtualRegister + 1, 0);
+ TargetRegisterInfo::FirstVirtualRegister + 1, 0);
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterCoalescer.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/EquivalenceClasses.h"
MachineFunction* mf_;
const TargetMachine* tm_;
- const MRegisterInfo* mri_;
+ const TargetRegisterInfo* tri_;
const TargetInstrInfo* tii_;
MachineRegisterInfo *reginfo_;
BitVector allocatableRegs_;
for (; i != e; ++i) {
DOUT << "\t" << *i->first << " -> ";
unsigned reg = i->first->reg;
- if (MRegisterInfo::isVirtualRegister(reg)) {
+ if (TargetRegisterInfo::isVirtualRegister(reg)) {
reg = vrm_->getPhys(reg);
}
- DOUT << mri_->getName(reg) << '\n';
+ DOUT << tri_->getName(reg) << '\n';
}
}
};
}
void RALinScan::ComputeRelatedRegClasses() {
- const MRegisterInfo &MRI = *mri_;
+ const TargetRegisterInfo &TRI = *tri_;
// First pass, add all reg classes to the union, and determine at least one
// reg class that each register is in.
bool HasAliases = false;
- for (MRegisterInfo::regclass_iterator RCI = MRI.regclass_begin(),
- E = MRI.regclass_end(); RCI != E; ++RCI) {
+ for (TargetRegisterInfo::regclass_iterator RCI = TRI.regclass_begin(),
+ E = TRI.regclass_end(); RCI != E; ++RCI) {
RelatedRegClasses.insert(*RCI);
for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
I != E; ++I) {
- HasAliases = HasAliases || *MRI.getAliasSet(*I) != 0;
+ HasAliases = HasAliases || *TRI.getAliasSet(*I) != 0;
const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
if (PRC) {
for (std::map<unsigned, const TargetRegisterClass*>::iterator
I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
I != E; ++I)
- for (const unsigned *AS = MRI.getAliasSet(I->first); *AS; ++AS)
+ for (const unsigned *AS = TRI.getAliasSet(I->first); *AS; ++AS)
RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
}
unsigned SrcReg, DstReg;
if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg))
return Reg;
- if (MRegisterInfo::isVirtualRegister(SrcReg))
+ if (TargetRegisterInfo::isVirtualRegister(SrcReg))
if (!vrm_->isAssignedReg(SrcReg))
return Reg;
else
// Try to coalesce.
if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
- DOUT << "Coalescing: " << cur << " -> " << mri_->getName(SrcReg) << '\n';
+ DOUT << "Coalescing: " << cur << " -> " << tri_->getName(SrcReg) << '\n';
vrm_->clearVirt(cur.reg);
vrm_->assignVirt2Phys(cur.reg, SrcReg);
++NumCoalesce;
bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
mf_ = &fn;
tm_ = &fn.getTarget();
- mri_ = tm_->getRegisterInfo();
+ tri_ = tm_->getRegisterInfo();
tii_ = tm_->getInstrInfo();
reginfo_ = &mf_->getRegInfo();
- allocatableRegs_ = mri_->getAllocatableSet(fn);
+ allocatableRegs_ = tri_->getAllocatableSet(fn);
li_ = &getAnalysis<LiveIntervals>();
loopInfo = &getAnalysis<MachineLoopInfo>();
if (RelatedRegClasses.empty())
ComputeRelatedRegClasses();
- if (!prt_.get()) prt_.reset(new PhysRegTracker(*mri_));
+ if (!prt_.get()) prt_.reset(new PhysRegTracker(*tri_));
vrm_.reset(new VirtRegMap(*mf_));
if (!spiller_.get()) spiller_.reset(createSpiller());
"interval sets should be empty on initialization");
for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
- if (MRegisterInfo::isPhysicalRegister(i->second.reg)) {
+ if (TargetRegisterInfo::isPhysicalRegister(i->second.reg)) {
reginfo_->setPhysRegUsed(i->second.reg);
fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
} else
processActiveIntervals(cur->beginNumber());
processInactiveIntervals(cur->beginNumber());
- assert(MRegisterInfo::isVirtualRegister(cur->reg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
"Can only allocate virtual registers!");
// Allocating a virtual register. try to find a free
IntervalPtr &IP = active_.back();
unsigned reg = IP.first->reg;
DOUT << "\tinterval " << *IP.first << " expired\n";
- assert(MRegisterInfo::isVirtualRegister(reg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->delRegUse(reg);
for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
LiveInterval &cur = i->second;
unsigned Reg = 0;
- bool isPhys = MRegisterInfo::isPhysicalRegister(cur.reg);
+ bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
if (isPhys)
Reg = i->second.reg;
else if (vrm_->isAssignedReg(cur.reg))
if (IntervalPos == Interval->end()) { // Remove expired intervals.
DOUT << "\t\tinterval " << *Interval << " expired\n";
- assert(MRegisterInfo::isVirtualRegister(reg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->delRegUse(reg);
} else if (IntervalPos->start > CurPoint) {
// Move inactive intervals to inactive list.
DOUT << "\t\tinterval " << *Interval << " inactive\n";
- assert(MRegisterInfo::isVirtualRegister(reg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->delRegUse(reg);
} else if (IntervalPos->start <= CurPoint) {
// move re-activated intervals in active list
DOUT << "\t\tinterval " << *Interval << " active\n";
- assert(MRegisterInfo::isVirtualRegister(reg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->addRegUse(reg);
/// register and its weight.
static void updateSpillWeights(std::vector<float> &Weights,
unsigned reg, float weight,
- const MRegisterInfo *MRI) {
+ const TargetRegisterInfo *TRI) {
Weights[reg] += weight;
- for (const unsigned* as = MRI->getAliasSet(reg); *as; ++as)
+ for (const unsigned* as = TRI->getAliasSet(reg); *as; ++as)
Weights[*as] += weight;
}
unsigned SrcReg, DstReg;
if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
unsigned Reg = 0;
- if (MRegisterInfo::isPhysicalRegister(SrcReg))
+ if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
Reg = SrcReg;
else if (vrm_->isAssignedReg(SrcReg))
Reg = vrm_->getPhys(SrcReg);
for (IntervalPtrs::const_iterator i = inactive_.begin(),
e = inactive_.end(); i != e; ++i) {
unsigned Reg = i->first->reg;
- assert(MRegisterInfo::isVirtualRegister(Reg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
"Can only allocate virtual registers!");
const TargetRegisterClass *RegRC = reginfo_->getRegClass(Reg);
// If this is not in a related reg class to the register we're allocating,
// conflict with it. Check to see if we conflict with it or any of its
// aliases.
SmallSet<unsigned, 8> RegAliases;
- for (const unsigned *AS = mri_->getAliasSet(physReg); *AS; ++AS)
+ for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
RegAliases.insert(*AS);
bool ConflictsWithFixed = false;
// the free physical register and add this interval to the active
// list.
if (physReg) {
- DOUT << mri_->getName(physReg) << '\n';
+ DOUT << tri_->getName(physReg) << '\n';
vrm_->assignVirt2Phys(cur->reg, physReg);
prt_->addRegUse(physReg);
active_.push_back(std::make_pair(cur, cur->begin()));
DOUT << "no free registers\n";
// Compile the spill weights into an array that is better for scanning.
- std::vector<float> SpillWeights(mri_->getNumRegs(), 0.0);
+ std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0);
for (std::vector<std::pair<unsigned, float> >::iterator
I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
- updateSpillWeights(SpillWeights, I->first, I->second, mri_);
+ updateSpillWeights(SpillWeights, I->first, I->second, tri_);
// for each interval in active, update spill weights.
for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
i != e; ++i) {
unsigned reg = i->first->reg;
- assert(MRegisterInfo::isVirtualRegister(reg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
- updateSpillWeights(SpillWeights, reg, i->first->weight, mri_);
+ updateSpillWeights(SpillWeights, reg, i->first->weight, tri_);
}
DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
unsigned reg = *i;
// No need to worry about if the alias register size < regsize of RC.
// We are going to spill all registers that alias it anyway.
- for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as) {
+ for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
if (minWeight > SpillWeights[*as]) {
minWeight = SpillWeights[*as];
minReg = *as;
}
DOUT << "\t\tregister with min weight: "
- << mri_->getName(minReg) << " (" << minWeight << ")\n";
+ << tri_->getName(minReg) << " (" << minWeight << ")\n";
// if the current has the minimum weight, we need to spill it and
// add any added intervals back to unhandled, and restart
// minimum weight, rollback to the interval with the earliest
// start point and let the linear scan algorithm run again
std::vector<LiveInterval*> added;
- assert(MRegisterInfo::isPhysicalRegister(minReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
"did not choose a register to spill?");
- BitVector toSpill(mri_->getNumRegs());
+ BitVector toSpill(tri_->getNumRegs());
// We are going to spill minReg and all its aliases.
toSpill[minReg] = true;
- for (const unsigned* as = mri_->getAliasSet(minReg); *as; ++as)
+ for (const unsigned* as = tri_->getAliasSet(minReg); *as; ++as)
toSpill[*as] = true;
// the earliest start of a spilled interval indicates up to where
// mark our rollback point.
for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
unsigned reg = i->first->reg;
- if (//MRegisterInfo::isVirtualRegister(reg) &&
+ if (//TargetRegisterInfo::isVirtualRegister(reg) &&
toSpill[vrm_->getPhys(reg)] &&
cur->overlapsFrom(*i->first, i->second)) {
DOUT << "\t\t\tspilling(a): " << *i->first << '\n';
}
for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
unsigned reg = i->first->reg;
- if (//MRegisterInfo::isVirtualRegister(reg) &&
+ if (//TargetRegisterInfo::isVirtualRegister(reg) &&
toSpill[vrm_->getPhys(reg)] &&
cur->overlapsFrom(*i->first, i->second-1)) {
DOUT << "\t\t\tspilling(i): " << *i->first << '\n';
IntervalPtrs::iterator it;
if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
active_.erase(it);
- assert(!MRegisterInfo::isPhysicalRegister(i->reg));
+ assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
if (!spilled.count(i->reg))
unhandled_.push(i);
prt_->delRegUse(vrm_->getPhys(i->reg));
vrm_->clearVirt(i->reg);
} else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
inactive_.erase(it);
- assert(!MRegisterInfo::isPhysicalRegister(i->reg));
+ assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
if (!spilled.count(i->reg))
unhandled_.push(i);
vrm_->clearVirt(i->reg);
} else {
- assert(MRegisterInfo::isVirtualRegister(i->reg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
"Can only allocate virtual registers!");
vrm_->clearVirt(i->reg);
unhandled_.push(i);
HI->expiredAt(cur->beginNumber())) {
DOUT << "\t\t\tundo changes for: " << *HI << '\n';
active_.push_back(std::make_pair(HI, HI->begin()));
- assert(!MRegisterInfo::isPhysicalRegister(HI->reg));
+ assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
prt_->addRegUse(vrm_->getPhys(HI->reg));
}
}
/// getFreePhysReg - return a free physical register for this virtual register
/// interval if we have one, otherwise return 0.
unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
- std::vector<unsigned> inactiveCounts(mri_->getNumRegs(), 0);
+ std::vector<unsigned> inactiveCounts(tri_->getNumRegs(), 0);
unsigned MaxInactiveCount = 0;
const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
i != e; ++i) {
unsigned reg = i->first->reg;
- assert(MRegisterInfo::isVirtualRegister(reg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
// If this is not in a related reg class to the register we're allocating,
if (cur->preference)
if (prt_->isRegAvail(cur->preference)) {
DOUT << "\t\tassigned the preferred register: "
- << mri_->getName(cur->preference) << "\n";
+ << tri_->getName(cur->preference) << "\n";
return cur->preference;
} else
DOUT << "\t\tunable to assign the preferred register: "
- << mri_->getName(cur->preference) << "\n";
+ << tri_->getName(cur->preference) << "\n";
// Scan for the first available register.
TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
private:
const TargetMachine *TM;
MachineFunction *MF;
- const MRegisterInfo *MRI;
+ const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
// StackSlotForVirtReg - Maps virtual regs to the frame index where these
Virt2LastUseMap;
std::pair<MachineInstr*,unsigned>& getVirtRegLastUse(unsigned Reg) {
- assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
+ assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
return Virt2LastUseMap[Reg];
}
BitVector VirtRegModified;
void markVirtRegModified(unsigned Reg, bool Val = true) {
- assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
- Reg -= MRegisterInfo::FirstVirtualRegister;
+ assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
+ Reg -= TargetRegisterInfo::FirstVirtualRegister;
if (Val)
VirtRegModified.set(Reg);
else
}
bool isVirtRegModified(unsigned Reg) const {
- assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
- assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
+ assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
+ assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
&& "Illegal virtual register!");
- return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister];
+ return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
}
void AddToPhysRegsUseOrder(unsigned Reg) {
///
bool areRegsEqual(unsigned R1, unsigned R2) const {
if (R1 == R2) return true;
- for (const unsigned *AliasSet = MRI->getAliasSet(R2);
+ for (const unsigned *AliasSet = TRI->getAliasSet(R2);
*AliasSet; ++AliasSet) {
if (*AliasSet == R1) return true;
}
assert(VirtReg && "Spilling a physical register is illegal!"
" Must not have appropriate kill for the register or use exists beyond"
" the intended one.");
- DOUT << " Spilling register " << MRI->getName(PhysReg)
+ DOUT << " Spilling register " << TRI->getName(PhysReg)
<< " containing %reg" << VirtReg;
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
} else {
// If the selected register aliases any other registers, we must make
// sure that one of the aliases isn't alive.
- for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg);
+ for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
*AliasSet; ++AliasSet)
if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
PhysRegsUsed[*AliasSet] != -2) // If allocatable.
// If the selected register aliases any other allocated registers, it is
// not free!
- for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg);
+ for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
*AliasSet; ++AliasSet)
if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use?
return false; // Can't use this reg then.
} else {
// If one of the registers aliased to the current register is
// compatible, use it.
- for (const unsigned *AliasIt = MRI->getAliasSet(R);
+ for (const unsigned *AliasIt = TRI->getAliasSet(R);
*AliasIt; ++AliasIt) {
if (RC->contains(*AliasIt) &&
// If this is pinned down for some reason, don't use it. For
markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
DOUT << " Reloading %reg" << VirtReg << " into "
- << MRI->getName(PhysReg) << "\n";
+ << TRI->getName(PhysReg) << "\n";
// Add move instruction(s)
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
MF->getRegInfo().setPhysRegUsed(Reg);
PhysRegsUsed[Reg] = 0; // It is free and reserved now
AddToPhysRegsUseOrder(Reg);
- for (const unsigned *AliasSet = MRI->getSubRegisters(Reg);
+ for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
AddToPhysRegsUseOrder(*AliasSet);
const TargetInstrDesc &TID = MI->getDesc();
DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
DOUT << " Regs have values: ";
- for (unsigned i = 0; i != MRI->getNumRegs(); ++i)
+ for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
- DOUT << "[" << MRI->getName(i)
+ DOUT << "[" << TRI->getName(i)
<< ",%reg" << PhysRegsUsed[i] << "] ";
DOUT << "\n");
MachineOperand& MO = MI->getOperand(i);
// here we are looking for only used operands (never def&use)
if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
- MRegisterInfo::isVirtualRegister(MO.getReg()))
+ TargetRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i);
}
for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
unsigned VirtReg = Kills[i];
unsigned PhysReg = VirtReg;
- if (MRegisterInfo::isVirtualRegister(VirtReg)) {
+ if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
// If the virtual register was never materialized into a register, it
// might not be in the map, but it won't hurt to zero it out anyway.
unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
}
if (PhysReg) {
- DOUT << " Last use of " << MRI->getName(PhysReg)
+ DOUT << " Last use of " << TRI->getName(PhysReg)
<< "[%reg" << VirtReg <<"], removing it from live set\n";
removePhysReg(PhysReg);
- for (const unsigned *AliasSet = MRI->getSubRegisters(PhysReg);
+ for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
DOUT << " Last use of "
- << MRI->getName(*AliasSet)
+ << TRI->getName(*AliasSet)
<< "[%reg" << VirtReg <<"], removing it from live set\n";
removePhysReg(*AliasSet);
}
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
- MRegisterInfo::isPhysicalRegister(MO.getReg())) {
+ TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
// These are extra physical register defs when a sub-register
PhysRegsUsed[Reg] = 0; // It is free and reserved now
AddToPhysRegsUseOrder(Reg);
- for (const unsigned *AliasSet = MRI->getSubRegisters(Reg);
+ for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
MF->getRegInfo().setPhysRegUsed(*AliasSet);
PhysRegsUsed[Reg] = 0; // It is free and reserved now
}
MF->getRegInfo().setPhysRegUsed(Reg);
- for (const unsigned *AliasSet = MRI->getSubRegisters(Reg);
+ for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
AddToPhysRegsUseOrder(*AliasSet);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDef() && MO.getReg() &&
- MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned DestVirtReg = MO.getReg();
unsigned DestPhysReg;
for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
unsigned VirtReg = DeadDefs[i];
unsigned PhysReg = VirtReg;
- if (MRegisterInfo::isVirtualRegister(VirtReg)) {
+ if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
PhysReg = PhysRegSlot;
assert(PhysReg != 0);
}
if (PhysReg) {
- DOUT << " Register " << MRI->getName(PhysReg)
+ DOUT << " Register " << TRI->getName(PhysReg)
<< " [%reg" << VirtReg
<< "] is never used, removing it frame live list\n";
removePhysReg(PhysReg);
- for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg);
+ for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
- DOUT << " Register " << MRI->getName(*AliasSet)
+ DOUT << " Register " << TRI->getName(*AliasSet)
<< " [%reg" << *AliasSet
<< "] is never used, removing it frame live list\n";
removePhysReg(*AliasSet);
MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
// Spill all physical registers holding virtual registers now.
- for (unsigned i = 0, e = MRI->getNumRegs(); i != e; ++i)
+ for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
if (unsigned VirtReg = PhysRegsUsed[i])
spillVirtReg(MBB, MI, VirtReg, i);
#if 0
// This checking code is very expensive.
bool AllOk = true;
- for (unsigned i = MRegisterInfo::FirstVirtualRegister,
+ for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
if (unsigned PR = Virt2PhysRegMap[i]) {
cerr << "Register still mapped: " << i << " -> " << PR << "\n";
DOUT << "Machine Function " << "\n";
MF = &Fn;
TM = &Fn.getTarget();
- MRI = TM->getRegisterInfo();
+ TRI = TM->getRegisterInfo();
TII = TM->getInstrInfo();
- PhysRegsUsed.assign(MRI->getNumRegs(), -1);
+ PhysRegsUsed.assign(TRI->getNumRegs(), -1);
// At various places we want to efficiently check to see whether a register
// is allocatable. To handle this, we mark all unallocatable registers as
// being pinned down, permanently.
{
- BitVector Allocable = MRI->getAllocatableSet(Fn);
+ BitVector Allocable = TRI->getAllocatableSet(Fn);
for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
if (!Allocable[i])
PhysRegsUsed[i] = -2; // Mark the reg unallocable.
unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
Virt2PhysRegMap.grow(LastVirtReg);
Virt2LastUseMap.grow(LastVirtReg);
- VirtRegModified.resize(LastVirtReg+1-MRegisterInfo::FirstVirtualRegister);
+ VirtRegModified.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
private:
MachineFunction *MF;
const TargetMachine *TM;
- const MRegisterInfo *MRI;
+ const TargetRegisterInfo *TRI;
// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
// these values are spilled
// Made to combat the incorrect allocation of r2 = add r1, r1
std::map<unsigned, unsigned> Virt2PhysRegMap;
- RegsUsed.resize(MRI->getNumRegs());
+ RegsUsed.resize(TRI->getNumRegs());
// This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses).
MachineOperand &op = MI->getOperand(i);
if (op.isRegister() && op.getReg() &&
- MRegisterInfo::isVirtualRegister(op.getReg())) {
+ TargetRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getReg();
DOUT << "op: " << op << "\n";
DOUT << "\t inst[" << i << "]: ";
DOUT << "Machine Function\n";
MF = &Fn;
TM = &MF->getTarget();
- MRI = TM->getRegisterInfo();
+ TRI = TM->getRegisterInfo();
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
#include "llvm/CodeGen/RegisterCoalescer.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Pass.h"
using namespace llvm;
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
CCState::CCState(unsigned CC, bool isVarArg, const TargetMachine &tm,
SmallVector<CCValAssign, 16> &locs)
: CallingConv(CC), IsVarArg(isVarArg), TM(tm),
- MRI(*TM.getRegisterInfo()), Locs(locs) {
+ TRI(*TM.getRegisterInfo()), Locs(locs) {
// No stack is used.
StackOffset = 0;
- UsedRegs.resize(MRI.getNumRegs());
+ UsedRegs.resize(TRI.getNumRegs());
}
// HandleByVal - Allocate a stack slot large enough to pass an argument by
void CCState::MarkAllocated(unsigned Reg) {
UsedRegs[Reg/32] |= 1 << (Reg&31);
- if (const unsigned *RegAliases = MRI.getAliasSet(Reg))
+ if (const unsigned *RegAliases = TRI.getAliasSet(Reg))
for (; (Reg = *RegAliases); ++RegAliases)
UsedRegs[Reg/32] |= 1 << (Reg&31);
}
: DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) {
TII = TM.getInstrInfo();
MF = &DAG.getMachineFunction();
- MRI = TM.getRegisterInfo();
+ TRI = TM.getRegisterInfo();
ConstPool = BB->getParent()->getConstantPool();
}
/// a specified operand is a physical register dependency. If so, returns the
/// register and the cost of copying the register.
static void CheckForPhysRegDependency(SDNode *Def, SDNode *Use, unsigned Op,
- const MRegisterInfo *MRI,
+ const TargetRegisterInfo *TRI,
const TargetInstrInfo *TII,
unsigned &PhysReg, int &Cost) {
if (Op != 2 || Use->getOpcode() != ISD::CopyToReg)
return;
unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
- if (MRegisterInfo::isVirtualRegister(Reg))
+ if (TargetRegisterInfo::isVirtualRegister(Reg))
return;
unsigned ResNo = Use->getOperand(2).ResNo;
II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
PhysReg = Reg;
const TargetRegisterClass *RC =
- MRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg);
+ TRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg);
Cost = RC->getCopyCost();
}
}
unsigned PhysReg = 0;
int Cost = 1;
// Determine if this is a physical register dependency.
- CheckForPhysRegDependency(OpN, N, i, MRI, TII, PhysReg, Cost);
+ CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
SU->addPred(OpSU, isChain, false, PhysReg, Cost);
}
}
}
static const TargetRegisterClass *getInstrOperandRegClass(
- const MRegisterInfo *MRI,
+ const TargetRegisterInfo *TRI,
const TargetInstrInfo *TII,
const TargetInstrDesc &II,
unsigned Op) {
}
if (II.OpInfo[Op].isLookupPtrRegClass())
return TII->getPointerRegClass();
- return MRI->getRegClass(II.OpInfo[Op].RegClass);
+ return TRI->getRegClass(II.OpInfo[Op].RegClass);
}
void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
unsigned InstanceNo, unsigned SrcReg,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
unsigned VRBase = 0;
- if (MRegisterInfo::isVirtualRegister(SrcReg)) {
+ if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
// Just use the input register directly!
if (InstanceNo > 0)
VRBaseMap.erase(SDOperand(Node, ResNo));
Use->getOperand(2).Val == Node &&
Use->getOperand(2).ResNo == ResNo) {
unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
- if (MRegisterInfo::isVirtualRegister(DestReg)) {
+ if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
VRBase = DestReg;
Match = false;
} else if (DestReg != SrcReg)
if (VRBase)
TRC = RegInfo.getRegClass(VRBase);
else
- TRC = MRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg);
+ TRC = TRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg);
// If all uses are reading from the src physical register and copying the
// register is either impossible or very expensive, then don't create a copy.
Use->getOperand(2).Val == Node &&
Use->getOperand(2).ResNo == i) {
unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
- if (MRegisterInfo::isVirtualRegister(Reg)) {
+ if (TargetRegisterInfo::isVirtualRegister(Reg)) {
VRBase = Reg;
MI->addOperand(MachineOperand::CreateReg(Reg, true));
break;
// Create the result registers for this node and add the result regs to
// the machine instruction.
if (VRBase == 0) {
- const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, i);
+ const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
assert(RC && "Isn't a register operand!");
VRBase = RegInfo.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
// Verify that it is right.
- assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
+ assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
const TargetRegisterClass *RC =
- getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
+ getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
if (VRC != RC) {
MI->addOperand(MachineOperand::CreateReg(VReg, false));
// Verify that it is right.
- assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
+ assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
const TargetRegisterClass *RC =
- getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
+ getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
assert(RegInfo.getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
const TargetRegisterClass *TRC,
unsigned SubIdx) {
// Pick the register class of the subregister
- MRegisterInfo::regclass_iterator I = TRC->subregclasses_begin() + SubIdx-1;
+ TargetRegisterInfo::regclass_iterator I =
+ TRC->subregclasses_begin() + SubIdx-1;
assert(I < TRC->subregclasses_end() &&
"Invalid subregister index for register class");
return *I;
unsigned SubIdx,
MVT::ValueType VT) {
// Pick the register class of the superegister for this type
- for (MRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
+ for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
E = TRC->superregclasses_end(); I != E; ++I)
if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
return *I;
if (Use->getOpcode() == ISD::CopyToReg &&
Use->getOperand(2).Val == Node) {
unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
- if (MRegisterInfo::isVirtualRegister(DestReg)) {
+ if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
VRBase = DestReg;
break;
}
if (Use->getOpcode() == ISD::CopyToReg &&
Use->getOperand(2).Val == Node) {
unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
- if (MRegisterInfo::isVirtualRegister(DestReg)) {
+ if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
VRBase = DestReg;
break;
}
if (InReg != DestReg) {// Coalesced away the copy?
const TargetRegisterClass *TRC = 0;
// Get the target register class
- if (MRegisterInfo::isVirtualRegister(InReg))
+ if (TargetRegisterInfo::isVirtualRegister(InReg))
TRC = RegInfo.getRegClass(InReg);
else
TRC =
- MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(),
+ TRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(),
InReg);
TII->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
}
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#define DEBUG_TYPE "pre-RA-sched"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
void ScheduleDAGRRList::Schedule() {
DOUT << "********** List Scheduling **********\n";
- LiveRegDefs.resize(MRI->getNumRegs(), NULL);
- LiveRegCycles.resize(MRI->getNumRegs(), 0);
+ LiveRegDefs.resize(TRI->getNumRegs(), NULL);
+ LiveRegCycles.resize(TRI->getNumRegs(), 0);
// Build scheduling units.
BuildSchedUnits();
if (RegAdded.insert(Reg))
LRegs.push_back(Reg);
}
- for (const unsigned *Alias = MRI->getAliasSet(Reg);
+ for (const unsigned *Alias = TRI->getAliasSet(Reg);
*Alias; ++Alias)
if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
if (RegAdded.insert(*Alias))
if (RegAdded.insert(*Reg))
LRegs.push_back(*Reg);
}
- for (const unsigned *Alias = MRI->getAliasSet(*Reg);
+ for (const unsigned *Alias = TRI->getAliasSet(*Reg);
*Alias; ++Alias)
if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
if (RegAdded.insert(*Alias))
// Issue expensive cross register class copies.
MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII);
const TargetRegisterClass *RC =
- MRI->getPhysicalRegisterRegClass(VT, Reg);
- const TargetRegisterClass *DestRC = MRI->getCrossCopyRegClass(RC);
+ TRI->getPhysicalRegisterRegClass(VT, Reg);
+ const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
if (!DestRC) {
assert(false && "Don't know how to copy this physical register!");
abort();
std::vector<unsigned> SethiUllmanNumbers;
const TargetInstrInfo *TII;
- const MRegisterInfo *MRI;
+ const TargetRegisterInfo *TRI;
public:
explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii,
- const MRegisterInfo *mri)
- : TII(tii), MRI(mri) {}
+ const TargetRegisterInfo *tri)
+ : TII(tii), TRI(tri) {}
void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap,
std::vector<SUnit> &sunits) {
/// physical register def.
static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU,
const TargetInstrInfo *TII,
- const MRegisterInfo *MRI) {
+ const TargetRegisterInfo *TRI) {
SDNode *N = SuccSU->Node;
unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs();
const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs();
unsigned Reg = ImpDefs[i - NumDefs];
for (;*SUImpDefs; ++SUImpDefs) {
unsigned SUReg = *SUImpDefs;
- if (MRI->regsOverlap(Reg, SUReg))
+ if (TRI->regsOverlap(Reg, SUReg))
return true;
}
}
// Don't constrain nodes with physical register defs if the
// predecessor can clobber them.
if (SuccSU->hasPhysRegDefs) {
- if (canClobberPhysRegDefs(SuccSU, SU, TII, MRI))
+ if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
continue;
}
// Don't constraint extract_subreg / insert_subreg these may be
SelectionDAG *DAG,
MachineBasicBlock *BB) {
const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
- const MRegisterInfo *MRI = DAG->getTarget().getRegisterInfo();
+ const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo();
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true,
- new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII, MRI));
+ new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII, TRI));
}
llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
cerr << LBB->getName() << " ";
cerr << (const void*)BBDN->getBasicBlock() << ">";
} else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
- if (G && R->getReg() && MRegisterInfo::isPhysicalRegister(R->getReg())) {
+ if (G && R->getReg() &&
+ TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
cerr << " " <<G->getTarget().getRegisterInfo()->getName(R->getReg());
} else {
cerr << " #" << R->getReg();
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
/// register class for the register. Otherwise, return null.
static const TargetRegisterClass *
isAllocatableRegister(unsigned Reg, MachineFunction &MF,
- const TargetLowering &TLI, const MRegisterInfo *MRI) {
+ const TargetLowering &TLI,
+ const TargetRegisterInfo *TRI) {
MVT::ValueType FoundVT = MVT::Other;
const TargetRegisterClass *FoundRC = 0;
- for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
- E = MRI->regclass_end(); RCI != E; ++RCI) {
+ for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
+ E = TRI->regclass_end(); RCI != E; ++RCI) {
MVT::ValueType ThisVT = MVT::Other;
const TargetRegisterClass *RC = *RCI;
OpInfo.ConstraintVT);
}
- const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
+ const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
unsigned NumAllocated = 0;
for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
unsigned Reg = RegClassRegs[i];
// Check to see if this register is allocatable (i.e. don't give out the
// stack pointer).
if (RC == 0) {
- RC = isAllocatableRegister(Reg, MF, TLI, MRI);
+ RC = isAllocatableRegister(Reg, MF, TLI, TRI);
if (!RC) { // Couldn't allocate this register.
// Reset NumAllocated to make sure we return consecutive registers.
NumAllocated = 0;
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/GraphWriter.h"
#include "llvm/ADT/StringExtras.h"
//Op += " " + (const void*)BBDN->getBasicBlock();
} else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node)) {
if (G && R->getReg() != 0 &&
- MRegisterInfo::isPhysicalRegister(R->getReg())) {
+ TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
Op = Op + " " + G->getTarget().getRegisterInfo()->getName(R->getReg());
} else {
Op += " #" + utostr(R->getReg());
#include "llvm/Target/TargetSubtarget.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/DerivedTypes.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/ADT/StringExtras.h"
std::string RegName(Constraint.begin()+1, Constraint.end()-1);
// Figure out which register class contains this reg.
- const MRegisterInfo *RI = TM.getRegisterInfo();
- for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
E = RI->regclass_end(); RCI != E; ++RCI) {
const TargetRegisterClass *RC = *RCI;
// If a live interval is a physical register, conservatively check if any
// of its sub-registers is overlapping the live interval of the virtual
// register. If so, do not coalesce.
- if (MRegisterInfo::isPhysicalRegister(IntB.reg) &&
- *mri_->getSubRegisters(IntB.reg)) {
- for (const unsigned* SR = mri_->getSubRegisters(IntB.reg); *SR; ++SR)
+ if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
+ *tri_->getSubRegisters(IntB.reg)) {
+ for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
DOUT << "Interfere with sub-register ";
- DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
+ DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
return false;
}
}
- DOUT << "\nExtending: "; IntB.print(DOUT, mri_);
+ DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
// We are about to delete CopyMI, so need to remove it as the 'instruction
// If the IntB live range is assigned to a physical register, and if that
// physreg has aliases,
- if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
+ if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
// Update the liveintervals of sub-registers.
- for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) {
+ for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) {
LiveInterval &AliasLI = li_->getInterval(*AS);
AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
// Okay, merge "B1" into the same value number as "B0".
if (BValNo != ValLR->valno)
IntB.MergeValueNumberInto(BValNo, ValLR->valno);
- DOUT << " result = "; IntB.print(DOUT, mri_);
+ DOUT << " result = "; IntB.print(DOUT, tri_);
DOUT << "\n";
// If the source instruction was killing the source register before the
return false; // Not coalescable.
}
- bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
- bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
+ bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(repSrcReg);
+ bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(repDstReg);
// If they are both physical registers, we cannot join them.
if (SrcIsPhys && DstIsPhys) {
if (SrcIsPhys)
// r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
// coalesced with AX.
- repSrcReg = mri_->getSubReg(repSrcReg, SubIdx);
+ repSrcReg = tri_->getSubReg(repSrcReg, SubIdx);
else if (DstIsPhys) {
// If this is a extract_subreg where dst is a physical register, e.g.
// cl = EXTRACT_SUBREG reg1024, 1
// then create and update the actual physical register allocated to RHS.
const TargetRegisterClass *RC=mf_->getRegInfo().getRegClass(repSrcReg);
- for (const unsigned *SRs = mri_->getSuperRegisters(repDstReg);
+ for (const unsigned *SRs = tri_->getSuperRegisters(repDstReg);
unsigned SR = *SRs; ++SRs) {
- if (repDstReg == mri_->getSubReg(SR, SubIdx) &&
+ if (repDstReg == tri_->getSubReg(SR, SubIdx) &&
RC->contains(SR)) {
RealDstReg = SR;
break;
if (li_->hasInterval(RealDstReg) &&
RHS.overlaps(li_->getInterval(RealDstReg))) {
DOUT << "Interfere with register ";
- DEBUG(li_->getInterval(RealDstReg).print(DOUT, mri_));
+ DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_));
return false; // Not coalescable
}
- for (const unsigned* SR = mri_->getSubRegisters(RealDstReg); *SR; ++SR)
+ for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
DOUT << "Interfere with sub-register ";
- DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
+ DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
return false; // Not coalescable
}
} else {
assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg &&
"Register mapping is horribly broken!");
- DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
- DOUT << " and "; DstInt.print(DOUT, mri_);
+ DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
+ DOUT << " and "; DstInt.print(DOUT, tri_);
DOUT << ": ";
// Check if it is necessary to propagate "isDead" property before intervals
if (isDead) {
// Result of the copy is dead. Propagate this property.
if (SrcStart == 0) {
- assert(MRegisterInfo::isPhysicalRegister(repSrcReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(repSrcReg) &&
"Live-in must be a physical register!");
// Live-in to the function but dead. Remove it from entry live-in set.
// JoinIntervals may end up swapping the two intervals.
std::swap(repSrcReg, repDstReg);
std::swap(ResSrcInt, ResDstInt);
}
- assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(repSrcReg) &&
"LiveInterval::join didn't work right!");
// If we're about to merge live ranges into a physical register live range,
// we have to update any aliased register's live ranges to indicate that they
// have clobbered values for this range.
- if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
+ if (TargetRegisterInfo::isPhysicalRegister(repDstReg)) {
// Unset unnecessary kills.
if (!ResDstInt->containsOneValue()) {
for (LiveInterval::Ranges::const_iterator I = ResSrcInt->begin(),
}
// Update the liveintervals of sub-registers.
- for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS)
+ for (const unsigned *AS = tri_->getSubRegisters(repDstReg); *AS; ++AS)
li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
li_->getVNInfoAllocator());
} else {
}
// Remember these liveintervals have been joined.
- JoinedLIs.set(repSrcReg - MRegisterInfo::FirstVirtualRegister);
- if (MRegisterInfo::isVirtualRegister(repDstReg))
- JoinedLIs.set(repDstReg - MRegisterInfo::FirstVirtualRegister);
+ JoinedLIs.set(repSrcReg - TargetRegisterInfo::FirstVirtualRegister);
+ if (TargetRegisterInfo::isVirtualRegister(repDstReg))
+ JoinedLIs.set(repDstReg - TargetRegisterInfo::FirstVirtualRegister);
if (isExtSubReg && !SrcIsPhys && !DstIsPhys) {
if (!Swapped) {
}
}
- DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, mri_);
+ DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
DOUT << "\n";
// repSrcReg is guarateed to be the register whose live interval that is
// If a live interval is a physical register, conservatively check if any
// of its sub-registers is overlapping the live interval of the virtual
// register. If so, do not coalesce.
- if (MRegisterInfo::isPhysicalRegister(LHS.reg) &&
- *mri_->getSubRegisters(LHS.reg)) {
- for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR)
+ if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
+ *tri_->getSubRegisters(LHS.reg)) {
+ for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
DOUT << "Interfere with sub-register ";
- DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
+ DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
return false;
}
- } else if (MRegisterInfo::isPhysicalRegister(RHS.reg) &&
- *mri_->getSubRegisters(RHS.reg)) {
- for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR)
+ } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
+ *tri_->getSubRegisters(RHS.reg)) {
+ for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
DOUT << "Interfere with sub-register ";
- DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
+ DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
return false;
}
}
// If RHS is not defined as a copy from the LHS, we can use simpler and
// faster checks to see if the live ranges are coalescable. This joiner
// can't swap the LHS/RHS intervals though.
- if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
+ if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
return SimpleJoin(LHS, RHS);
} else {
RHSValNoInfo = RHSValNoInfo0;
// If we get here, we know that we can coalesce the live ranges. Ask the
// intervals to coalesce themselves now.
if ((RHS.ranges.size() > LHS.ranges.size() &&
- MRegisterInfo::isVirtualRegister(LHS.reg)) ||
- MRegisterInfo::isPhysicalRegister(RHS.reg)) {
+ TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
+ TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
Swapped = true;
} else {
return false;
else if (left.isBackEdge == right.isBackEdge) {
// Join virtuals to physical registers first.
- bool LDstIsPhys = MRegisterInfo::isPhysicalRegister(left.DstReg);
- bool LSrcIsPhys = MRegisterInfo::isPhysicalRegister(left.SrcReg);
+ bool LDstIsPhys = TargetRegisterInfo::isPhysicalRegister(left.DstReg);
+ bool LSrcIsPhys = TargetRegisterInfo::isPhysicalRegister(left.SrcReg);
bool LIsPhys = LDstIsPhys || LSrcIsPhys;
- bool RDstIsPhys = MRegisterInfo::isPhysicalRegister(right.DstReg);
- bool RSrcIsPhys = MRegisterInfo::isPhysicalRegister(right.SrcReg);
+ bool RDstIsPhys = TargetRegisterInfo::isPhysicalRegister(right.DstReg);
+ bool RSrcIsPhys = TargetRegisterInfo::isPhysicalRegister(right.SrcReg);
bool RIsPhys = RDstIsPhys || RSrcIsPhys;
if (LIsPhys && !RIsPhys)
return false;
unsigned repSrcReg = rep(SrcReg);
unsigned repDstReg = rep(DstReg);
- bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
- bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
+ bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(repSrcReg);
+ bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(repDstReg);
if (NewHeuristic) {
JoinQueue->push(CopyRec(Inst, SrcReg, DstReg, LoopDepth,
isBackEdgeCopy(Inst, DstReg)));
// unnecessary kills.
int RegNum = JoinedLIs.find_first();
while (RegNum != -1) {
- unsigned Reg = RegNum + MRegisterInfo::FirstVirtualRegister;
+ unsigned Reg = RegNum + TargetRegisterInfo::FirstVirtualRegister;
unsigned repReg = rep(Reg);
LiveInterval &LI = li_->getInterval(repReg);
LiveVariables::VarInfo& svi = lv_->getVarInfo(Reg);
unsigned RegB) const {
// Get the register classes for the first reg.
- if (MRegisterInfo::isPhysicalRegister(RegA)) {
- assert(MRegisterInfo::isVirtualRegister(RegB) &&
+ if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
+ assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
"Shouldn't consider two physregs!");
return !mf_->getRegInfo().getRegClass(RegB)->contains(RegA);
}
// Compare against the regclass for the second reg.
const TargetRegisterClass *RegClass = mf_->getRegInfo().getRegClass(RegA);
- if (MRegisterInfo::isVirtualRegister(RegB))
+ if (TargetRegisterInfo::isVirtualRegister(RegB))
return RegClass != mf_->getRegInfo().getRegClass(RegB);
else
return !RegClass->contains(RegB);
for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isUse() && MO.getReg() &&
- mri_->regsOverlap(rep(MO.getReg()), Reg)) {
+ tri_->regsOverlap(rep(MO.getReg()), Reg)) {
MOU = &MO;
return MI;
}
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDef() &&
- mri_->regsOverlap(rep(MO.getReg()), Reg))
+ tri_->regsOverlap(rep(MO.getReg()), Reg))
return &MO;
}
return NULL;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isKill() && MO.getReg() &&
- mri_->regsOverlap(rep(MO.getReg()), Reg))
+ tri_->regsOverlap(rep(MO.getReg()), Reg))
MO.setIsKill(false);
}
}
for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isKill() && MO.getReg() &&
- mri_->regsOverlap(rep(MO.getReg()), Reg)) {
+ tri_->regsOverlap(rep(MO.getReg()), Reg)) {
MO.setIsKill(false);
}
}
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDef() &&
- mri_->regsOverlap(rep(MO.getReg()), Reg))
+ tri_->regsOverlap(rep(MO.getReg()), Reg))
return true;
}
return false;
}
void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
- if (MRegisterInfo::isPhysicalRegister(reg))
- cerr << mri_->getName(reg);
+ if (TargetRegisterInfo::isPhysicalRegister(reg))
+ cerr << tri_->getName(reg);
else
cerr << "%reg" << reg;
}
bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
mf_ = &fn;
tm_ = &fn.getTarget();
- mri_ = tm_->getRegisterInfo();
+ tri_ = tm_->getRegisterInfo();
tii_ = tm_->getInstrInfo();
li_ = &getAnalysis<LiveIntervals>();
lv_ = &getAnalysis<LiveVariables>();
<< "********** Function: "
<< ((Value*)mf_->getFunction())->getName() << '\n';
- allocatableRegs_ = mri_->getAllocatableSet(fn);
- for (MRegisterInfo::regclass_iterator I = mri_->regclass_begin(),
- E = mri_->regclass_end(); I != E; ++I)
+ allocatableRegs_ = tri_->getAllocatableSet(fn);
+ for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
+ E = tri_->regclass_end(); I != E; ++I)
allocatableRCRegs_.insert(std::make_pair(*I,
- mri_->getAllocatableSet(fn, *I)));
+ tri_->getAllocatableSet(fn, *I)));
MachineRegisterInfo &RegInfo = mf_->getRegInfo();
r2rMap_.grow(RegInfo.getLastVirtReg());
joinIntervals();
DOUT << "********** INTERVALS POST JOINING **********\n";
for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
- I->second.print(DOUT, mri_);
+ I->second.print(DOUT, tri_);
DOUT << "\n";
}
for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
const MachineOperand &mop = mii->getOperand(i);
if (mop.isRegister() && mop.getReg() &&
- MRegisterInfo::isVirtualRegister(mop.getReg())) {
+ TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
// replace register with representative register
unsigned OrigReg = mop.getReg();
unsigned reg = rep(OrigReg);
unsigned SubIdx = RegSubIdxMap[OrigReg];
- if (SubIdx && MRegisterInfo::isPhysicalRegister(reg))
- mii->getOperand(i).setReg(mri_->getSubReg(reg, SubIdx));
+ if (SubIdx && TargetRegisterInfo::isPhysicalRegister(reg))
+ mii->getOperand(i).setReg(tri_->getSubReg(reg, SubIdx));
else {
mii->getOperand(i).setReg(reg);
mii->getOperand(i).setSubReg(SubIdx);
for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
LiveInterval &LI = I->second;
- if (MRegisterInfo::isVirtualRegister(LI.reg)) {
+ if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
// If the live interval length is essentially zero, i.e. in every live
// range the use follows def immediately, it doesn't make sense to spill
// it and hope it will be easier to allocate for this li.
namespace llvm {
class SimpleRegisterCoalescing;
class LiveVariables;
- class MRegisterInfo;
+ class TargetRegisterInfo;
class TargetInstrInfo;
class VirtRegMap;
class MachineLoopInfo;
public RegisterCoalescer {
MachineFunction* mf_;
const TargetMachine* tm_;
- const MRegisterInfo* mri_;
+ const TargetRegisterInfo* tri_;
const TargetInstrInfo* tii_;
LiveIntervals *li_;
LiveVariables *lv_;
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
unsigned regA = mi->getOperand(ti).getReg();
unsigned regB = mi->getOperand(si).getReg();
- assert(MRegisterInfo::isVirtualRegister(regA) &&
- MRegisterInfo::isVirtualRegister(regB) &&
+ assert(TargetRegisterInfo::isVirtualRegister(regA) &&
+ TargetRegisterInfo::isVirtualRegister(regB) &&
"cannot update physical register live information");
#ifndef NDEBUG
}
int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
"attempt to assign stack slot to already spilled register");
const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg);
}
void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
"attempt to assign stack slot to already spilled register");
assert((frameIndex >= 0 ||
}
int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
"attempt to assign re-mat id to already spilled register");
Virt2ReMatIdMap[virtReg] = ReMatId;
}
void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
"attempt to assign re-mat id to already spilled register");
Virt2ReMatIdMap[virtReg] = id;
}
void VirtRegMap::print(std::ostream &OS) const {
- const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
+ const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo();
OS << "********** REGISTER MAP **********\n";
- for (unsigned i = MRegisterInfo::FirstVirtualRegister,
+ for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
- OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
+ OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) << "]\n";
}
- for (unsigned i = MRegisterInfo::FirstVirtualRegister,
+ for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i)
if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (MO.isRegister() && MO.getReg())
- if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned VirtReg = MO.getReg();
unsigned PhysReg = VRM.getPhys(VirtReg);
if (!VRM.isAssignedReg(VirtReg)) {
/// register pressure in other blocks).
class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
MachineRegisterInfo *RegInfo;
- const MRegisterInfo *MRI;
+ const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
public:
bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
RegInfo = &MF.getRegInfo();
- MRI = MF.getTarget().getRegisterInfo();
+ TRI = MF.getTarget().getRegisterInfo();
TII = MF.getTarget().getInstrInfo();
DOUT << "\n**** Local spiller rewriting function '"
<< MF.getFunction()->getName() << "':\n";
/// this bit and addAvailable sets it if.
namespace {
class VISIBILITY_HIDDEN AvailableSpills {
- const MRegisterInfo *MRI;
+ const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
// SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
void ClobberPhysRegOnly(unsigned PhysReg);
public:
- AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
- : MRI(mri), TII(tii) {
+ AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii)
+ : TRI(tri), TII(tii) {
}
- const MRegisterInfo *getRegInfo() const { return MRI; }
+ const TargetRegisterInfo *getRegInfo() const { return TRI; }
/// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
/// available in a physical register, return that PhysReg, otherwise
DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
else
DOUT << "Remembering SS#" << SlotOrReMat;
- DOUT << " in physreg " << MRI->getName(Reg) << "\n";
+ DOUT << " in physreg " << TRI->getName(Reg) << "\n";
}
/// canClobberPhysReg - Return true if the spiller is allowed to change the
assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
"Bidirectional map mismatch!");
SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
- DOUT << "PhysReg " << MRI->getName(PhysReg)
+ DOUT << "PhysReg " << TRI->getName(PhysReg)
<< " copied, it is available for use but can no longer be modified\n";
}
}
/// stackslot register and its aliases. The register and its aliases may
/// still available but is no longer allowed to be modifed.
void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
- for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
+ for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
disallowClobberPhysRegOnly(*AS);
disallowClobberPhysRegOnly(PhysReg);
}
assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
"Bidirectional map mismatch!");
SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
- DOUT << "PhysReg " << MRI->getName(PhysReg)
+ DOUT << "PhysReg " << TRI->getName(PhysReg)
<< " clobbered, invalidating ";
if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
/// value. We use this to invalidate any info about stuff we thing lives in
/// it and any of its aliases.
void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
- for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
+ for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
ClobberPhysRegOnly(*AS);
ClobberPhysRegOnly(PhysReg);
}
std::vector<ReusedOp> Reuses;
BitVector PhysRegsClobbered;
public:
- ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
- PhysRegsClobbered.resize(mri->getNumRegs());
+ ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) {
+ PhysRegsClobbered.resize(tri->getNumRegs());
}
bool hasReuses() const {
// value aliases the new register. If so, codegen the previous reload
// and use this one.
unsigned PRRU = Op.PhysRegReused;
- const MRegisterInfo *MRI = Spills.getRegInfo();
- if (MRI->areAliases(PRRU, PhysReg)) {
+ const TargetRegisterInfo *TRI = Spills.getRegInfo();
+ if (TRI->areAliases(PRRU, PhysReg)) {
// Okay, we found out that an alias of a reused register
// was used. This isn't good because it means we have
// to undo a previous reuse.
Rejected, RegKills, KillOps, VRM);
if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
- MRI->reMaterialize(*MBB, MI, NewPhysReg,
+ TRI->reMaterialize(*MBB, MI, NewPhysReg,
VRM.getReMaterializedMI(NewOp.VirtReg));
++NumReMats;
} else {
if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse())
continue;
unsigned VirtReg = MO.getReg();
- if (MRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
+ if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
continue;
if (VRM.isAssignedReg(VirtReg)) {
unsigned PhysReg = VRM.getPhys(VirtReg);
- if (PhysReg && MRI->regsOverlap(PhysReg, UnfoldPR))
+ if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR))
return false;
} else if (VRM.isReMaterialized(VirtReg))
continue;
int SS = VRM.getStackSlot(VirtReg);
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
if (PhysReg) {
- if (MRI->regsOverlap(PhysReg, UnfoldPR))
+ if (TRI->regsOverlap(PhysReg, UnfoldPR))
return false;
continue;
}
PhysReg = VRM.getPhys(VirtReg);
- if (!MRI->regsOverlap(PhysReg, UnfoldPR))
+ if (!TRI->regsOverlap(PhysReg, UnfoldPR))
continue;
// Ok, we'll need to reload the value into a register which makes
/// findSuperReg - Find the SubReg's super-register of given register class
/// where its SubIdx sub-register is SubReg.
static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
- unsigned SubIdx, const MRegisterInfo *MRI) {
+ unsigned SubIdx, const TargetRegisterInfo *TRI) {
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
I != E; ++I) {
unsigned Reg = *I;
- if (MRI->getSubReg(Reg, SubIdx) == SubReg)
+ if (TRI->getSubReg(Reg, SubIdx) == SubReg)
return Reg;
}
return 0;
// Spills - Keep track of which spilled values are available in physregs so
// that we can choose to reuse the physregs instead of emitting reloads.
- AvailableSpills Spills(MRI, TII);
+ AvailableSpills Spills(TRI, TII);
// MaybeDeadStores - When we need to write a value back into a stack slot,
// keep track of the inserted store. If the stack slot value is never read
SmallSet<MachineInstr*, 4> ReMatDefs;
// Keep track of kill information.
- BitVector RegKills(MRI->getNumRegs());
+ BitVector RegKills(TRI->getNumRegs());
std::vector<MachineOperand*> KillOps;
- KillOps.resize(MRI->getNumRegs(), NULL);
+ KillOps.resize(TRI->getNumRegs(), NULL);
for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
MII != E; ) {
unsigned Phys = VRM.getPhys(VirtReg);
RegInfo->setPhysRegUsed(Phys);
if (VRM.isReMaterialized(VirtReg)) {
- MRI->reMaterialize(MBB, &MI, Phys,
+ TRI->reMaterialize(MBB, &MI, Phys,
VRM.getReMaterializedMI(VirtReg));
++NumReMats;
} else {
/// ReusedOperands - Keep track of operand reuse in case we need to undo
/// reuse.
- ReuseInfo ReusedOperands(MI, MRI);
+ ReuseInfo ReusedOperands(MI, TRI);
// Process all of the spilled uses and all non spilled reg references.
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
continue; // Ignore non-register operands.
unsigned VirtReg = MO.getReg();
- if (MRegisterInfo::isPhysicalRegister(VirtReg)) {
+ if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
// Ignore physregs for spilling, but remember that it is used by this
// function.
RegInfo->setPhysRegUsed(VirtReg);
continue;
}
- assert(MRegisterInfo::isVirtualRegister(VirtReg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
"Not a virtual or a physical register?");
unsigned SubIdx = MO.getSubReg();
RegInfo->setPhysRegUsed(Phys);
if (MO.isDef())
ReusedOperands.markClobbered(Phys);
- unsigned RReg = SubIdx ? MRI->getSubReg(Phys, SubIdx) : Phys;
+ unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
MI.getOperand(i).setReg(RReg);
continue;
}
else
DOUT << "Reusing SS#" << ReuseSlot;
DOUT << " from physreg "
- << MRI->getName(PhysReg) << " for vreg"
+ << TRI->getName(PhysReg) << " for vreg"
<< VirtReg <<" instead of reloading into physreg "
- << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
- unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
+ << TRI->getName(VRM.getPhys(VirtReg)) << "\n";
+ unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
MI.getOperand(i).setReg(RReg);
// The only technical detail we have is that we don't know that
DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
else
DOUT << "Reusing SS#" << ReuseSlot;
- DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
+ DOUT << " from physreg " << TRI->getName(PhysReg) << " for vreg"
<< VirtReg
<< " instead of reloading into same physreg.\n";
- unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
+ unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
MI.getOperand(i).setReg(RReg);
ReusedOperands.markClobbered(RReg);
++NumReused;
Spills.addAvailable(ReuseSlot, &MI, DesignatedReg);
unsigned RReg =
- SubIdx ? MRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
+ SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
MI.getOperand(i).setReg(RReg);
DOUT << '\t' << *prior(MII);
++NumReused;
RegInfo->setPhysRegUsed(PhysReg);
ReusedOperands.markClobbered(PhysReg);
if (DoReMat) {
- MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
+ TRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
++NumReMats;
} else {
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
// unless it's a two-address operand.
if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
MI.getOperand(i).setIsKill();
- unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
+ unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
MI.getOperand(i).setReg(RReg);
UpdateKills(*prior(MII), RegKills, KillOps);
DOUT << '\t' << *prior(MII);
int StackSlot;
if (!(MR & VirtRegMap::isRef)) {
if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
- assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
"Src hasn't been allocated yet?");
// Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
// this as a potentially dead store in case there is a subsequent
continue;
unsigned VirtReg = MO.getReg();
- if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
+ if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) {
// Check to see if this is a noop copy. If so, eliminate the
// instruction before considering the dest reg to be changed.
unsigned Src, Dst;
if (TiedOp != -1) {
PhysReg = MI.getOperand(TiedOp).getReg();
if (SubIdx) {
- unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, MRI);
- assert(SuperReg && MRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
+ unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI);
+ assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
"Can't find corresponding super-register!");
PhysReg = SuperReg;
}
}
RegInfo->setPhysRegUsed(PhysReg);
- unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
+ unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
ReusedOperands.markClobbered(RReg);
MI.getOperand(i).setReg(RReg);
#ifndef LLVM_CODEGEN_VIRTREGMAP_H
#define LLVM_CODEGEN_VIRTREGMAP_H
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/Support/Streams.h"
/// @brief returns the physical register mapped to the specified
/// virtual register
unsigned getPhys(unsigned virtReg) const {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
return Virt2PhysMap[virtReg];
}
/// @brief creates a mapping for the specified virtual register to
/// the specified physical register
void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
- assert(MRegisterInfo::isVirtualRegister(virtReg) &&
- MRegisterInfo::isPhysicalRegister(physReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
+ TargetRegisterInfo::isPhysicalRegister(physReg));
assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
"attempt to assign physical register to already mapped "
"virtual register");
/// @brief clears the specified virtual register's, physical
/// register mapping
void clearVirt(unsigned virtReg) {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
assert(Virt2PhysMap[virtReg] != NO_PHYS_REG &&
"attempt to clear a not assigned virtual register");
Virt2PhysMap[virtReg] = NO_PHYS_REG;
/// @brief returns the stack slot mapped to the specified virtual
/// register
int getStackSlot(unsigned virtReg) const {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
return Virt2StackSlotMap[virtReg];
}
/// @brief returns the rematerialization id mapped to the specified virtual
/// register
int getReMatId(unsigned virtReg) const {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
return Virt2ReMatIdMap[virtReg];
}
const MachineOperand &MO = MI->getOperand(opNum);
switch (MO.getType()) {
case MachineOperand::MO_Register:
- if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
+ if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
else
assert(0 && "not implemented");
const MachineOperand &MO2 = MI->getOperand(Op+1);
const MachineOperand &MO3 = MI->getOperand(Op+2);
- assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
+ assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
O << TM.getRegisterInfo()->get(MO1.getReg()).Name;
// Print the shift opc.
<< " ";
if (MO2.getReg()) {
- assert(MRegisterInfo::isPhysicalRegister(MO2.getReg()));
+ assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
O << TM.getRegisterInfo()->get(MO2.getReg()).Name;
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
} else {
const MachineOperand &MO2 = MI->getOperand(Op+1);
const MachineOperand &MO3 = MI->getOperand(Op+2);
- assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
+ assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
if (MO2.getReg()) {
return;
}
- assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
+ assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
if (Modifier && strcmp(Modifier, "submode") == 0) {
ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
}
const MachineOperand &MO1 = MI->getOperand(Op);
- assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
+ assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).Name << "]";
}
intptr_t rv = 0;
const MachineOperand &MO = MI.getOperand(OpIndex);
if (MO.isRegister()) {
- assert(MRegisterInfo::isPhysicalRegister(MO.getReg()));
+ assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
} else if (MO.isImmediate()) {
rv = MO.getImm();
if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx)
if(IsShiftByRegister) {
// set the value of bit[11:8] (register Rs).
- assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
+ assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg());
assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
Value |= op << ARMII::RegRsShift;
// set bit I(25), because this is not in immediate enconding.
Value |= 1 << ARMII::I_BitShift;
- assert(MRegisterInfo::isPhysicalRegister(MO2.getReg()));
+ assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
// set bit[3:0] to the corresponding Rm register
Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
for (unsigned i = OpIndex + 4, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MOR = MI.getOperand(i);
unsigned RegNumber = ARMRegisterInfo::getRegisterNumbering(MOR.getReg());
- assert(MRegisterInfo::isPhysicalRegister(MOR.getReg()) && RegNumber < 16);
+ assert(TargetRegisterInfo::isPhysicalRegister(MOR.getReg()) &&
+ RegNumber < 16);
Value |= 0x1 << RegNumber;
}
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.getReg() &&
- MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
if (MO.isDef()) {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+ virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Support/Compiler.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
ARMLoadStoreOpt() : MachineFunctionPass((intptr_t)&ID) {}
const TargetInstrInfo *TII;
- const MRegisterInfo *MRI;
+ const TargetRegisterInfo *TRI;
ARMFunctionInfo *AFI;
RegScavenger *RS;
const TargetMachine &TM = Fn.getTarget();
AFI = Fn.getInfo<ARMFunctionInfo>();
TII = TM.getInstrInfo();
- MRI = TM.getRegisterInfo();
+ TRI = TM.getRegisterInfo();
RS = new RegScavenger();
bool Modified = false;
#include "ARMSubtarget.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/BitVector.h"
//
//===----------------------------------------------------------------------===//
//
-// This file contains the ARM implementation of the MRegisterInfo class.
+// This file contains the ARM implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
//
-// This file contains the ARM implementation of the MRegisterInfo class.
+// This file contains the ARM implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef ARMREGISTERINFO_H
#define ARMREGISTERINFO_H
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "ARMGenRegisterInfo.h.inc"
namespace llvm {
GPRClass::iterator
GPRClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo *RI = TM.getRegisterInfo();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
GPRClass::iterator I;
if (Subtarget.isThumb())
virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual TargetJITInfo *getJITInfo() { return &JITInfo; }
- virtual const MRegisterInfo *getRegisterInfo() const {
+ virtual const TargetRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
virtual const TargetData *getTargetData() const { return &DataLayout; }
{
const MachineOperand &MO = MI->getOperand(opNum);
if (MO.getType() == MachineOperand::MO_Register) {
- assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
+ assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ "Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
O << MO.getImm();
void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
- const MRegisterInfo &RI = *TM.getRegisterInfo();
+ const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register:
VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
std::vector<SDOperand> LS;
for (int i = 0; i < 6; ++i) {
- if (MRegisterInfo::isPhysicalRegister(args_int[i]))
+ if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
- if (MRegisterInfo::isPhysicalRegister(args_float[i]))
+ if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+ virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
//
//===----------------------------------------------------------------------===//
//
-// This file contains the Alpha implementation of the MRegisterInfo class.
+// This file contains the Alpha implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
//
-// This file contains the Alpha implementation of the MRegisterInfo class.
+// This file contains the Alpha implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef ALPHAREGISTERINFO_H
#define ALPHAREGISTERINFO_H
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "AlphaGenRegisterInfo.h.inc"
namespace llvm {
virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; }
- virtual const MRegisterInfo *getRegisterInfo() const {
+ virtual const TargetRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
virtual TargetLowering* getTargetLowering() const {
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Target/TargetAsmInfo.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/Statistic.h"
///
void printRegister(const MachineOperand &MO, bool R0AsZero) {
unsigned RegNo = MO.getReg();
- assert(MRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??");
+ assert(TargetRegisterInfo::isPhysicalRegister(RegNo) &&
+ "Not physreg??");
O << TM.getRegisterInfo()->get(RegNo).Name;
}
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.isRegister()) {
- assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
+ assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
O << MO.getImm();
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+ virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
//
//===----------------------------------------------------------------------===//
//
-// This file contains the Cell implementation of the MRegisterInfo class.
+// This file contains the Cell implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
//
-// This file contains the Cell SPU implementation of the MRegisterInfo class.
+// This file contains the Cell SPU implementation of the TargetRegisterInfo
+// class.
//
//===----------------------------------------------------------------------===//
return const_cast<SPUTargetLowering*>(&TLInfo);
}
- virtual const MRegisterInfo *getRegisterInfo() const {
+ virtual const TargetRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
void printOperand(const MachineInstr *MI, unsigned OpNo){
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.getType() == MachineOperand::MO_Register) {
- assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
+ assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ "Not physref??");
//XXX Bug Workaround: See note in Printer::doInitialization about %.
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else {
void IA64AsmPrinter::printOp(const MachineOperand &MO,
bool isBRCALLinsn /* = false */) {
- const MRegisterInfo &RI = *TM.getRegisterInfo();
+ const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register:
O << RI.get(MO.getReg()).Name;
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+ virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
//
// Return true if the instruction is a register to register move and
//
//===----------------------------------------------------------------------===//
//
-// This file contains the IA64 implementation of the MRegisterInfo class. This
-// file is responsible for the frame pointer elimination optimization on IA64.
+// This file contains the IA64 implementation of the TargetRegisterInfo class.
+// This file is responsible for the frame pointer elimination optimization
+// on IA64.
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
//
-// This file contains the IA64 implementation of the MRegisterInfo class.
+// This file contains the IA64 implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef IA64REGISTERINFO_H
#define IA64REGISTERINFO_H
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "IA64GenRegisterInfo.h.inc"
namespace llvm { class llvm::Type; }
virtual IA64TargetLowering *getTargetLowering() const {
return const_cast<IA64TargetLowering*>(&TLInfo);
}
- virtual const MRegisterInfo *getRegisterInfo() const {
+ virtual const TargetRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
virtual const TargetData *getTargetData() const { return &DataLayout; }
+++ /dev/null
-//===- MRegisterInfo.cpp - Target Register Information Implementation -----===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the MRegisterInfo interface.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MRegisterInfo.h"
-#include "llvm/Target/TargetFrameInfo.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/ADT/BitVector.h"
-
-using namespace llvm;
-
-MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
- regclass_iterator RCB, regclass_iterator RCE,
- int CFSO, int CFDO)
- : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
- assert(NumRegs < FirstVirtualRegister &&
- "Target has too many physical registers!");
-
- CallFrameSetupOpcode = CFSO;
- CallFrameDestroyOpcode = CFDO;
-}
-
-MRegisterInfo::~MRegisterInfo() {}
-
-/// getPhysicalRegisterRegClass - Returns the Register Class of a physical
-/// register.
-const TargetRegisterClass *
-MRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT,
- unsigned reg) const {
- assert(isPhysicalRegister(reg) && "reg must be a physical register");
- // Pick the register class of the right type that contains this physreg.
- for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I)
- if ((*I)->hasType(VT) && (*I)->contains(reg))
- return *I;
- assert(false && "Couldn't find the register class");
- return 0;
-}
-
-
-/// getAllocatableSetForRC - Toggle the bits that represent allocatable
-/// registers for the specific register class.
-static void getAllocatableSetForRC(MachineFunction &MF,
- const TargetRegisterClass *RC, BitVector &R){
- for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
- E = RC->allocation_order_end(MF); I != E; ++I)
- R.set(*I);
-}
-
-BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF,
- const TargetRegisterClass *RC) const {
- BitVector Allocatable(NumRegs);
- if (RC) {
- getAllocatableSetForRC(MF, RC, Allocatable);
- return Allocatable;
- }
-
- for (MRegisterInfo::regclass_iterator I = regclass_begin(),
- E = regclass_end(); I != E; ++I)
- getAllocatableSetForRC(MF, *I, Allocatable);
- return Allocatable;
-}
-
-/// getFrameIndexOffset - Returns the displacement from the frame register to
-/// the stack frame of the specified index. This is the default implementation
-/// which is likely incorrect for the target.
-int MRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
- const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
- MachineFrameInfo *MFI = MF.getFrameInfo();
- return MFI->getObjectOffset(FI) + MFI->getStackSize() -
- TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
-}
-
-/// getInitialFrameState - Returns a list of machine moves that are assumed
-/// on entry to a function.
-void
-MRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
- // Default is to do nothing.
-}
-
void MipsAsmPrinter::
emitFrameDirective(MachineFunction &MF)
{
- const MRegisterInfo &RI = *TM.getRegisterInfo();
+ const TargetRegisterInfo &RI = *TM.getRegisterInfo();
unsigned stackReg = RI.getFrameRegister(MF);
unsigned returnReg = RI.getRARegister();
unsigned int MipsAsmPrinter::
getSavedRegsBitmask(bool isFloat, MachineFunction &MF)
{
- const MRegisterInfo &RI = *TM.getRegisterInfo();
+ const TargetRegisterInfo &RI = *TM.getRegisterInfo();
// Float Point Registers, TODO
if (isFloat)
printOperand(const MachineInstr *MI, int opNum)
{
const MachineOperand &MO = MI->getOperand(opNum);
- const MRegisterInfo &RI = *TM.getRegisterInfo();
+ const TargetRegisterInfo &RI = *TM.getRegisterInfo();
bool closeP = false;
bool isPIC = (TM.getRelocationModel() == Reloc::PIC_);
bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
switch (MO.getType())
{
case MachineOperand::MO_Register:
- if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
+ if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
O << "$" << LowercaseString (RI.get(MO.getReg()).Name);
else
O << "$" << MO.getReg();
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+ virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
//
//===----------------------------------------------------------------------===//
//
-// This file contains the MIPS implementation of the MRegisterInfo class.
+// This file contains the MIPS implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
//
-// This file contains the Mips implementation of the MRegisterInfo class.
+// This file contains the Mips implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef MIPSREGISTERINFO_H
#define MIPSREGISTERINFO_H
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "MipsGenRegisterInfo.h.inc"
namespace llvm {
virtual const TargetData *getTargetData() const
{ return &DataLayout;}
- virtual const MRegisterInfo *getRegisterInfo() const {
+ virtual const TargetRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Target/TargetAsmInfo.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/Statistic.h"
///
void printRegister(const MachineOperand &MO, bool R0AsZero) {
unsigned RegNo = MO.getReg();
- assert(MRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??");
+ assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??");
// If we should use 0 for R0.
if (R0AsZero && RegNo == PPC::R0) {
// by the scheduler. Detect them now.
MachineFunction &Fn = MachineFunction::get(&F);
bool HasVectorVReg = false;
- for (unsigned i = MRegisterInfo::FirstVirtualRegister,
+ for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
e = RegInfo->getLastVirtReg()+1; i != e; ++i)
if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
HasVectorVReg = true;
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+ virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
//
//===----------------------------------------------------------------------===//
//
-// This file contains the PowerPC implementation of the MRegisterInfo class.
+// This file contains the PowerPC implementation of the TargetRegisterInfo
+// class.
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
//
-// This file contains the PowerPC implementation of the MRegisterInfo class.
+// This file contains the PowerPC implementation of the TargetRegisterInfo
+// class.
//
//===----------------------------------------------------------------------===//
virtual PPCTargetLowering *getTargetLowering() const {
return const_cast<PPCTargetLowering*>(&TLInfo);
}
- virtual const MRegisterInfo *getRegisterInfo() const {
+ virtual const TargetRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
const MachineOperand &MO = MI->getOperand (opNum);
- const MRegisterInfo &RI = *TM.getRegisterInfo();
+ const TargetRegisterInfo &RI = *TM.getRegisterInfo();
bool CloseParen = false;
if (MI->getOpcode() == SP::SETHIi && !MO.isRegister() && !MO.isImmediate()) {
O << "%hi(";
}
switch (MO.getType()) {
case MachineOperand::MO_Register:
- if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
+ if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
else
O << "%reg" << MO.getReg();
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+ virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
//
//===----------------------------------------------------------------------===//
//
-// This file contains the SPARC implementation of the MRegisterInfo class.
+// This file contains the SPARC implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
//
-// This file contains the Sparc implementation of the MRegisterInfo class.
+// This file contains the Sparc implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef SPARCREGISTERINFO_H
#define SPARCREGISTERINFO_H
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "SparcGenRegisterInfo.h.inc"
namespace llvm {
virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; }
- virtual const MRegisterInfo *getRegisterInfo() const {
+ virtual const TargetRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
virtual const TargetData *getTargetData() const { return &DataLayout; }
--- /dev/null
+//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the TargetRegisterInfo interface.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/ADT/BitVector.h"
+
+using namespace llvm;
+
+TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
+ regclass_iterator RCB, regclass_iterator RCE,
+ int CFSO, int CFDO)
+ : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
+ assert(NumRegs < FirstVirtualRegister &&
+ "Target has too many physical registers!");
+
+ CallFrameSetupOpcode = CFSO;
+ CallFrameDestroyOpcode = CFDO;
+}
+
+TargetRegisterInfo::~TargetRegisterInfo() {}
+
+/// getPhysicalRegisterRegClass - Returns the Register Class of a physical
+/// register.
+const TargetRegisterClass *
+TargetRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT,
+ unsigned reg) const {
+ assert(isPhysicalRegister(reg) && "reg must be a physical register");
+ // Pick the register class of the right type that contains this physreg.
+ for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I)
+ if ((*I)->hasType(VT) && (*I)->contains(reg))
+ return *I;
+ assert(false && "Couldn't find the register class");
+ return 0;
+}
+
+
+/// getAllocatableSetForRC - Toggle the bits that represent allocatable
+/// registers for the specific register class.
+static void getAllocatableSetForRC(MachineFunction &MF,
+ const TargetRegisterClass *RC, BitVector &R){
+ for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
+ E = RC->allocation_order_end(MF); I != E; ++I)
+ R.set(*I);
+}
+
+BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF,
+ const TargetRegisterClass *RC) const {
+ BitVector Allocatable(NumRegs);
+ if (RC) {
+ getAllocatableSetForRC(MF, RC, Allocatable);
+ return Allocatable;
+ }
+
+ for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
+ E = regclass_end(); I != E; ++I)
+ getAllocatableSetForRC(MF, *I, Allocatable);
+ return Allocatable;
+}
+
+/// getFrameIndexOffset - Returns the displacement from the frame register to
+/// the stack frame of the specified index. This is the default implementation
+/// which is likely incorrect for the target.
+int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
+ const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ return MFI->getObjectOffset(FI) + MFI->getStackSize() -
+ TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
+}
+
+/// getInitialFrameState - Returns a list of machine moves that are assumed
+/// on entry to a function.
+void
+TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
+ // Default is to do nothing.
+}
+
void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
const char *Modifier, bool NotRIPRel) {
const MachineOperand &MO = MI->getOperand(OpNo);
- const MRegisterInfo &RI = *TM.getRegisterInfo();
+ const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register: {
- assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should not make it this far!");
O << '%';
unsigned Reg = MO.getReg();
bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
const char Mode) {
- const MRegisterInfo &RI = *TM.getRegisterInfo();
+ const TargetRegisterInfo &RI = *TM.getRegisterInfo();
unsigned Reg = MO.getReg();
switch (Mode) {
default: return true; // Unknown mode.
const TargetRegisterClass *clas;
for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
- MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
+ TargetRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) ==
X86::RFP32RegisterClass ||
clas == X86::RFP64RegisterClass ||
if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
(Op.getOpcode()== ISD::CopyFromReg &&
(OpReg = cast<RegisterSDNode>(Op.getOperand(1))) &&
- OpReg->getReg() >= MRegisterInfo::FirstVirtualRegister))
+ OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister))
return true;
return false;
}
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
/// make the right decision when generating code for different targets.
const X86Subtarget *Subtarget;
- const MRegisterInfo *RegInfo;
+ const TargetRegisterInfo *RegInfo;
/// X86StackPtr - X86 physical register used as stack ptr.
unsigned X86StackPtr;
#include "llvm/Target/TargetInstrInfo.h"
#include "X86RegisterInfo.h"
#include "llvm/ADT/IndexedMap.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
namespace llvm {
class X86RegisterInfo;
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+ virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
// Return true if the instruction is a register to register move and
// leave the source and dest operands in the passed parameters.
void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
const char *Modifier) {
- const MRegisterInfo &RI = *TM.getRegisterInfo();
+ const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register: {
- if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
+ if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
MVT::ValueType VT = (strcmp(Modifier,"subreg64") == 0) ?
bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
const char Mode) {
- const MRegisterInfo &RI = *TM.getRegisterInfo();
+ const TargetRegisterInfo &RI = *TM.getRegisterInfo();
unsigned Reg = MO.getReg();
switch (Mode) {
default: return true; // Unknown mode.
#include "X86AsmPrinter.h"
#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
namespace llvm {
const char *Modifier = 0) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.isRegister()) {
- assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??");
+ assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ "Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else {
printOp(MO, Modifier);
//
//===----------------------------------------------------------------------===//
//
-// This file contains the X86 implementation of the MRegisterInfo class. This
-// file is responsible for the frame pointer elimination optimization on X86.
+// This file contains the X86 implementation of the TargetRegisterInfo class.
+// This file is responsible for the frame pointer elimination optimization
+// on X86.
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
//
-// This file contains the X86 implementation of the MRegisterInfo class.
+// This file contains the X86 implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "X86GenRegisterInfo.h.inc"
namespace llvm {
GR8Class::iterator
GR8Class::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo *RI = TM.getRegisterInfo();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
if (!Subtarget.is64Bit())
return X86_GR8_AO_32;
GR8Class::iterator
GR8Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo *RI = TM.getRegisterInfo();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
if (!Subtarget.is64Bit())
return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
GR16Class::iterator
GR16Class::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo *RI = TM.getRegisterInfo();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
if (Subtarget.is64Bit()) {
if (RI->hasFP(MF))
GR16Class::iterator
GR16Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo *RI = TM.getRegisterInfo();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
if (Subtarget.is64Bit()) {
if (RI->hasFP(MF))
GR32Class::iterator
GR32Class::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo *RI = TM.getRegisterInfo();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
if (Subtarget.is64Bit()) {
if (RI->hasFP(MF))
GR32Class::iterator
GR32Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo *RI = TM.getRegisterInfo();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
if (Subtarget.is64Bit()) {
if (RI->hasFP(MF))
GR64Class::iterator
GR64Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo *RI = TM.getRegisterInfo();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
return end()-2; // If so, don't allocate RSP or RBP
else
virtual X86TargetLowering *getTargetLowering() const {
return const_cast<X86TargetLowering*>(&TLInfo);
}
- virtual const MRegisterInfo *getRegisterInfo() const {
+ virtual const TargetRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
virtual const TargetData *getTargetData() const { return &DataLayout; }
// 6. Address expressions should become first-class entities.
// Simple copy instruction. isMoveInstr could easily be inferred from this,
-// as could MRegisterInfo::copyRegToReg.
+// as could TargetRegisterInfo::copyRegToReg.
def MOV8rr : Inst<(ops R8:$dst, R8:$src),
"mov $dst, $src", 0x88, MRMDestReg,
[(set R8:$dst, R8:$src)]>;
const std::string &TargetName = Target.getName();
std::string ClassName = TargetName + "GenRegisterInfo";
- OS << "#include \"llvm/Target/MRegisterInfo.h\"\n";
+ OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
OS << "#include <string>\n\n";
OS << "namespace llvm {\n\n";
- OS << "struct " << ClassName << " : public MRegisterInfo {\n"
+ OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
<< " " << ClassName
<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< " virtual int getDwarfRegNumFull(unsigned RegNum, "
// Emit the constructor of the class...
OS << ClassName << "::" << ClassName
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
- << " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1
+ << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
<< " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
UniqueIdentifier="{4FC737F1-C7A5-4376-A066-2A32D752A2FF}"
>
<File
- RelativePath="..\..\lib\Target\MRegisterInfo.cpp"
+ RelativePath="..\..\lib\Target\TargetRegisterInfo.cpp"
>
</File>
<File
UniqueIdentifier="{93995380-89BD-4b04-88EB-625FBE52EBFB}"
>
<File
- RelativePath="..\..\include\llvm\Target\MRegisterInfo.h"
+ RelativePath="..\..\include\llvm\Target\TargetRegisterInfo.h"
>
</File>
<File
projects / oota-llvm.git / commitdiff