[mips][msa] Summarize tests

Adds a comment to the start of each test summarizing the area the test covers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189465 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/Mips/msa/2r.ll b/test/CodeGen/Mips/msa/2r.ll
index b0061ae081147e051c7eeeee26ea5ffa4253b48d..7719b7cc0cf74192a723902569a6a305930a412f 100644 (file)
--- a/test/CodeGen/Mips/msa/2r.ll
+++ b/test/CodeGen/Mips/msa/2r.ll
@@ -1,3 +1,5 @@
+; Test the MSA intrinsics that are encoded with the 2R instruction format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/test/CodeGen/Mips/msa/2r_vector_scalar.ll
index 9d0765a2523b48791db9078f9d262ad1ba60c3ac..e03c9a3464fdc0c63a69e2034c2f9b0eb97bbefe 100644 (file)
--- a/test/CodeGen/Mips/msa/2r_vector_scalar.ll
+++ b/test/CodeGen/Mips/msa/2r_vector_scalar.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 2R instruction format and
+; convert scalars to vectors.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_fill_b_ARG1 = global i32 23, align 16

diff --git a/test/CodeGen/Mips/msa/2rf.ll b/test/CodeGen/Mips/msa/2rf.ll
index 6283cdf7294254dc41111dfa61a5e9ef62d363d6..74372871ae1b4e0f697cc83b786e89dd19d3932b 100644 (file)
--- a/test/CodeGen/Mips/msa/2rf.ll
+++ b/test/CodeGen/Mips/msa/2rf.ll
@@ -1,3 +1,5 @@
+; Test the MSA intrinsics that are encoded with the 2RF instruction format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_flog2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16

diff --git a/test/CodeGen/Mips/msa/2rf_exup.ll b/test/CodeGen/Mips/msa/2rf_exup.ll
index 54e416de7da22c3b6bbebec4631c2f0b24039334..ca47c95b8a27e8ec03a729b59479cad09f9497cb 100644 (file)
--- a/test/CodeGen/Mips/msa/2rf_exup.ll
+++ b/test/CodeGen/Mips/msa/2rf_exup.ll
@@ -1,3 +1,6 @@
+; Test the MSA floating point conversion intrinsics (e.g. float->double) that
+; are encoded with the 2RF instruction format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_fexupl_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16

diff --git a/test/CodeGen/Mips/msa/2rf_float_int.ll b/test/CodeGen/Mips/msa/2rf_float_int.ll
index 4b2ef22434c25e543ed557237feb049b2363d841..c76064a8bad0282c5703ba126ff249bac2566759 100644 (file)
--- a/test/CodeGen/Mips/msa/2rf_float_int.ll
+++ b/test/CodeGen/Mips/msa/2rf_float_int.ll
@@ -1,3 +1,6 @@
+; Test the MSA integer to floating point conversion intrinsics that are encoded
+; with the 2RF instruction format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16

diff --git a/test/CodeGen/Mips/msa/2rf_fq.ll b/test/CodeGen/Mips/msa/2rf_fq.ll
index e0f80c09f186341ad5e2c19bb85580db9c915b13..6808a2a99da1e4b1b33e9d3231233401da04f369 100644 (file)
--- a/test/CodeGen/Mips/msa/2rf_fq.ll
+++ b/test/CodeGen/Mips/msa/2rf_fq.ll
@@ -1,3 +1,6 @@
+; Test the MSA fixed-point to floating point conversion intrinsics that are
+; encoded with the 2RF instruction format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16

diff --git a/test/CodeGen/Mips/msa/2rf_int_float.ll b/test/CodeGen/Mips/msa/2rf_int_float.ll
index ef5c0c3db124e58e23d4c44e48451c1eabb82f32..b5eaad27e903090f89e8d4bd5b730b53172c0af1 100644 (file)
--- a/test/CodeGen/Mips/msa/2rf_int_float.ll
+++ b/test/CodeGen/Mips/msa/2rf_int_float.ll
@@ -1,3 +1,7 @@
+; Test the MSA floating point to integer intrinsics that are encoded with the
+; 2RF instruction format. This includes conversions but other instructions such
+; as fclass are also here.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16

diff --git a/test/CodeGen/Mips/msa/2rf_tq.ll b/test/CodeGen/Mips/msa/2rf_tq.ll
index 190f93ce6ec519e8110bb2874d43a735613effd0..aa7fc8636f414cc6424eee5335bf20ec40058c81 100644 (file)
--- a/test/CodeGen/Mips/msa/2rf_tq.ll
+++ b/test/CodeGen/Mips/msa/2rf_tq.ll
@@ -1,3 +1,6 @@
+; Test the MSA floating-point to fixed-point conversion intrinsics that are
+; encoded with the 2RF instruction format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16

diff --git a/test/CodeGen/Mips/msa/3r-a.ll b/test/CodeGen/Mips/msa/3r-a.ll
index 3cdeae4af3aa2b7e065b5151733821a8ac7e4eb5..79b82374a9cd297943a68d58e2eb5804a423466a 100644 (file)
--- a/test/CodeGen/Mips/msa/3r-a.ll
+++ b/test/CodeGen/Mips/msa/3r-a.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'a'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_add_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/3r-b.ll b/test/CodeGen/Mips/msa/3r-b.ll
index afcc391e5344a892e8e2ab06ce767d871a0d27c3..786c71f9614dd77273ee61658d267521c78ed820 100644 (file)
--- a/test/CodeGen/Mips/msa/3r-b.ll
+++ b/test/CodeGen/Mips/msa/3r-b.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'b'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/3r-c.ll b/test/CodeGen/Mips/msa/3r-c.ll
index 56636947ac9251a93aea52d07f84f3b26e4294f1..0ad6afbe429d2f5ddaf55f8068925fe77a310ca7 100644 (file)
--- a/test/CodeGen/Mips/msa/3r-c.ll
+++ b/test/CodeGen/Mips/msa/3r-c.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'c'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_ceq_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/3r-d.ll b/test/CodeGen/Mips/msa/3r-d.ll
index 3b20743a5da4c69f8804151c37d517858756124c..ee94e5650d8b56346bc30c528b7be5d3d749a845 100644 (file)
--- a/test/CodeGen/Mips/msa/3r-d.ll
+++ b/test/CodeGen/Mips/msa/3r-d.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'd'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/3r-i.ll b/test/CodeGen/Mips/msa/3r-i.ll
index b5c6a305d657e726489e0a64dad52918ca1409a8..2f9acd1f1ed4ececb930c3fed3e69fb9e96841ea 100644 (file)
--- a/test/CodeGen/Mips/msa/3r-i.ll
+++ b/test/CodeGen/Mips/msa/3r-i.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'i'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_ilvev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/3r-m.ll b/test/CodeGen/Mips/msa/3r-m.ll
index 7f0cb363d9283585e3ce7941869bcb83f8858949..041d603dd4d911dce8dec5c45e2c3bdba610c823 100644 (file)
--- a/test/CodeGen/Mips/msa/3r-m.ll
+++ b/test/CodeGen/Mips/msa/3r-m.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'm'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_max_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/3r-p.ll b/test/CodeGen/Mips/msa/3r-p.ll
index 1386533296bbdf19286071527e4a2ca4bb2bd48f..f328cad614d4cc3aa3506c79f0fc1eb4fdf95545 100644 (file)
--- a/test/CodeGen/Mips/msa/3r-p.ll
+++ b/test/CodeGen/Mips/msa/3r-p.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'p'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_pckev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/3r-s.ll b/test/CodeGen/Mips/msa/3r-s.ll
index 6c977c636d322f871ce01a626761c48a21a3a809..bcc6ba7829c9ed8cecfcf497eb9233fc881795b9 100644 (file)
--- a/test/CodeGen/Mips/msa/3r-s.ll
+++ b/test/CodeGen/Mips/msa/3r-s.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 's'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/3r-v.ll b/test/CodeGen/Mips/msa/3r-v.ll
index 5c2ab9b2280a0360031404dbbfa746a43e9128fa..055491d6a7f7a1e94888613ff98c6304b97ba6fa 100644 (file)
--- a/test/CodeGen/Mips/msa/3r-v.ll
+++ b/test/CodeGen/Mips/msa/3r-v.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'v'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_vshf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/3r_4r.ll b/test/CodeGen/Mips/msa/3r_4r.ll
index c7d189e926df3feae8d131fd36791d9e39c779ef..52f3cd3b8808f3ccf842d8c4812cad07f1b2ecaf 100644 (file)
--- a/test/CodeGen/Mips/msa/3r_4r.ll
+++ b/test/CodeGen/Mips/msa/3r_4r.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format and
+; use the result as a third operand.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_maddv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/3r_4r_widen.ll b/test/CodeGen/Mips/msa/3r_4r_widen.ll
index 891d11a2f4e01d911c63385fc838ef5340727406..63592b4b052a83b439d50f343394ce1cd4a9125e 100644 (file)
--- a/test/CodeGen/Mips/msa/3r_4r_widen.ll
+++ b/test/CodeGen/Mips/msa/3r_4r_widen.ll
@@ -1,3 +1,7 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format and
+; use the result as a third operand and results in wider elements than the
+; operands had.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_dpadd_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16

diff --git a/test/CodeGen/Mips/msa/3r_splat.ll b/test/CodeGen/Mips/msa/3r_splat.ll
index dad61eb8b61e8d0a70ba55780613e8fcb3375fef..001f723f7d445a35f58caa649c6e8f9745425f36 100644 (file)
--- a/test/CodeGen/Mips/msa/3r_splat.ll
+++ b/test/CodeGen/Mips/msa/3r_splat.ll
@@ -1,3 +1,6 @@
+; Test the MSA splat intrinsics that are encoded with the 3R instruction
+; format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_splat_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/3rf.ll b/test/CodeGen/Mips/msa/3rf.ll
index e2d5a208c086b23dd5206cc8d0a0895b7986449c..265c8fb4b0762e481badb6710e769d578f330641 100644 (file)
--- a/test/CodeGen/Mips/msa/3rf.ll
+++ b/test/CodeGen/Mips/msa/3rf.ll
@@ -1,3 +1,5 @@
+; Test the MSA intrinsics that are encoded with the 3RF instruction format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16

diff --git a/test/CodeGen/Mips/msa/3rf_4rf.ll b/test/CodeGen/Mips/msa/3rf_4rf.ll
index cef38fd6e9a1f4120d99570924193710bcff4746..913fe70c06e32b222a121c429a00a10db6874869 100644 (file)
--- a/test/CodeGen/Mips/msa/3rf_4rf.ll
+++ b/test/CodeGen/Mips/msa/3rf_4rf.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3RF instruction format and
+; use the result as a third operand.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_fmadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16

diff --git a/test/CodeGen/Mips/msa/3rf_4rf_q.ll b/test/CodeGen/Mips/msa/3rf_4rf_q.ll
index b490e180385e96634468b08fb18e4fddb8ff0440..4fbc69d3c4d78b1c291ad2d0a0832207288c241d 100644 (file)
--- a/test/CodeGen/Mips/msa/3rf_4rf_q.ll
+++ b/test/CodeGen/Mips/msa/3rf_4rf_q.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3RF instruction format and
+; use the result as a third operand and perform fixed-point operations.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16

diff --git a/test/CodeGen/Mips/msa/3rf_exdo.ll b/test/CodeGen/Mips/msa/3rf_exdo.ll
index 45a80116e006168a4d8bdc103bbdd356b4aa327e..d5713cb9aea8f4e4e3bc78e201f3100c254ae8f6 100644 (file)
--- a/test/CodeGen/Mips/msa/3rf_exdo.ll
+++ b/test/CodeGen/Mips/msa/3rf_exdo.ll
@@ -1,3 +1,6 @@
+; Test the MSA floating-point conversion intrinsics that are encoded with the
+; 3RF instruction format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16

diff --git a/test/CodeGen/Mips/msa/3rf_float_int.ll b/test/CodeGen/Mips/msa/3rf_float_int.ll
index 6b9998d4b1266ceedd44de225c54af638886d758..6fd46f5e7f23b9be0cb7708317304de774f4ee62 100644 (file)
--- a/test/CodeGen/Mips/msa/3rf_float_int.ll
+++ b/test/CodeGen/Mips/msa/3rf_float_int.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3RF instruction format and
+; take an integer as an operand.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_fexp2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16

diff --git a/test/CodeGen/Mips/msa/3rf_int_float.ll b/test/CodeGen/Mips/msa/3rf_int_float.ll
index 112f1177b903ddb4ad9e6dd518d303bd59444ecd..3d10ad3ca70af0acb675e8814655ca8a15362de7 100644 (file)
--- a/test/CodeGen/Mips/msa/3rf_int_float.ll
+++ b/test/CodeGen/Mips/msa/3rf_int_float.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3RF instruction format and
+; produce an integer as a result.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_fceq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16

diff --git a/test/CodeGen/Mips/msa/3rf_q.ll b/test/CodeGen/Mips/msa/3rf_q.ll
index 748fd9c686945b171635aede762c612554f9d58b..857ae3f617d696308e61e04a908cc50a84458b9e 100644 (file)
--- a/test/CodeGen/Mips/msa/3rf_q.ll
+++ b/test/CodeGen/Mips/msa/3rf_q.ll
@@ -1,3 +1,6 @@
+; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction
+; format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16

diff --git a/test/CodeGen/Mips/msa/bit.ll b/test/CodeGen/Mips/msa/bit.ll
index fe36ed7a0a3d9ee83b6cb86d6df624e6190ca382..28bf0e75bc09b79c4b0a2eeabcd4e23e8eca6bc9 100644 (file)
--- a/test/CodeGen/Mips/msa/bit.ll
+++ b/test/CodeGen/Mips/msa/bit.ll
@@ -1,3 +1,5 @@
+; Test the MSA intrinsics that are encoded with the BIT instruction format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_sat_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/bitcast.ll b/test/CodeGen/Mips/msa/bitcast.ll
index fccdbf6df215571d6f777163cfbf0d41f2f11937..03195a84592e21b611cd78ec011f3a93b341a978 100644 (file)
--- a/test/CodeGen/Mips/msa/bitcast.ll
+++ b/test/CodeGen/Mips/msa/bitcast.ll
@@ -1,3 +1,5 @@
+; Test the bitcast operation for big-endian and little-endian.
+
 ; RUN: llc -march=mipsel -mattr=+msa < %s | FileCheck -check-prefix=LITENDIAN %s
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=BIGENDIAN %s
 

diff --git a/test/CodeGen/Mips/msa/elm_copy.ll b/test/CodeGen/Mips/msa/elm_copy.ll
index f31bb506db2f6b4a5b8531947e76994fbaac6432..a966043b5de6700d9e0621320d64c42de7532520 100644 (file)
--- a/test/CodeGen/Mips/msa/elm_copy.ll
+++ b/test/CodeGen/Mips/msa/elm_copy.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the ELM instruction format and
+; are element extraction operations.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/elm_insv.ll b/test/CodeGen/Mips/msa/elm_insv.ll
index be0b5c4f2d304367d91cf8ad4d7237886078dd62..eb7dbf515d24e0d7b27da4879ad793e344213bda 100644 (file)
--- a/test/CodeGen/Mips/msa/elm_insv.ll
+++ b/test/CodeGen/Mips/msa/elm_insv.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
-;
 ; Test the MSA element insertion intrinsics that are encoded with the ELM
 ; instruction format.
 
+; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+
 @llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
 @llvm_mips_insert_b_ARG3 = global i32 27, align 16
 @llvm_mips_insert_b_RES  = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

diff --git a/test/CodeGen/Mips/msa/elm_shift_slide.ll b/test/CodeGen/Mips/msa/elm_shift_slide.ll
index 5bddeaf203de1f2b641c6d8816d9939dc3eeff5d..2568ba01f7b92c4f5d33ba519fd7dbb4cf2e8b40 100644 (file)
--- a/test/CodeGen/Mips/msa/elm_shift_slide.ll
+++ b/test/CodeGen/Mips/msa/elm_shift_slide.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the ELM instruction format and
+; are either shifts or slides.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/i5-a.ll b/test/CodeGen/Mips/msa/i5-a.ll
index fe93534b2ff68380a32db590b8b6f114f8f94f6e..f158494f35f4d6f3f25d82b5b54699ffb7e7b29b 100644 (file)
--- a/test/CodeGen/Mips/msa/i5-a.ll
+++ b/test/CodeGen/Mips/msa/i5-a.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the I5 instruction format.
+; There are lots of these so this covers those beginning with 'a'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_addvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/i5-b.ll b/test/CodeGen/Mips/msa/i5-b.ll
index 87d4527124a1b6bb1d837e59146c8cf1ca5e35be..165c9a449a6616f04224a3ff9a10290d0f431d26 100644 (file)
--- a/test/CodeGen/Mips/msa/i5-b.ll
+++ b/test/CodeGen/Mips/msa/i5-b.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the I5 instruction format.
+; There are lots of these so this covers those beginning with 'b'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/i5-c.ll b/test/CodeGen/Mips/msa/i5-c.ll
index 5e9eed8b2d075ce56eb1358f7bf6f9131095e04e..e9ebee40adcf32d2a01fc8f80d2f308e3c4a6955 100644 (file)
--- a/test/CodeGen/Mips/msa/i5-c.ll
+++ b/test/CodeGen/Mips/msa/i5-c.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the I5 instruction format.
+; There are lots of these so this covers those beginning with 'c'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/i5-m.ll b/test/CodeGen/Mips/msa/i5-m.ll
index 9e35848546154983801eea974df3b0344830a675..a4677194acb305ef55e4c87de25d3463296795d0 100644 (file)
--- a/test/CodeGen/Mips/msa/i5-m.ll
+++ b/test/CodeGen/Mips/msa/i5-m.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the I5 instruction format.
+; There are lots of these so this covers those beginning with 'm'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_maxi_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/i5-s.ll b/test/CodeGen/Mips/msa/i5-s.ll
index 058e0edba82559b90cfb258dc640550d8b734c53..616085c7f45aac568c9822801640bf7e326e15de 100644 (file)
--- a/test/CodeGen/Mips/msa/i5-s.ll
+++ b/test/CodeGen/Mips/msa/i5-s.ll
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the I5 instruction format.
+; There are lots of these so this covers those beginning with 's'
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_subvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/i8.ll b/test/CodeGen/Mips/msa/i8.ll
index 5587848158fcc0b51c2e5b35fbba08aba42ce85c..e629b046624479b12e00fa98a9c2a09b82663060 100644 (file)
--- a/test/CodeGen/Mips/msa/i8.ll
+++ b/test/CodeGen/Mips/msa/i8.ll
@@ -1,3 +1,5 @@
+; Test the MSA intrinsics that are encoded with the I8 instruction format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 @llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

diff --git a/test/CodeGen/Mips/msa/spill.ll b/test/CodeGen/Mips/msa/spill.ll
index 33f4a441e2736386519894f7d8df3b9ebd4d8205..5c927bffffff6072e4ff3750666720201ccef9a1 100644 (file)
--- a/test/CodeGen/Mips/msa/spill.ll
+++ b/test/CodeGen/Mips/msa/spill.ll
@@ -1,3 +1,6 @@
+; Test that the correct instruction is chosen for spill and reload by trying
+; to have 33 live MSA registers simultaneously
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
 
 define i32 @test_i8(<16 x i8>* %p0, <16 x i8>* %q1) nounwind {

diff --git a/test/CodeGen/Mips/msa/vec.ll b/test/CodeGen/Mips/msa/vec.ll
index eb293e8607bd5b4a0b1d532347f84113be5c3acc..13a23fa272138ae574590c245d145eedbd9bf7b5 100644 (file)
--- a/test/CodeGen/Mips/msa/vec.ll
+++ b/test/CodeGen/Mips/msa/vec.ll
@@ -1,7 +1,7 @@
+; Test the MSA intrinsics that are encoded with the VEC instruction format.
+
 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=ANYENDIAN %s
 ; RUN: llc -march=mipsel -mattr=+msa < %s | FileCheck -check-prefix=ANYENDIAN %s
-; 
-; Test the MSA intrinsics that are encoded with the VEC instruction format.
 
 @llvm_mips_and_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
 @llvm_mips_and_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16