1 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
3 @llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
4 @llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
6 define void @llvm_mips_andi_b_test() nounwind {
8 %0 = load <16 x i8>* @llvm_mips_andi_b_ARG1
9 %1 = tail call <16 x i8> @llvm.mips.andi.b(<16 x i8> %0, i32 25)
10 store <16 x i8> %1, <16 x i8>* @llvm_mips_andi_b_RES
14 declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32) nounwind
16 ; CHECK: llvm_mips_andi_b_test:
20 ; CHECK: .size llvm_mips_andi_b_test
22 @llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
23 @llvm_mips_bmnzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
25 define void @llvm_mips_bmnzi_b_test() nounwind {
27 %0 = load <16 x i8>* @llvm_mips_bmnzi_b_ARG1
28 %1 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, i32 25)
29 store <16 x i8> %1, <16 x i8>* @llvm_mips_bmnzi_b_RES
33 declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, i32) nounwind
35 ; CHECK: llvm_mips_bmnzi_b_test:
39 ; CHECK: .size llvm_mips_bmnzi_b_test
41 @llvm_mips_bmzi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
42 @llvm_mips_bmzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
44 define void @llvm_mips_bmzi_b_test() nounwind {
46 %0 = load <16 x i8>* @llvm_mips_bmzi_b_ARG1
47 %1 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, i32 25)
48 store <16 x i8> %1, <16 x i8>* @llvm_mips_bmzi_b_RES
52 declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, i32) nounwind
54 ; CHECK: llvm_mips_bmzi_b_test:
58 ; CHECK: .size llvm_mips_bmzi_b_test
60 @llvm_mips_bseli_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
61 @llvm_mips_bseli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
63 define void @llvm_mips_bseli_b_test() nounwind {
65 %0 = load <16 x i8>* @llvm_mips_bseli_b_ARG1
66 %1 = tail call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %0, i32 25)
67 store <16 x i8> %1, <16 x i8>* @llvm_mips_bseli_b_RES
71 declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, i32) nounwind
73 ; CHECK: llvm_mips_bseli_b_test:
77 ; CHECK: .size llvm_mips_bseli_b_test
79 @llvm_mips_nori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
80 @llvm_mips_nori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
82 define void @llvm_mips_nori_b_test() nounwind {
84 %0 = load <16 x i8>* @llvm_mips_nori_b_ARG1
85 %1 = tail call <16 x i8> @llvm.mips.nori.b(<16 x i8> %0, i32 25)
86 store <16 x i8> %1, <16 x i8>* @llvm_mips_nori_b_RES
90 declare <16 x i8> @llvm.mips.nori.b(<16 x i8>, i32) nounwind
92 ; CHECK: llvm_mips_nori_b_test:
96 ; CHECK: .size llvm_mips_nori_b_test
98 @llvm_mips_ori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
99 @llvm_mips_ori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
101 define void @llvm_mips_ori_b_test() nounwind {
103 %0 = load <16 x i8>* @llvm_mips_ori_b_ARG1
104 %1 = tail call <16 x i8> @llvm.mips.ori.b(<16 x i8> %0, i32 25)
105 store <16 x i8> %1, <16 x i8>* @llvm_mips_ori_b_RES
109 declare <16 x i8> @llvm.mips.ori.b(<16 x i8>, i32) nounwind
111 ; CHECK: llvm_mips_ori_b_test:
115 ; CHECK: .size llvm_mips_ori_b_test
117 @llvm_mips_shf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
118 @llvm_mips_shf_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
120 define void @llvm_mips_shf_b_test() nounwind {
122 %0 = load <16 x i8>* @llvm_mips_shf_b_ARG1
123 %1 = tail call <16 x i8> @llvm.mips.shf.b(<16 x i8> %0, i32 25)
124 store <16 x i8> %1, <16 x i8>* @llvm_mips_shf_b_RES
128 declare <16 x i8> @llvm.mips.shf.b(<16 x i8>, i32) nounwind
130 ; CHECK: llvm_mips_shf_b_test:
134 ; CHECK: .size llvm_mips_shf_b_test
136 @llvm_mips_shf_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
137 @llvm_mips_shf_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
139 define void @llvm_mips_shf_h_test() nounwind {
141 %0 = load <8 x i16>* @llvm_mips_shf_h_ARG1
142 %1 = tail call <8 x i16> @llvm.mips.shf.h(<8 x i16> %0, i32 25)
143 store <8 x i16> %1, <8 x i16>* @llvm_mips_shf_h_RES
147 declare <8 x i16> @llvm.mips.shf.h(<8 x i16>, i32) nounwind
149 ; CHECK: llvm_mips_shf_h_test:
153 ; CHECK: .size llvm_mips_shf_h_test
155 @llvm_mips_shf_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
156 @llvm_mips_shf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
158 define void @llvm_mips_shf_w_test() nounwind {
160 %0 = load <4 x i32>* @llvm_mips_shf_w_ARG1
161 %1 = tail call <4 x i32> @llvm.mips.shf.w(<4 x i32> %0, i32 25)
162 store <4 x i32> %1, <4 x i32>* @llvm_mips_shf_w_RES
166 declare <4 x i32> @llvm.mips.shf.w(<4 x i32>, i32) nounwind
168 ; CHECK: llvm_mips_shf_w_test:
172 ; CHECK: .size llvm_mips_shf_w_test
174 @llvm_mips_xori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
175 @llvm_mips_xori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
177 define void @llvm_mips_xori_b_test() nounwind {
179 %0 = load <16 x i8>* @llvm_mips_xori_b_ARG1
180 %1 = tail call <16 x i8> @llvm.mips.xori.b(<16 x i8> %0, i32 25)
181 store <16 x i8> %1, <16 x i8>* @llvm_mips_xori_b_RES
185 declare <16 x i8> @llvm.mips.xori.b(<16 x i8>, i32) nounwind
187 ; CHECK: llvm_mips_xori_b_test:
191 ; CHECK: .size llvm_mips_xori_b_test