Fix TableGen warnings. This partly reverts my previous change to this file,

leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78815 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index d2ef593c10179bb1a2be809c88ee5cae47dc3b54..91975eed4e8f706b64d67c47d578cec07d02da76 100644 (file)
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -113,8 +113,8 @@ def addrmode_neonldstm : Operand<i32>,
 // NEON load / store instructions
 //===----------------------------------------------------------------------===//
 
-let mayLoad = 1 in {
 /* TODO: Take advantage of vldm.
+let mayLoad = 1 in {
 def VLDMD : NI<(outs),
                (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
                NoItinerary,
@@ -134,6 +134,7 @@ def VLDMS : NI<(outs),
   let Inst{20}    = 1;
   let Inst{11-9}  = 0b101;
 }
+}
 */
 
 // Use vldmia to load a Q register as a D register pair.
@@ -148,6 +149,18 @@ def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
   let Inst{11-9}  = 0b101;
 }
 
+// Use vstmia to store a Q register as a D register pair.
+def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
+               NoItinerary,
+               "vstmia $addr, ${src:dregpair}",
+               [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
+  let Inst{27-25} = 0b110;
+  let Inst{24}    = 0; // P bit
+  let Inst{23}    = 1; // U bit
+  let Inst{20}    = 0;
+  let Inst{11-9}  = 0b101;
+}
+
 //   VLD1     : Vector Load (multiple single elements)
 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
   : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
@@ -172,6 +185,8 @@ def  VLD1q32  : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1>;
 def  VLD1qf   : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
 def  VLD1q64  : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
 
+let mayLoad = 1 in {
+
 //   VLD2     : Vector Load (multiple 2-element structures)
 class VLD2D<string OpcodeStr>
   : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
@@ -204,19 +219,6 @@ def  VLD4d16  : VLD4D<"vld4.16">;
 def  VLD4d32  : VLD4D<"vld4.32">;
 }
 
-let mayStore = 1 in {
-// Use vstmia to store a Q register as a D register pair.
-def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
-               NoItinerary,
-               "vstmia $addr, ${src:dregpair}",
-               [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
-  let Inst{27-25} = 0b110;
-  let Inst{24}    = 0; // P bit
-  let Inst{23}    = 1; // U bit
-  let Inst{20}    = 0;
-  let Inst{11-9}  = 0b101;
-}
-
 //   VST1     : Vector Store (multiple single elements)
 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
   : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
@@ -241,6 +243,8 @@ def  VST1q32  : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
 def  VST1qf   : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
 def  VST1q64  : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
 
+let mayStore = 1 in {
+
 //   VST2     : Vector Store (multiple 2-element structures)
 class VST2D<string OpcodeStr>
   : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,