1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
71 def SDTARMVLD2 : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
72 def SDTARMVLD3 : SDTypeProfile<3, 1, [SDTCisSameAs<0, 1>,
73 SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>;
74 def SDTARMVLD4 : SDTypeProfile<4, 1, [SDTCisSameAs<0, 1>,
76 SDTCisSameAs<0, 3>, SDTCisPtrTy<4>]>;
77 def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD2,
78 [SDNPHasChain, SDNPMayLoad]>;
79 def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3,
80 [SDNPHasChain, SDNPMayLoad]>;
81 def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4,
82 [SDNPHasChain, SDNPMayLoad]>;
84 def SDTARMVST2 : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>]>;
85 def SDTARMVST3 : SDTypeProfile<0, 4, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
87 def SDTARMVST4 : SDTypeProfile<0, 5, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
91 def NEONvst2d : SDNode<"ARMISD::VST2D", SDTARMVST2,
92 [SDNPHasChain, SDNPMayStore]>;
93 def NEONvst3d : SDNode<"ARMISD::VST3D", SDTARMVST3,
94 [SDNPHasChain, SDNPMayStore]>;
95 def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4,
96 [SDNPHasChain, SDNPMayStore]>;
98 //===----------------------------------------------------------------------===//
99 // NEON operand definitions
100 //===----------------------------------------------------------------------===//
102 // addrmode_neonldstm := reg
104 /* TODO: Take advantage of vldm.
105 def addrmode_neonldstm : Operand<i32>,
106 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
107 let PrintMethod = "printAddrNeonLdStMOperand";
108 let MIOperandInfo = (ops GPR, i32imm);
112 //===----------------------------------------------------------------------===//
113 // NEON load / store instructions
114 //===----------------------------------------------------------------------===//
117 /* TODO: Take advantage of vldm.
118 def VLDMD : NI<(outs),
119 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
121 "vldm${addr:submode} ${addr:base}, $dst1",
123 let Inst{27-25} = 0b110;
125 let Inst{11-9} = 0b101;
128 def VLDMS : NI<(outs),
129 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
131 "vldm${addr:submode} ${addr:base}, $dst1",
133 let Inst{27-25} = 0b110;
135 let Inst{11-9} = 0b101;
139 // Use vldmia to load a Q register as a D register pair.
140 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
142 "vldmia $addr, ${dst:dregpair}",
143 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
144 let Inst{27-25} = 0b110;
145 let Inst{24} = 0; // P bit
146 let Inst{23} = 1; // U bit
148 let Inst{11-9} = 0b101;
151 // VLD1 : Vector Load (multiple single elements)
152 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
153 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
155 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
156 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
157 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
158 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
160 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
161 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
163 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1>;
164 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1>;
165 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1>;
166 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1>;
167 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1>;
169 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1>;
170 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1>;
171 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1>;
172 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
173 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
175 // VLD2 : Vector Load (multiple 2-element structures)
176 class VLD2D<string OpcodeStr>
177 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
179 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>;
181 def VLD2d8 : VLD2D<"vld2.8">;
182 def VLD2d16 : VLD2D<"vld2.16">;
183 def VLD2d32 : VLD2D<"vld2.32">;
185 // VLD3 : Vector Load (multiple 3-element structures)
186 class VLD3D<string OpcodeStr>
187 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
189 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>;
191 def VLD3d8 : VLD3D<"vld3.8">;
192 def VLD3d16 : VLD3D<"vld3.16">;
193 def VLD3d32 : VLD3D<"vld3.32">;
195 // VLD4 : Vector Load (multiple 4-element structures)
196 class VLD4D<string OpcodeStr>
197 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
198 (ins addrmode6:$addr),
200 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>;
202 def VLD4d8 : VLD4D<"vld4.8">;
203 def VLD4d16 : VLD4D<"vld4.16">;
204 def VLD4d32 : VLD4D<"vld4.32">;
207 let mayStore = 1 in {
208 // Use vstmia to store a Q register as a D register pair.
209 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
211 "vstmia $addr, ${src:dregpair}",
212 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
213 let Inst{27-25} = 0b110;
214 let Inst{24} = 0; // P bit
215 let Inst{23} = 1; // U bit
217 let Inst{11-9} = 0b101;
220 // VST1 : Vector Store (multiple single elements)
221 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
222 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
224 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
225 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
226 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
227 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
229 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
230 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
232 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
233 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1>;
234 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1>;
235 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1>;
236 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1>;
238 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1>;
239 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1>;
240 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
241 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
242 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
244 // VST2 : Vector Store (multiple 2-element structures)
245 class VST2D<string OpcodeStr>
246 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
247 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), []>;
249 def VST2d8 : VST2D<"vst2.8">;
250 def VST2d16 : VST2D<"vst2.16">;
251 def VST2d32 : VST2D<"vst2.32">;
253 // VST3 : Vector Store (multiple 3-element structures)
254 class VST3D<string OpcodeStr>
255 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
257 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), []>;
259 def VST3d8 : VST3D<"vst3.8">;
260 def VST3d16 : VST3D<"vst3.16">;
261 def VST3d32 : VST3D<"vst3.32">;
263 // VST4 : Vector Store (multiple 4-element structures)
264 class VST4D<string OpcodeStr>
265 : NLdSt<(outs), (ins addrmode6:$addr,
266 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
267 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), []>;
269 def VST4d8 : VST4D<"vst4.8">;
270 def VST4d16 : VST4D<"vst4.16">;
271 def VST4d32 : VST4D<"vst4.32">;
275 //===----------------------------------------------------------------------===//
276 // NEON pattern fragments
277 //===----------------------------------------------------------------------===//
279 // Extract D sub-registers of Q registers.
280 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
281 def DSubReg_i8_reg : SDNodeXForm<imm, [{
282 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
284 def DSubReg_i16_reg : SDNodeXForm<imm, [{
285 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
287 def DSubReg_i32_reg : SDNodeXForm<imm, [{
288 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
290 def DSubReg_f64_reg : SDNodeXForm<imm, [{
291 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
294 // Extract S sub-registers of Q registers.
295 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
296 def SSubReg_f32_reg : SDNodeXForm<imm, [{
297 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
300 // Translate lane numbers from Q registers to D subregs.
301 def SubReg_i8_lane : SDNodeXForm<imm, [{
302 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
304 def SubReg_i16_lane : SDNodeXForm<imm, [{
305 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
307 def SubReg_i32_lane : SDNodeXForm<imm, [{
308 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
311 //===----------------------------------------------------------------------===//
312 // Instruction Classes
313 //===----------------------------------------------------------------------===//
315 // Basic 2-register operations, both double- and quad-register.
316 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
317 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
318 ValueType ResTy, ValueType OpTy, SDNode OpNode>
319 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
320 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
321 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
322 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
323 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
324 ValueType ResTy, ValueType OpTy, SDNode OpNode>
325 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
326 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
327 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
329 // Basic 2-register operations, scalar single-precision.
330 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
331 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
332 ValueType ResTy, ValueType OpTy, SDNode OpNode>
333 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
334 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
335 NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
337 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
338 : NEONFPPat<(ResTy (OpNode SPR:$a)),
340 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
343 // Basic 2-register intrinsics, both double- and quad-register.
344 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
345 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
346 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
347 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
348 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
349 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
350 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
351 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
352 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
353 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
354 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
355 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
357 // Basic 2-register intrinsics, scalar single-precision
358 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
359 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
360 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
361 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
362 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
363 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
365 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
366 : NEONFPPat<(f32 (OpNode SPR:$a)),
368 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
371 // Narrow 2-register intrinsics.
372 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
373 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
374 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
375 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
376 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
377 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
379 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
380 // derived from N2VImm instead of N2V because of the way the size is encoded.)
381 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
382 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
384 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
385 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
386 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
388 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
389 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
390 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
391 (ins DPR:$src1, DPR:$src2), NoItinerary,
392 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
393 "$src1 = $dst1, $src2 = $dst2", []>;
394 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
395 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
396 (ins QPR:$src1, QPR:$src2), NoItinerary,
397 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
398 "$src1 = $dst1, $src2 = $dst2", []>;
400 // Basic 3-register operations, both double- and quad-register.
401 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
402 string OpcodeStr, ValueType ResTy, ValueType OpTy,
403 SDNode OpNode, bit Commutable>
404 : N3V<op24, op23, op21_20, op11_8, 0, op4,
405 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
406 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
407 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
408 let isCommutable = Commutable;
410 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
411 string OpcodeStr, ValueType ResTy, ValueType OpTy,
412 SDNode OpNode, bit Commutable>
413 : N3V<op24, op23, op21_20, op11_8, 1, op4,
414 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
415 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
416 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
417 let isCommutable = Commutable;
420 // Basic 3-register operations, scalar single-precision
421 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
422 string OpcodeStr, ValueType ResTy, ValueType OpTy,
423 SDNode OpNode, bit Commutable>
424 : N3V<op24, op23, op21_20, op11_8, 0, op4,
425 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary,
426 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
427 let isCommutable = Commutable;
429 class N3VDsPat<SDNode OpNode, NeonI Inst>
430 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
432 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
433 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
436 // Basic 3-register intrinsics, both double- and quad-register.
437 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
438 string OpcodeStr, ValueType ResTy, ValueType OpTy,
439 Intrinsic IntOp, bit Commutable>
440 : N3V<op24, op23, op21_20, op11_8, 0, op4,
441 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
442 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
443 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
444 let isCommutable = Commutable;
446 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
447 string OpcodeStr, ValueType ResTy, ValueType OpTy,
448 Intrinsic IntOp, bit Commutable>
449 : N3V<op24, op23, op21_20, op11_8, 1, op4,
450 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
451 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
452 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
453 let isCommutable = Commutable;
456 // Multiply-Add/Sub operations, both double- and quad-register.
457 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
458 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
459 : N3V<op24, op23, op21_20, op11_8, 0, op4,
460 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
461 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
462 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
463 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
464 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
465 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
466 : N3V<op24, op23, op21_20, op11_8, 1, op4,
467 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
468 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
469 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
470 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
472 // Multiply-Add/Sub operations, scalar single-precision
473 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
474 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
475 : N3V<op24, op23, op21_20, op11_8, 0, op4,
476 (outs DPR_VFP2:$dst),
477 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary,
478 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
480 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
481 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
483 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
484 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
485 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
488 // Neon 3-argument intrinsics, both double- and quad-register.
489 // The destination register is also used as the first source operand register.
490 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
491 string OpcodeStr, ValueType ResTy, ValueType OpTy,
493 : N3V<op24, op23, op21_20, op11_8, 0, op4,
494 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
495 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
496 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
497 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
498 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
499 string OpcodeStr, ValueType ResTy, ValueType OpTy,
501 : N3V<op24, op23, op21_20, op11_8, 1, op4,
502 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
503 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
504 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
505 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
507 // Neon Long 3-argument intrinsic. The destination register is
508 // a quad-register and is also used as the first source operand register.
509 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
510 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
511 : N3V<op24, op23, op21_20, op11_8, 0, op4,
512 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
513 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
515 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
517 // Narrowing 3-register intrinsics.
518 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
519 string OpcodeStr, ValueType TyD, ValueType TyQ,
520 Intrinsic IntOp, bit Commutable>
521 : N3V<op24, op23, op21_20, op11_8, 0, op4,
522 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
523 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
524 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
525 let isCommutable = Commutable;
528 // Long 3-register intrinsics.
529 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
530 string OpcodeStr, ValueType TyQ, ValueType TyD,
531 Intrinsic IntOp, bit Commutable>
532 : N3V<op24, op23, op21_20, op11_8, 0, op4,
533 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
534 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
535 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
536 let isCommutable = Commutable;
539 // Wide 3-register intrinsics.
540 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
541 string OpcodeStr, ValueType TyQ, ValueType TyD,
542 Intrinsic IntOp, bit Commutable>
543 : N3V<op24, op23, op21_20, op11_8, 0, op4,
544 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary,
545 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
546 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
547 let isCommutable = Commutable;
550 // Pairwise long 2-register intrinsics, both double- and quad-register.
551 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
552 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
553 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
554 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
555 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
556 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
557 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
558 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
559 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
560 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
561 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
562 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
564 // Pairwise long 2-register accumulate intrinsics,
565 // both double- and quad-register.
566 // The destination register is also used as the first source operand register.
567 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
568 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
569 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
570 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
571 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
572 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
573 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
574 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
575 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
576 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
577 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
578 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
579 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
580 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
582 // Shift by immediate,
583 // both double- and quad-register.
584 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
585 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
586 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
587 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
588 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
589 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
590 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
591 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
592 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
593 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
594 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
595 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
597 // Long shift by immediate.
598 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
599 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
600 ValueType OpTy, SDNode OpNode>
601 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
602 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
603 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
604 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
605 (i32 imm:$SIMM))))]>;
607 // Narrow shift by immediate.
608 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
609 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
610 ValueType OpTy, SDNode OpNode>
611 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
612 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
613 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
614 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
615 (i32 imm:$SIMM))))]>;
617 // Shift right by immediate and accumulate,
618 // both double- and quad-register.
619 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
620 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
621 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
622 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
624 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
625 [(set DPR:$dst, (Ty (add DPR:$src1,
626 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
627 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
628 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
629 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
630 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
632 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
633 [(set QPR:$dst, (Ty (add QPR:$src1,
634 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
636 // Shift by immediate and insert,
637 // both double- and quad-register.
638 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
639 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
640 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
641 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
643 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
644 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
645 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
646 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
647 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
648 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
650 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
651 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
653 // Convert, with fractional bits immediate,
654 // both double- and quad-register.
655 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
656 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
658 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
659 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
660 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
661 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
662 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
663 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
665 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
666 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
667 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
668 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
670 //===----------------------------------------------------------------------===//
672 //===----------------------------------------------------------------------===//
674 // Neon 3-register vector operations.
676 // First with only element sizes of 8, 16 and 32 bits:
677 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
678 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
679 // 64-bit vector types.
680 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
681 v8i8, v8i8, OpNode, Commutable>;
682 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
683 v4i16, v4i16, OpNode, Commutable>;
684 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
685 v2i32, v2i32, OpNode, Commutable>;
687 // 128-bit vector types.
688 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
689 v16i8, v16i8, OpNode, Commutable>;
690 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
691 v8i16, v8i16, OpNode, Commutable>;
692 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
693 v4i32, v4i32, OpNode, Commutable>;
696 // ....then also with element size 64 bits:
697 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
698 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
699 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
700 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
701 v1i64, v1i64, OpNode, Commutable>;
702 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
703 v2i64, v2i64, OpNode, Commutable>;
707 // Neon Narrowing 2-register vector intrinsics,
708 // source operand element sizes of 16, 32 and 64 bits:
709 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
710 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
712 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
713 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
714 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
715 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
716 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
717 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
721 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
722 // source operand element sizes of 16, 32 and 64 bits:
723 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
724 bit op4, string OpcodeStr, Intrinsic IntOp> {
725 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
726 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
727 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
728 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
729 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
730 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
734 // Neon 3-register vector intrinsics.
736 // First with only element sizes of 16 and 32 bits:
737 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
738 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
739 // 64-bit vector types.
740 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
741 v4i16, v4i16, IntOp, Commutable>;
742 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
743 v2i32, v2i32, IntOp, Commutable>;
745 // 128-bit vector types.
746 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
747 v8i16, v8i16, IntOp, Commutable>;
748 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
749 v4i32, v4i32, IntOp, Commutable>;
752 // ....then also with element size of 8 bits:
753 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
754 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
755 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
756 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
757 v8i8, v8i8, IntOp, Commutable>;
758 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
759 v16i8, v16i8, IntOp, Commutable>;
762 // ....then also with element size of 64 bits:
763 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
764 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
765 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
766 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
767 v1i64, v1i64, IntOp, Commutable>;
768 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
769 v2i64, v2i64, IntOp, Commutable>;
773 // Neon Narrowing 3-register vector intrinsics,
774 // source operand element sizes of 16, 32 and 64 bits:
775 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
776 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
777 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
778 v8i8, v8i16, IntOp, Commutable>;
779 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
780 v4i16, v4i32, IntOp, Commutable>;
781 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
782 v2i32, v2i64, IntOp, Commutable>;
786 // Neon Long 3-register vector intrinsics.
788 // First with only element sizes of 16 and 32 bits:
789 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
790 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
791 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
792 v4i32, v4i16, IntOp, Commutable>;
793 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
794 v2i64, v2i32, IntOp, Commutable>;
797 // ....then also with element size of 8 bits:
798 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
799 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
800 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
801 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
802 v8i16, v8i8, IntOp, Commutable>;
806 // Neon Wide 3-register vector intrinsics,
807 // source operand element sizes of 8, 16 and 32 bits:
808 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
809 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
810 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
811 v8i16, v8i8, IntOp, Commutable>;
812 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
813 v4i32, v4i16, IntOp, Commutable>;
814 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
815 v2i64, v2i32, IntOp, Commutable>;
819 // Neon Multiply-Op vector operations,
820 // element sizes of 8, 16 and 32 bits:
821 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
822 string OpcodeStr, SDNode OpNode> {
823 // 64-bit vector types.
824 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
825 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
826 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
827 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
828 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
829 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
831 // 128-bit vector types.
832 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
833 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
834 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
835 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
836 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
837 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
841 // Neon 3-argument intrinsics,
842 // element sizes of 8, 16 and 32 bits:
843 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
844 string OpcodeStr, Intrinsic IntOp> {
845 // 64-bit vector types.
846 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
847 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
848 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
849 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
850 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
851 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
853 // 128-bit vector types.
854 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
855 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
856 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
857 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
858 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
859 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
863 // Neon Long 3-argument intrinsics.
865 // First with only element sizes of 16 and 32 bits:
866 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
867 string OpcodeStr, Intrinsic IntOp> {
868 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
869 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
870 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
871 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
874 // ....then also with element size of 8 bits:
875 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
876 string OpcodeStr, Intrinsic IntOp>
877 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
878 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
879 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
883 // Neon 2-register vector intrinsics,
884 // element sizes of 8, 16 and 32 bits:
885 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
886 bits<5> op11_7, bit op4, string OpcodeStr,
888 // 64-bit vector types.
889 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
890 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
891 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
892 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
893 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
894 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
896 // 128-bit vector types.
897 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
898 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
899 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
900 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
901 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
902 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
906 // Neon Pairwise long 2-register intrinsics,
907 // element sizes of 8, 16 and 32 bits:
908 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
909 bits<5> op11_7, bit op4,
910 string OpcodeStr, Intrinsic IntOp> {
911 // 64-bit vector types.
912 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
913 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
914 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
915 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
916 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
917 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
919 // 128-bit vector types.
920 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
921 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
922 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
923 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
924 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
925 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
929 // Neon Pairwise long 2-register accumulate intrinsics,
930 // element sizes of 8, 16 and 32 bits:
931 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
932 bits<5> op11_7, bit op4,
933 string OpcodeStr, Intrinsic IntOp> {
934 // 64-bit vector types.
935 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
936 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
937 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
938 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
939 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
940 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
942 // 128-bit vector types.
943 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
944 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
945 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
946 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
947 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
948 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
952 // Neon 2-register vector shift by immediate,
953 // element sizes of 8, 16, 32 and 64 bits:
954 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
955 string OpcodeStr, SDNode OpNode> {
956 // 64-bit vector types.
957 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
958 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
959 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
960 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
961 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
962 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
963 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
964 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
966 // 128-bit vector types.
967 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
968 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
969 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
970 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
971 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
972 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
973 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
974 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
978 // Neon Shift-Accumulate vector operations,
979 // element sizes of 8, 16, 32 and 64 bits:
980 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
981 string OpcodeStr, SDNode ShOp> {
982 // 64-bit vector types.
983 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
984 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
985 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
986 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
987 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
988 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
989 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
990 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
992 // 128-bit vector types.
993 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
994 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
995 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
996 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
997 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
998 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
999 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1000 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1004 // Neon Shift-Insert vector operations,
1005 // element sizes of 8, 16, 32 and 64 bits:
1006 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1007 string OpcodeStr, SDNode ShOp> {
1008 // 64-bit vector types.
1009 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
1010 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1011 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
1012 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1013 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
1014 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1015 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
1016 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1018 // 128-bit vector types.
1019 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
1020 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1021 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
1022 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1023 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
1024 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1025 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
1026 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1029 //===----------------------------------------------------------------------===//
1030 // Instruction Definitions.
1031 //===----------------------------------------------------------------------===//
1033 // Vector Add Operations.
1035 // VADD : Vector Add (integer and floating-point)
1036 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
1037 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
1038 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
1039 // VADDL : Vector Add Long (Q = D + D)
1040 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
1041 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
1042 // VADDW : Vector Add Wide (Q = Q + D)
1043 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1044 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1045 // VHADD : Vector Halving Add
1046 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
1047 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
1048 // VRHADD : Vector Rounding Halving Add
1049 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1050 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1051 // VQADD : Vector Saturating Add
1052 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
1053 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
1054 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1055 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1056 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1057 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1059 // Vector Multiply Operations.
1061 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1062 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
1063 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
1064 int_arm_neon_vmulp, 1>;
1065 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
1066 int_arm_neon_vmulp, 1>;
1067 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
1068 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
1069 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1070 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1071 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1072 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1073 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1074 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
1075 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
1076 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
1077 int_arm_neon_vmullp, 1>;
1078 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1079 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1081 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1083 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1084 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
1085 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
1086 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
1087 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1088 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1089 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1090 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1091 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1092 // VMLS : Vector Multiply Subtract (integer and floating-point)
1093 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
1094 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
1095 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
1096 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1097 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1098 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1099 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1100 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1102 // Vector Subtract Operations.
1104 // VSUB : Vector Subtract (integer and floating-point)
1105 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
1106 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
1107 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
1108 // VSUBL : Vector Subtract Long (Q = D - D)
1109 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
1110 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
1111 // VSUBW : Vector Subtract Wide (Q = Q - D)
1112 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1113 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1114 // VHSUB : Vector Halving Subtract
1115 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
1116 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
1117 // VQSUB : Vector Saturing Subtract
1118 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
1119 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
1120 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1121 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1122 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1123 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1125 // Vector Comparisons.
1127 // VCEQ : Vector Compare Equal
1128 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
1129 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1130 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1131 // VCGE : Vector Compare Greater Than or Equal
1132 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
1133 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
1134 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1135 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1136 // VCGT : Vector Compare Greater Than
1137 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1138 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1139 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1140 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1141 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1142 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1143 int_arm_neon_vacged, 0>;
1144 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1145 int_arm_neon_vacgeq, 0>;
1146 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1147 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1148 int_arm_neon_vacgtd, 0>;
1149 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1150 int_arm_neon_vacgtq, 0>;
1151 // VTST : Vector Test Bits
1152 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1154 // Vector Bitwise Operations.
1156 // VAND : Vector Bitwise AND
1157 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1158 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1160 // VEOR : Vector Bitwise Exclusive OR
1161 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1162 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1164 // VORR : Vector Bitwise OR
1165 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1166 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1168 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1169 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1170 (ins DPR:$src1, DPR:$src2), NoItinerary,
1171 "vbic\t$dst, $src1, $src2", "",
1172 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1173 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1174 (ins QPR:$src1, QPR:$src2), NoItinerary,
1175 "vbic\t$dst, $src1, $src2", "",
1176 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1178 // VORN : Vector Bitwise OR NOT
1179 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1180 (ins DPR:$src1, DPR:$src2), NoItinerary,
1181 "vorn\t$dst, $src1, $src2", "",
1182 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1183 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1184 (ins QPR:$src1, QPR:$src2), NoItinerary,
1185 "vorn\t$dst, $src1, $src2", "",
1186 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1188 // VMVN : Vector Bitwise NOT
1189 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1190 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1191 "vmvn\t$dst, $src", "",
1192 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1193 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1194 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1195 "vmvn\t$dst, $src", "",
1196 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1197 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1198 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1200 // VBSL : Vector Bitwise Select
1201 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1202 (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
1203 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1205 (v2i32 (or (and DPR:$src2, DPR:$src1),
1206 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1207 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1208 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
1209 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1211 (v4i32 (or (and QPR:$src2, QPR:$src1),
1212 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1214 // VBIF : Vector Bitwise Insert if False
1215 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1216 // VBIT : Vector Bitwise Insert if True
1217 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1218 // These are not yet implemented. The TwoAddress pass will not go looking
1219 // for equivalent operations with different register constraints; it just
1222 // Vector Absolute Differences.
1224 // VABD : Vector Absolute Difference
1225 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1226 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1227 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1228 int_arm_neon_vabds, 0>;
1229 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1230 int_arm_neon_vabds, 0>;
1232 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1233 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1234 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1236 // VABA : Vector Absolute Difference and Accumulate
1237 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1238 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1240 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1241 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1242 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1244 // Vector Maximum and Minimum.
1246 // VMAX : Vector Maximum
1247 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1248 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1249 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1250 int_arm_neon_vmaxs, 1>;
1251 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1252 int_arm_neon_vmaxs, 1>;
1254 // VMIN : Vector Minimum
1255 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1256 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1257 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1258 int_arm_neon_vmins, 1>;
1259 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1260 int_arm_neon_vmins, 1>;
1262 // Vector Pairwise Operations.
1264 // VPADD : Vector Pairwise Add
1265 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1266 int_arm_neon_vpadd, 0>;
1267 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1268 int_arm_neon_vpadd, 0>;
1269 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1270 int_arm_neon_vpadd, 0>;
1271 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1272 int_arm_neon_vpadd, 0>;
1274 // VPADDL : Vector Pairwise Add Long
1275 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1276 int_arm_neon_vpaddls>;
1277 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1278 int_arm_neon_vpaddlu>;
1280 // VPADAL : Vector Pairwise Add and Accumulate Long
1281 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1282 int_arm_neon_vpadals>;
1283 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1284 int_arm_neon_vpadalu>;
1286 // VPMAX : Vector Pairwise Maximum
1287 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1288 int_arm_neon_vpmaxs, 0>;
1289 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1290 int_arm_neon_vpmaxs, 0>;
1291 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1292 int_arm_neon_vpmaxs, 0>;
1293 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1294 int_arm_neon_vpmaxu, 0>;
1295 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1296 int_arm_neon_vpmaxu, 0>;
1297 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1298 int_arm_neon_vpmaxu, 0>;
1299 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1300 int_arm_neon_vpmaxs, 0>;
1302 // VPMIN : Vector Pairwise Minimum
1303 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1304 int_arm_neon_vpmins, 0>;
1305 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1306 int_arm_neon_vpmins, 0>;
1307 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1308 int_arm_neon_vpmins, 0>;
1309 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1310 int_arm_neon_vpminu, 0>;
1311 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1312 int_arm_neon_vpminu, 0>;
1313 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1314 int_arm_neon_vpminu, 0>;
1315 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1316 int_arm_neon_vpmins, 0>;
1318 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1320 // VRECPE : Vector Reciprocal Estimate
1321 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1322 v2i32, v2i32, int_arm_neon_vrecpe>;
1323 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1324 v4i32, v4i32, int_arm_neon_vrecpe>;
1325 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1326 v2f32, v2f32, int_arm_neon_vrecpe>;
1327 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1328 v4f32, v4f32, int_arm_neon_vrecpe>;
1330 // VRECPS : Vector Reciprocal Step
1331 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1332 int_arm_neon_vrecps, 1>;
1333 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1334 int_arm_neon_vrecps, 1>;
1336 // VRSQRTE : Vector Reciprocal Square Root Estimate
1337 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1338 v2i32, v2i32, int_arm_neon_vrsqrte>;
1339 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1340 v4i32, v4i32, int_arm_neon_vrsqrte>;
1341 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1342 v2f32, v2f32, int_arm_neon_vrsqrte>;
1343 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1344 v4f32, v4f32, int_arm_neon_vrsqrte>;
1346 // VRSQRTS : Vector Reciprocal Square Root Step
1347 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1348 int_arm_neon_vrsqrts, 1>;
1349 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1350 int_arm_neon_vrsqrts, 1>;
1354 // VSHL : Vector Shift
1355 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1356 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1357 // VSHL : Vector Shift Left (Immediate)
1358 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1359 // VSHR : Vector Shift Right (Immediate)
1360 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1361 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1363 // VSHLL : Vector Shift Left Long
1364 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1365 v8i16, v8i8, NEONvshlls>;
1366 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1367 v4i32, v4i16, NEONvshlls>;
1368 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1369 v2i64, v2i32, NEONvshlls>;
1370 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1371 v8i16, v8i8, NEONvshllu>;
1372 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1373 v4i32, v4i16, NEONvshllu>;
1374 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1375 v2i64, v2i32, NEONvshllu>;
1377 // VSHLL : Vector Shift Left Long (with maximum shift count)
1378 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1379 v8i16, v8i8, NEONvshlli>;
1380 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1381 v4i32, v4i16, NEONvshlli>;
1382 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1383 v2i64, v2i32, NEONvshlli>;
1385 // VSHRN : Vector Shift Right and Narrow
1386 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1387 v8i8, v8i16, NEONvshrn>;
1388 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1389 v4i16, v4i32, NEONvshrn>;
1390 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1391 v2i32, v2i64, NEONvshrn>;
1393 // VRSHL : Vector Rounding Shift
1394 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1395 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1396 // VRSHR : Vector Rounding Shift Right
1397 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1398 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1400 // VRSHRN : Vector Rounding Shift Right and Narrow
1401 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1402 v8i8, v8i16, NEONvrshrn>;
1403 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1404 v4i16, v4i32, NEONvrshrn>;
1405 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1406 v2i32, v2i64, NEONvrshrn>;
1408 // VQSHL : Vector Saturating Shift
1409 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1410 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1411 // VQSHL : Vector Saturating Shift Left (Immediate)
1412 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1413 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1414 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1415 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1417 // VQSHRN : Vector Saturating Shift Right and Narrow
1418 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1419 v8i8, v8i16, NEONvqshrns>;
1420 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1421 v4i16, v4i32, NEONvqshrns>;
1422 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1423 v2i32, v2i64, NEONvqshrns>;
1424 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1425 v8i8, v8i16, NEONvqshrnu>;
1426 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1427 v4i16, v4i32, NEONvqshrnu>;
1428 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1429 v2i32, v2i64, NEONvqshrnu>;
1431 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1432 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1433 v8i8, v8i16, NEONvqshrnsu>;
1434 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1435 v4i16, v4i32, NEONvqshrnsu>;
1436 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1437 v2i32, v2i64, NEONvqshrnsu>;
1439 // VQRSHL : Vector Saturating Rounding Shift
1440 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1441 int_arm_neon_vqrshifts, 0>;
1442 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1443 int_arm_neon_vqrshiftu, 0>;
1445 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1446 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1447 v8i8, v8i16, NEONvqrshrns>;
1448 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1449 v4i16, v4i32, NEONvqrshrns>;
1450 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1451 v2i32, v2i64, NEONvqrshrns>;
1452 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1453 v8i8, v8i16, NEONvqrshrnu>;
1454 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1455 v4i16, v4i32, NEONvqrshrnu>;
1456 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1457 v2i32, v2i64, NEONvqrshrnu>;
1459 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1460 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1461 v8i8, v8i16, NEONvqrshrnsu>;
1462 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1463 v4i16, v4i32, NEONvqrshrnsu>;
1464 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1465 v2i32, v2i64, NEONvqrshrnsu>;
1467 // VSRA : Vector Shift Right and Accumulate
1468 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1469 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1470 // VRSRA : Vector Rounding Shift Right and Accumulate
1471 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1472 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1474 // VSLI : Vector Shift Left and Insert
1475 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1476 // VSRI : Vector Shift Right and Insert
1477 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1479 // Vector Absolute and Saturating Absolute.
1481 // VABS : Vector Absolute Value
1482 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1484 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1485 v2f32, v2f32, int_arm_neon_vabs>;
1486 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1487 v4f32, v4f32, int_arm_neon_vabs>;
1489 // VQABS : Vector Saturating Absolute Value
1490 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1491 int_arm_neon_vqabs>;
1495 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1496 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1498 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1499 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1501 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1502 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1503 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1504 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1506 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1507 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1509 // VNEG : Vector Negate
1510 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1511 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1512 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1513 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1514 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1515 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1517 // VNEG : Vector Negate (floating-point)
1518 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1519 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1520 "vneg.f32\t$dst, $src", "",
1521 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1522 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1523 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1524 "vneg.f32\t$dst, $src", "",
1525 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1527 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1528 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1529 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1530 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1531 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1532 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1534 // VQNEG : Vector Saturating Negate
1535 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1536 int_arm_neon_vqneg>;
1538 // Vector Bit Counting Operations.
1540 // VCLS : Vector Count Leading Sign Bits
1541 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1543 // VCLZ : Vector Count Leading Zeros
1544 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1546 // VCNT : Vector Count One Bits
1547 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1548 v8i8, v8i8, int_arm_neon_vcnt>;
1549 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1550 v16i8, v16i8, int_arm_neon_vcnt>;
1552 // Vector Move Operations.
1554 // VMOV : Vector Move (Register)
1556 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1557 NoItinerary, "vmov\t$dst, $src", "", []>;
1558 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1559 NoItinerary, "vmov\t$dst, $src", "", []>;
1561 // VMOV : Vector Move (Immediate)
1563 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1564 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1565 return ARM::getVMOVImm(N, 1, *CurDAG);
1567 def vmovImm8 : PatLeaf<(build_vector), [{
1568 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1571 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1572 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1573 return ARM::getVMOVImm(N, 2, *CurDAG);
1575 def vmovImm16 : PatLeaf<(build_vector), [{
1576 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1577 }], VMOV_get_imm16>;
1579 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1580 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1581 return ARM::getVMOVImm(N, 4, *CurDAG);
1583 def vmovImm32 : PatLeaf<(build_vector), [{
1584 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1585 }], VMOV_get_imm32>;
1587 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1588 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1589 return ARM::getVMOVImm(N, 8, *CurDAG);
1591 def vmovImm64 : PatLeaf<(build_vector), [{
1592 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1593 }], VMOV_get_imm64>;
1595 // Note: Some of the cmode bits in the following VMOV instructions need to
1596 // be encoded based on the immed values.
1598 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1599 (ins i8imm:$SIMM), NoItinerary,
1600 "vmov.i8\t$dst, $SIMM", "",
1601 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1602 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1603 (ins i8imm:$SIMM), NoItinerary,
1604 "vmov.i8\t$dst, $SIMM", "",
1605 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1607 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1608 (ins i16imm:$SIMM), NoItinerary,
1609 "vmov.i16\t$dst, $SIMM", "",
1610 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1611 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1612 (ins i16imm:$SIMM), NoItinerary,
1613 "vmov.i16\t$dst, $SIMM", "",
1614 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1616 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1617 (ins i32imm:$SIMM), NoItinerary,
1618 "vmov.i32\t$dst, $SIMM", "",
1619 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1620 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1621 (ins i32imm:$SIMM), NoItinerary,
1622 "vmov.i32\t$dst, $SIMM", "",
1623 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1625 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1626 (ins i64imm:$SIMM), NoItinerary,
1627 "vmov.i64\t$dst, $SIMM", "",
1628 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1629 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1630 (ins i64imm:$SIMM), NoItinerary,
1631 "vmov.i64\t$dst, $SIMM", "",
1632 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1634 // VMOV : Vector Get Lane (move scalar to ARM core register)
1636 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1637 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1638 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
1639 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1641 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1642 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1643 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
1644 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1646 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1647 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1648 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
1649 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1651 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1652 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1653 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
1654 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1656 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1657 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1658 NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
1659 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1661 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1662 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1663 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1664 (DSubReg_i8_reg imm:$lane))),
1665 (SubReg_i8_lane imm:$lane))>;
1666 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1667 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1668 (DSubReg_i16_reg imm:$lane))),
1669 (SubReg_i16_lane imm:$lane))>;
1670 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1671 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1672 (DSubReg_i8_reg imm:$lane))),
1673 (SubReg_i8_lane imm:$lane))>;
1674 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1675 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1676 (DSubReg_i16_reg imm:$lane))),
1677 (SubReg_i16_lane imm:$lane))>;
1678 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1679 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1680 (DSubReg_i32_reg imm:$lane))),
1681 (SubReg_i32_lane imm:$lane))>;
1682 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
1683 (EXTRACT_SUBREG QPR:$src1, (SSubReg_f32_reg imm:$src2))>;
1684 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1685 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1686 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1687 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1690 // VMOV : Vector Set Lane (move ARM core register to scalar)
1692 let Constraints = "$src1 = $dst" in {
1693 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1694 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1695 NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
1696 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1697 GPR:$src2, imm:$lane))]>;
1698 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1699 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1700 NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
1701 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1702 GPR:$src2, imm:$lane))]>;
1703 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1704 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1705 NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
1706 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1707 GPR:$src2, imm:$lane))]>;
1709 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1710 (v16i8 (INSERT_SUBREG QPR:$src1,
1711 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1712 (DSubReg_i8_reg imm:$lane))),
1713 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1714 (DSubReg_i8_reg imm:$lane)))>;
1715 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1716 (v8i16 (INSERT_SUBREG QPR:$src1,
1717 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1718 (DSubReg_i16_reg imm:$lane))),
1719 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1720 (DSubReg_i16_reg imm:$lane)))>;
1721 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1722 (v4i32 (INSERT_SUBREG QPR:$src1,
1723 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1724 (DSubReg_i32_reg imm:$lane))),
1725 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1726 (DSubReg_i32_reg imm:$lane)))>;
1728 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
1729 (INSERT_SUBREG QPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
1731 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1732 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1733 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1734 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1736 // VDUP : Vector Duplicate (from ARM core register to all elements)
1738 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1739 (vector_shuffle node:$lhs, node:$rhs), [{
1740 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1741 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1744 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1745 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1746 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1747 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1748 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1749 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1750 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1751 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1753 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1754 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1755 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1756 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1757 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1758 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1760 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1761 NoItinerary, "vdup", ".32\t$dst, $src",
1762 [(set DPR:$dst, (v2f32 (splat_lo
1764 (f32 (bitconvert GPR:$src))),
1766 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1767 NoItinerary, "vdup", ".32\t$dst, $src",
1768 [(set QPR:$dst, (v4f32 (splat_lo
1770 (f32 (bitconvert GPR:$src))),
1773 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1775 def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
1776 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1777 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
1780 def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
1781 (vector_shuffle node:$lhs, node:$rhs), [{
1782 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1783 return SVOp->isSplat();
1784 }], SHUFFLE_get_splat_lane>;
1786 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1787 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1788 (outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1789 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1790 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
1792 // vector_shuffle requires that the source and destination types match, so
1793 // VDUP to a 128-bit result uses a target-specific VDUPLANEQ node.
1794 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1795 ValueType ResTy, ValueType OpTy>
1796 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1797 (outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1798 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1799 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
1801 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1802 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1803 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1804 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1805 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1806 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1807 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1808 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1810 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
1811 (outs DPR:$dst), (ins SPR:$src),
1812 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1813 [(set DPR:$dst, (v2f32 (splat_lo
1814 (scalar_to_vector SPR:$src),
1817 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
1818 (outs QPR:$dst), (ins SPR:$src),
1819 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1820 [(set QPR:$dst, (v4f32 (splat_lo
1821 (scalar_to_vector SPR:$src),
1824 // VMOVN : Vector Narrowing Move
1825 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1826 int_arm_neon_vmovn>;
1827 // VQMOVN : Vector Saturating Narrowing Move
1828 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1829 int_arm_neon_vqmovns>;
1830 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1831 int_arm_neon_vqmovnu>;
1832 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1833 int_arm_neon_vqmovnsu>;
1834 // VMOVL : Vector Lengthening Move
1835 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1836 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1838 // Vector Conversions.
1840 // VCVT : Vector Convert Between Floating-Point and Integers
1841 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1842 v2i32, v2f32, fp_to_sint>;
1843 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1844 v2i32, v2f32, fp_to_uint>;
1845 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1846 v2f32, v2i32, sint_to_fp>;
1847 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1848 v2f32, v2i32, uint_to_fp>;
1850 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1851 v4i32, v4f32, fp_to_sint>;
1852 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1853 v4i32, v4f32, fp_to_uint>;
1854 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1855 v4f32, v4i32, sint_to_fp>;
1856 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1857 v4f32, v4i32, uint_to_fp>;
1859 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1860 // Note: Some of the opcode bits in the following VCVT instructions need to
1861 // be encoded based on the immed values.
1862 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1863 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1864 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1865 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1866 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1867 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1868 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1869 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1871 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1872 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1873 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1874 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1875 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1876 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1877 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1878 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1880 // VREV : Vector Reverse
1882 def vrev64_shuffle : PatFrag<(ops node:$in),
1883 (vector_shuffle node:$in, undef), [{
1884 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1885 return ARM::isVREVMask(SVOp, 64);
1888 def vrev32_shuffle : PatFrag<(ops node:$in),
1889 (vector_shuffle node:$in, undef), [{
1890 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1891 return ARM::isVREVMask(SVOp, 32);
1894 def vrev16_shuffle : PatFrag<(ops node:$in),
1895 (vector_shuffle node:$in, undef), [{
1896 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1897 return ARM::isVREVMask(SVOp, 16);
1900 // VREV64 : Vector Reverse elements within 64-bit doublewords
1902 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1903 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1904 (ins DPR:$src), NoItinerary,
1905 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1906 [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>;
1907 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1908 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1909 (ins QPR:$src), NoItinerary,
1910 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1911 [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>;
1913 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1914 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1915 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1916 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1918 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1919 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1920 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1921 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1923 // VREV32 : Vector Reverse elements within 32-bit words
1925 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1926 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1927 (ins DPR:$src), NoItinerary,
1928 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1929 [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>;
1930 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1931 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1932 (ins QPR:$src), NoItinerary,
1933 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1934 [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>;
1936 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1937 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1939 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1940 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1942 // VREV16 : Vector Reverse elements within 16-bit halfwords
1944 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1945 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1946 (ins DPR:$src), NoItinerary,
1947 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1948 [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>;
1949 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1950 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1951 (ins QPR:$src), NoItinerary,
1952 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1953 [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>;
1955 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1956 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1958 // VTRN : Vector Transpose
1960 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
1961 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
1962 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
1964 def VTRNq8 : N2VQShuffle<0b00, 0b00001, "vtrn.8">;
1965 def VTRNq16 : N2VQShuffle<0b01, 0b00001, "vtrn.16">;
1966 def VTRNq32 : N2VQShuffle<0b10, 0b00001, "vtrn.32">;
1968 // VUZP : Vector Unzip (Deinterleave)
1970 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
1971 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
1972 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
1974 def VUZPq8 : N2VQShuffle<0b00, 0b00010, "vuzp.8">;
1975 def VUZPq16 : N2VQShuffle<0b01, 0b00010, "vuzp.16">;
1976 def VUZPq32 : N2VQShuffle<0b10, 0b00010, "vuzp.32">;
1978 // VZIP : Vector Zip (Interleave)
1980 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
1981 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
1982 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
1984 def VZIPq8 : N2VQShuffle<0b00, 0b00011, "vzip.8">;
1985 def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">;
1986 def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">;
1988 //===----------------------------------------------------------------------===//
1989 // NEON instructions for single-precision FP math
1990 //===----------------------------------------------------------------------===//
1992 // These need separate instructions because they must use DPR_VFP2 register
1993 // class which have SPR sub-registers.
1995 // Vector Add Operations used for single-precision FP
1996 let neverHasSideEffects = 1 in
1997 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
1998 def : N3VDsPat<fadd, VADDfd_sfp>;
2000 // Vector Sub Operations used for single-precision FP
2001 let neverHasSideEffects = 1 in
2002 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2003 def : N3VDsPat<fsub, VSUBfd_sfp>;
2005 // Vector Multiply Operations used for single-precision FP
2006 let neverHasSideEffects = 1 in
2007 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2008 def : N3VDsPat<fmul, VMULfd_sfp>;
2010 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2011 let neverHasSideEffects = 1 in
2012 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>;
2013 def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2015 let neverHasSideEffects = 1 in
2016 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>;
2017 def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2019 // Vector Absolute used for single-precision FP
2020 let neverHasSideEffects = 1 in
2021 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
2022 v2f32, v2f32, int_arm_neon_vabs>;
2023 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2025 // Vector Negate used for single-precision FP
2026 let neverHasSideEffects = 1 in
2027 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2028 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
2029 "vneg.f32\t$dst, $src", "", []>;
2030 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2032 // Vector Convert between single-precision FP and integer
2033 let neverHasSideEffects = 1 in
2034 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2035 v2i32, v2f32, fp_to_sint>;
2036 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2038 let neverHasSideEffects = 1 in
2039 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2040 v2i32, v2f32, fp_to_uint>;
2041 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2043 let neverHasSideEffects = 1 in
2044 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2045 v2f32, v2i32, sint_to_fp>;
2046 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2048 let neverHasSideEffects = 1 in
2049 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2050 v2f32, v2i32, uint_to_fp>;
2051 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2053 //===----------------------------------------------------------------------===//
2054 // Non-Instruction Patterns
2055 //===----------------------------------------------------------------------===//
2058 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2059 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2060 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2061 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2062 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2063 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2064 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2065 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2066 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2067 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2068 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2069 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2070 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2071 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2072 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2073 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2074 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2075 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2076 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2077 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2078 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2079 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2080 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2081 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2082 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2083 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2084 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2085 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2086 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2087 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2089 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2090 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2091 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2092 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2093 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2094 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2095 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2096 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2097 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2098 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2099 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2100 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2101 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2102 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2103 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2104 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2105 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2106 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2107 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2108 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2109 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2110 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2111 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2112 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2113 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2114 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2115 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2116 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2117 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2118 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
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