Merging r258386:
authorTom Stellard <thomas.stellard@amd.com>
Tue, 26 Jan 2016 23:57:01 +0000 (23:57 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Tue, 26 Jan 2016 23:57:01 +0000 (23:57 +0000)
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r258386 | thomas.stellard | 2016-01-20 23:28:34 -0500 (Wed, 20 Jan 2016) | 14 lines

AMDGPU/SI: Pass whether to use the SI scheduler via Target Attribute

Summary:
Currently the SI scheduler can be selected via command line option,
but it turned out it would be better if it was selectable via a Target Attribute.

This patch adds "si-scheduler" attribute to the backend.

Reviewers: tstellarAMD, echristo

Subscribers: echristo, arsenm

Differential Revision: http://reviews.llvm.org/D16192

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@258885 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AMDGPU/AMDGPU.td
lib/Target/AMDGPU/AMDGPUSubtarget.cpp
lib/Target/AMDGPU/AMDGPUSubtarget.h
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

index db869cf7dd8b43173e20f9e30f65871cf70cfa0a..79c6604c4cc85707c8b0c8cb5cd34fab066c2900 100644 (file)
@@ -138,6 +138,11 @@ def FeatureEnableHugeScratchBuffer : SubtargetFeature<"huge-scratch-buffer",
         "true",
         "Enable scratch buffer sizes greater than 128 GB">;
 
+def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
+        "EnableSIScheduler",
+        "true",
+        "Enable SI Machine Scheduler">;
+
 class SubtargetFeatureFetchLimit <string Value> :
                           SubtargetFeature <"fetch"#Value,
         "TexVTXClauseSize",
index c6af5b93d257e381aef6048581fda1ef4b990f14..7d70fa73da29463ae065d771a446561e08ddf97d 100644 (file)
@@ -78,7 +78,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
       EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
       GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
       IsaVersion(ISAVersion0_0_0), EnableHugeScratchBuffer(false),
-      FrameLowering(nullptr),
+      EnableSIScheduler(false), FrameLowering(nullptr),
       InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
 
   initializeSubtargetDependencies(TT, GPU, FS);
index d3712276d5e7337c98b39d88e4203fcd00cc9eef..4796e9ef3454dfe64849736419b5c7e842510bb1 100644 (file)
@@ -90,6 +90,7 @@ private:
   int LDSBankCount;
   unsigned IsaVersion;
   bool EnableHugeScratchBuffer;
+  bool EnableSIScheduler;
 
   std::unique_ptr<AMDGPUFrameLowering> FrameLowering;
   std::unique_ptr<AMDGPUTargetLowering> TLInfo;
@@ -280,6 +281,10 @@ public:
     return EnableHugeScratchBuffer;
   }
 
+  bool enableSIScheduler() const {
+    return EnableSIScheduler;
+  }
+
   bool dumpCode() const {
     return DumpCode;
   }
index b1be6197a6c6a0a01a8b55d876f045a8af5a7fc4..519ae5cc748d077dee39cda37d58e66bcb9f85b1 100644 (file)
@@ -147,6 +147,8 @@ public:
     const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
     if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
       return createR600MachineScheduler(C);
+    else if (ST.enableSIScheduler())
+      return createSIMachineScheduler(C);
     return nullptr;
   }