Merging r258386:
[oota-llvm.git] / lib / Target / AMDGPU / AMDGPU.td
1 //===-- AMDGPU.td - AMDGPU Tablegen files ------------------*- tablegen -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 include "llvm/Target/Target.td"
11
12 //===----------------------------------------------------------------------===//
13 // Subtarget Features
14 //===----------------------------------------------------------------------===//
15
16 // Debugging Features
17
18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
19         "DumpCode",
20         "true",
21         "Dump MachineInstrs in the CodeEmitter">;
22
23 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
24         "DumpCode",
25         "true",
26         "Dump MachineInstrs in the CodeEmitter">;
27
28 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
29         "EnableIRStructurizer",
30         "false",
31         "Disable IR Structurizer">;
32
33 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
34         "EnablePromoteAlloca",
35         "true",
36         "Enable promote alloca pass">;
37
38 // Target features
39
40 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
41         "EnableIfCvt",
42         "false",
43         "Disable the if conversion pass">;
44
45 def FeatureFP64 : SubtargetFeature<"fp64",
46         "FP64",
47         "true",
48         "Enable double precision operations">;
49
50 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
51         "FP64Denormals",
52         "true",
53         "Enable double precision denormal handling",
54         [FeatureFP64]>;
55
56 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
57         "FastFMAF32",
58         "true",
59         "Assuming f32 fma is at least as fast as mul + add",
60         []>;
61
62 // Some instructions do not support denormals despite this flag. Using
63 // fp32 denormals also causes instructions to run at the double
64 // precision rate for the device.
65 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
66         "FP32Denormals",
67         "true",
68         "Enable single precision denormal handling">;
69
70 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
71         "Is64bit",
72         "true",
73         "Specify if 64-bit addressing should be used">;
74
75 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
76         "R600ALUInst",
77         "false",
78         "Older version of ALU instructions encoding">;
79
80 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
81         "HasVertexCache",
82         "true",
83         "Specify use of dedicated vertex cache">;
84
85 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
86         "CaymanISA",
87         "true",
88         "Use Cayman ISA">;
89
90 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
91         "CFALUBug",
92         "true",
93         "GPU has CF_ALU bug">;
94
95 // XXX - This should probably be removed once enabled by default
96 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
97         "EnableLoadStoreOpt",
98         "true",
99         "Enable SI load/store optimizer pass">;
100
101 // Performance debugging feature. Allow using DS instruction immediate
102 // offsets even if the base pointer can't be proven to be base. On SI,
103 // base pointer values that won't give the same result as a 16-bit add
104 // are not safe to fold, but this will override the conservative test
105 // for the base pointer.
106 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <"unsafe-ds-offset-folding",
107         "EnableUnsafeDSOffsetFolding",
108         "true",
109         "Force using DS instruction immediate offsets on SI">;
110
111 def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
112         "FlatForGlobal",
113         "true",
114         "Force to generate flat instruction for global">;
115
116 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
117         "FlatAddressSpace",
118         "true",
119         "Support flat address space">;
120
121 def FeatureXNACK : SubtargetFeature<"xnack",
122         "EnableXNACK",
123         "true",
124         "Enable XNACK support">;
125
126 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
127         "EnableVGPRSpilling",
128         "true",
129         "Enable spilling of VGPRs to scratch memory">;
130
131 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
132         "SGPRInitBug",
133         "true",
134         "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
135
136 def FeatureEnableHugeScratchBuffer : SubtargetFeature<"huge-scratch-buffer",
137         "EnableHugeScratchBuffer",
138         "true",
139         "Enable scratch buffer sizes greater than 128 GB">;
140
141 def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
142         "EnableSIScheduler",
143         "true",
144         "Enable SI Machine Scheduler">;
145
146 class SubtargetFeatureFetchLimit <string Value> :
147                           SubtargetFeature <"fetch"#Value,
148         "TexVTXClauseSize",
149         Value,
150         "Limit the maximum number of fetches in a clause to "#Value>;
151
152 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
153 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
154
155 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
156         "wavefrontsize"#Value,
157         "WavefrontSize",
158         !cast<string>(Value),
159         "The number of threads per wavefront">;
160
161 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
162 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
163 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
164
165 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
166       "ldsbankcount"#Value,
167       "LDSBankCount",
168       !cast<string>(Value),
169       "The number of LDS banks per compute unit.">;
170
171 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
172 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
173
174 class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping>
175                                  : SubtargetFeature <
176       "isaver"#Major#"."#Minor#"."#Stepping,
177       "IsaVersion",
178       "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
179       "Instruction set version number"
180 >;
181
182 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0>;
183 def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1>;
184 def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0>;
185 def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1>;
186
187 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
188         "localmemorysize"#Value,
189         "LocalMemorySize",
190         !cast<string>(Value),
191         "The size of local memory in bytes">;
192
193 def FeatureGCN : SubtargetFeature<"gcn",
194         "IsGCN",
195         "true",
196         "GCN or newer GPU">;
197
198 def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
199         "GCN1Encoding",
200         "true",
201         "Encoding format for SI and CI">;
202
203 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
204         "GCN3Encoding",
205         "true",
206         "Encoding format for VI">;
207
208 def FeatureCIInsts : SubtargetFeature<"ci-insts",
209         "CIInsts",
210         "true",
211         "Additional intstructions for CI+">;
212
213 // Dummy feature used to disable assembler instructions.
214 def FeatureDisable : SubtargetFeature<"",
215                                       "FeatureDisable","true",
216                                       "Dummy feature to disable assembler"
217                                       " instructions">;
218
219 class SubtargetFeatureGeneration <string Value,
220                                   list<SubtargetFeature> Implies> :
221         SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
222                           Value#" GPU generation", Implies>;
223
224 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
225 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
226 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
227
228 def FeatureR600 : SubtargetFeatureGeneration<"R600",
229         [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
230
231 def FeatureR700 : SubtargetFeatureGeneration<"R700",
232         [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
233
234 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
235         [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
236
237 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
238         [FeatureFetchLimit16, FeatureWavefrontSize64,
239          FeatureLocalMemorySize32768]
240 >;
241
242 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
243         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
244          FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
245          FeatureLDSBankCount32]>;
246
247 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
248         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
249          FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
250          FeatureGCN1Encoding, FeatureCIInsts]>;
251
252 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
253         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
254          FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
255          FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>;
256
257 //===----------------------------------------------------------------------===//
258
259 def AMDGPUInstrInfo : InstrInfo {
260   let guessInstructionProperties = 1;
261   let noNamedPositionallyEncodedOperands = 1;
262 }
263
264 def AMDGPUAsmParser : AsmParser {
265   // Some of the R600 registers have the same name, so this crashes.
266   // For example T0_XYZW and T0_XY both have the asm name T0.
267   let ShouldEmitMatchRegisterName = 0;
268 }
269
270 def AMDGPU : Target {
271   // Pull in Instruction Info:
272   let InstructionSet = AMDGPUInstrInfo;
273   let AssemblyParsers = [AMDGPUAsmParser];
274 }
275
276 // Dummy Instruction itineraries for pseudo instructions
277 def ALU_NULL : FuncUnit;
278 def NullALU : InstrItinClass;
279
280 //===----------------------------------------------------------------------===//
281 // Predicate helper class
282 //===----------------------------------------------------------------------===//
283
284 def TruePredicate : Predicate<"true">;
285 def isSICI : Predicate<
286   "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
287   "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
288 >, AssemblerPredicate<"FeatureGCN1Encoding">;
289
290 def isVI : Predicate <
291   "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
292   AssemblerPredicate<"FeatureGCN3Encoding">;
293
294 class PredicateControl {
295   Predicate SubtargetPredicate;
296   Predicate SIAssemblerPredicate = isSICI;
297   Predicate VIAssemblerPredicate = isVI;
298   list<Predicate> AssemblerPredicates = [];
299   Predicate AssemblerPredicate = TruePredicate;
300   list<Predicate> OtherPredicates = [];
301   list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
302                                             AssemblerPredicates,
303                                             OtherPredicates);
304 }
305
306 // Include AMDGPU TD files
307 include "R600Schedule.td"
308 include "SISchedule.td"
309 include "Processors.td"
310 include "AMDGPUInstrInfo.td"
311 include "AMDGPUIntrinsics.td"
312 include "AMDGPURegisterInfo.td"
313 include "AMDGPUInstructions.td"
314 include "AMDGPUCallingConv.td"