ARM isel for vld1, opcode selection for register stride post-index pseudos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143158 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 8a1b618b96380a0188a8481a9b01fc7aa8ffc564..39d4d39c9044bc336d30908fbf324496ef252cb9 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1562,6 +1562,10 @@ static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
   case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
   case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
   case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
+  case ARM::VLD1q8PseudoWB_fixed: return ARM::VLD1q8PseudoWB_register;
+  case ARM::VLD1q16PseudoWB_fixed: return ARM::VLD1q16PseudoWB_register;
+  case ARM::VLD1q32PseudoWB_fixed: return ARM::VLD1q32PseudoWB_register;
+  case ARM::VLD1q64PseudoWB_fixed: return ARM::VLD1q64PseudoWB_register;
   }
   return Opc; // If not one we handle, return it unchanged.
 }