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inline | side by side (from parent 1:
58c99da)
on the subtarget and just forward the accessor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210955
91177308-0d34-0410-b5e6-
96231b3b80d8
CodeGenOpt::Level OL,
bool isLittle)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
CodeGenOpt::Level OL,
bool isLittle)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
- Subtarget(TT, CPU, FS, isLittle, Options),
- InstrItins(Subtarget.getInstrItineraryData()) {
+ Subtarget(TT, CPU, FS, isLittle, Options) {
// Default to triple-appropriate float ABI
if (Options.FloatABIType == FloatABI::Default)
// Default to triple-appropriate float ABI
if (Options.FloatABIType == FloatABI::Default)
class ARMBaseTargetMachine : public LLVMTargetMachine {
protected:
ARMSubtarget Subtarget;
class ARMBaseTargetMachine : public LLVMTargetMachine {
protected:
ARMSubtarget Subtarget;
-private:
- InstrItineraryData InstrItins;
-
public:
ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
public:
ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
llvm_unreachable("getTargetLowering not implemented");
}
const InstrItineraryData *getInstrItineraryData() const override {
llvm_unreachable("getTargetLowering not implemented");
}
const InstrItineraryData *getInstrItineraryData() const override {
+ return &getSubtargetImpl()->getInstrItineraryData();
}
/// \brief Register ARM analysis passes with a pass manager.
}
/// \brief Register ARM analysis passes with a pass manager.