1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "ARMFrameLowering.h"
18 #include "ARMISelLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMJITInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
23 #include "Thumb1FrameLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/Target/TargetMachine.h"
32 class ARMBaseTargetMachine : public LLVMTargetMachine {
34 ARMSubtarget Subtarget;
36 ARMBaseTargetMachine(const Target &T, StringRef TT,
37 StringRef CPU, StringRef FS,
38 const TargetOptions &Options,
39 Reloc::Model RM, CodeModel::Model CM,
43 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
44 const ARMTargetLowering *getTargetLowering() const override {
45 // Implemented by derived classes
46 llvm_unreachable("getTargetLowering not implemented");
48 const InstrItineraryData *getInstrItineraryData() const override {
49 return &getSubtargetImpl()->getInstrItineraryData();
52 /// \brief Register ARM analysis passes with a pass manager.
53 void addAnalysisPasses(PassManagerBase &PM) override;
55 // Pass Pipeline Configuration
56 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
58 bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
61 /// ARMTargetMachine - ARM target machine.
63 class ARMTargetMachine : public ARMBaseTargetMachine {
64 virtual void anchor();
65 ARMInstrInfo InstrInfo;
66 ARMTargetLowering TLInfo;
67 ARMFrameLowering FrameLowering;
69 ARMTargetMachine(const Target &T, StringRef TT,
70 StringRef CPU, StringRef FS,
71 const TargetOptions &Options,
72 Reloc::Model RM, CodeModel::Model CM,
76 const ARMRegisterInfo *getRegisterInfo() const override {
77 return &InstrInfo.getRegisterInfo();
80 const ARMTargetLowering *getTargetLowering() const override {
84 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
85 return getSubtargetImpl()->getSelectionDAGInfo();
87 const ARMFrameLowering *getFrameLowering() const override {
88 return &FrameLowering;
90 const ARMInstrInfo *getInstrInfo() const override { return &InstrInfo; }
91 const DataLayout *getDataLayout() const override {
92 return getSubtargetImpl()->getDataLayout();
96 /// ARMLETargetMachine - ARM little endian target machine.
98 class ARMLETargetMachine : public ARMTargetMachine {
99 void anchor() override;
101 ARMLETargetMachine(const Target &T, StringRef TT,
102 StringRef CPU, StringRef FS, const TargetOptions &Options,
103 Reloc::Model RM, CodeModel::Model CM,
104 CodeGenOpt::Level OL);
107 /// ARMBETargetMachine - ARM big endian target machine.
109 class ARMBETargetMachine : public ARMTargetMachine {
110 void anchor() override;
112 ARMBETargetMachine(const Target &T, StringRef TT,
113 StringRef CPU, StringRef FS, const TargetOptions &Options,
114 Reloc::Model RM, CodeModel::Model CM,
115 CodeGenOpt::Level OL);
118 /// ThumbTargetMachine - Thumb target machine.
119 /// Due to the way architectures are handled, this represents both
120 /// Thumb-1 and Thumb-2.
122 class ThumbTargetMachine : public ARMBaseTargetMachine {
123 virtual void anchor();
124 // Either Thumb1InstrInfo or Thumb2InstrInfo.
125 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
126 ARMTargetLowering TLInfo;
127 // Either Thumb1FrameLowering or ARMFrameLowering.
128 std::unique_ptr<ARMFrameLowering> FrameLowering;
130 ThumbTargetMachine(const Target &T, StringRef TT,
131 StringRef CPU, StringRef FS,
132 const TargetOptions &Options,
133 Reloc::Model RM, CodeModel::Model CM,
134 CodeGenOpt::Level OL,
137 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
138 const ARMBaseRegisterInfo *getRegisterInfo() const override {
139 return &InstrInfo->getRegisterInfo();
142 const ARMTargetLowering *getTargetLowering() const override {
146 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
147 return getSubtargetImpl()->getSelectionDAGInfo();
150 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
151 const ARMBaseInstrInfo *getInstrInfo() const override {
152 return InstrInfo.get();
154 /// returns either Thumb1FrameLowering or ARMFrameLowering
155 const ARMFrameLowering *getFrameLowering() const override {
156 return FrameLowering.get();
158 const DataLayout *getDataLayout() const override {
159 return getSubtargetImpl()->getDataLayout();
163 /// ThumbLETargetMachine - Thumb little endian target machine.
165 class ThumbLETargetMachine : public ThumbTargetMachine {
166 void anchor() override;
168 ThumbLETargetMachine(const Target &T, StringRef TT,
169 StringRef CPU, StringRef FS, const TargetOptions &Options,
170 Reloc::Model RM, CodeModel::Model CM,
171 CodeGenOpt::Level OL);
174 /// ThumbBETargetMachine - Thumb big endian target machine.
176 class ThumbBETargetMachine : public ThumbTargetMachine {
177 void anchor() override;
179 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
180 StringRef FS, const TargetOptions &Options,
181 Reloc::Model RM, CodeModel::Model CM,
182 CodeGenOpt::Level OL);
185 } // end namespace llvm