Tidy some more comments and whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99081 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 0ac5ec7bb653a6a91c76cd953d89e675c98f9c9e..d5898396191c80cb47aabacd729915adcddd339b 100644 (file)
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -384,64 +384,61 @@ def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">;
 
 //   VLD2LN   : Vector Load (single 2-element structure to one lane)
 class VLD2LN<bits<4> op11_8, string Dt>
-  : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
-            (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
-            IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
-            "$src1 = $dst1, $src2 = $dst2", []>;
+  : NLdSt<1, 0b10, op11_8, {?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
+          (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
+          IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
+          "$src1 = $dst1, $src2 = $dst2", []>;
 
-// vld2 to single-spaced registers.
 def VLD2LNd8  : VLD2LN<0b0001, "8">;
 def VLD2LNd16 : VLD2LN<0b0101, "16"> { let Inst{5} = 0; }
 def VLD2LNd32 : VLD2LN<0b1001, "32"> { let Inst{6} = 0; }
 
-// vld2 to double-spaced even registers.
+// ...with double-spaced registers:
 def VLD2LNq16 : VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
 def VLD2LNq32 : VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
 
-// vld2 to double-spaced odd registers.
+// ...alternate versions to be allocated odd register numbers:
 def VLD2LNq16odd : VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
 def VLD2LNq32odd : VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
 
 //   VLD3LN   : Vector Load (single 3-element structure to one lane)
 class VLD3LN<bits<4> op11_8, string Dt>
-  : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
-            (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
-            nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
-            "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
-            "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
+  : NLdSt<1, 0b10, op11_8, {?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
+          (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
+          nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
+          "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
+          "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
 
-// vld3 to single-spaced registers.
 def VLD3LNd8  : VLD3LN<0b0010, "8"> { let Inst{4} = 0; }
 def VLD3LNd16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
 def VLD3LNd32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
 
-// vld3 to double-spaced even registers.
+// ...with double-spaced registers:
 def VLD3LNq16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
 def VLD3LNq32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
 
-// vld3 to double-spaced odd registers.
+// ...alternate versions to be allocated odd register numbers:
 def VLD3LNq16odd : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
 def VLD3LNq32odd : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
 
 //   VLD4LN   : Vector Load (single 4-element structure to one lane)
 class VLD4LN<bits<4> op11_8, string Dt>
-  : NLdSt<1,0b10,op11_8,{?,?,?,?},
-            (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
-            (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
-            nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
+  : NLdSt<1, 0b10, op11_8, {?,?,?,?},
+          (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
+          (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
+          nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
           "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
-            "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
+          "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
 
-// vld4 to single-spaced registers.
 def VLD4LNd8  : VLD4LN<0b0011, "8">;
 def VLD4LNd16 : VLD4LN<0b0111, "16"> { let Inst{5} = 0; }
 def VLD4LNd32 : VLD4LN<0b1011, "32"> { let Inst{6} = 0; }
 
-// vld4 to double-spaced even registers.
+// ...with double-spaced registers:
 def VLD4LNq16 : VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
 def VLD4LNq32 : VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
 
-// vld4 to double-spaced odd registers.
+// ...alternate versions to be allocated odd register numbers:
 def VLD4LNq16odd : VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
 def VLD4LNq32odd : VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
 
@@ -597,62 +594,59 @@ def VST4q32odd_UPD : VST4WB<0b1000, "32">;
 
 //   VST2LN   : Vector Store (single 2-element structure from one lane)
 class VST2LN<bits<4> op11_8, string Dt>
-  : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
+  : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
           (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
           IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
           "", []>;
 
-// vst2 to single-spaced registers.
 def VST2LNd8  : VST2LN<0b0001, "8">;
 def VST2LNd16 : VST2LN<0b0101, "16"> { let Inst{5} = 0; }
 def VST2LNd32 : VST2LN<0b1001, "32"> { let Inst{6} = 0; }
 
-// vst2 to double-spaced even registers.
+// ...with double-spaced registers:
 def VST2LNq16 : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
 def VST2LNq32 : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
 
-// vst2 to double-spaced odd registers.
+// ...alternate versions to be allocated odd register numbers:
 def VST2LNq16odd : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
 def VST2LNq32odd : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
 
 //   VST3LN   : Vector Store (single 3-element structure from one lane)
 class VST3LN<bits<4> op11_8, string Dt>
-  : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
+  : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
           (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
            nohash_imm:$lane), IIC_VST, "vst3", Dt,
           "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
 
-// vst3 to single-spaced registers.
 def VST3LNd8  : VST3LN<0b0010, "8"> { let Inst{4} = 0; }
 def VST3LNd16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
 def VST3LNd32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
 
-// vst3 to double-spaced even registers.
+// ...with double-spaced registers:
 def VST3LNq16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
 def VST3LNq32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
 
-// vst3 to double-spaced odd registers.
+// ...alternate versions to be allocated odd register numbers:
 def VST3LNq16odd : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
 def VST3LNq32odd : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
 
 //   VST4LN   : Vector Store (single 4-element structure from one lane)
 class VST4LN<bits<4> op11_8, string Dt>
-  : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
+  : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
           (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
            nohash_imm:$lane), IIC_VST, "vst4", Dt,
           "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
           "", []>;
 
-// vst4 to single-spaced registers.
 def VST4LNd8  : VST4LN<0b0011, "8">;
 def VST4LNd16 : VST4LN<0b0111, "16"> { let Inst{5} = 0; }
 def VST4LNd32 : VST4LN<0b1011, "32"> { let Inst{6} = 0; }
 
-// vst4 to double-spaced even registers.
+// ...with double-spaced registers:
 def VST4LNq16 : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
 def VST4LNq32 : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
 
-// vst4 to double-spaced odd registers.
+// ...alternate versions to be allocated odd register numbers:
 def VST4LNq16odd : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
 def VST4LNq32odd : VST4LN<0b1011, "32"> { let Inst{6} = 1; }