Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_s...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48578 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index f33946cdcc650dfcf237878f7cc88b355946a2e6..f6318495e0ffdb8c68ddd4f31e7346e71ae0bce6 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2400,7 +2400,9 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
 
       // If the shift wouldn't be a noop, the truncated type is an actual type,
       // and the truncate is free, then proceed with the transform.
-      if (ShiftAmt != 0 && TLI.isTruncateFree(VT, TruncVT)) {
+      if (ShiftAmt != 0 &&
+          TLI.isTypeLegal(TruncVT) &&
+          TLI.isTruncateFree(VT, TruncVT)) {
         SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy());
         SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt);
         SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift);

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 93fb802241cc4f3f2145516e2d02fb6d253ae278..5a05abac898e1fca0dd3b5e24908aad66225402b 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5662,7 +5662,7 @@ bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
     return false;
   unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
   unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
-  if (NumBits1 <= NumBits2 || NumBits2 < 8)
+  if (NumBits1 <= NumBits2)
     return false;
   return Subtarget->is64Bit() || NumBits1 < 64;
 }
@@ -5673,7 +5673,7 @@ bool X86TargetLowering::isTruncateFree(MVT::ValueType VT1,
     return false;
   unsigned NumBits1 = MVT::getSizeInBits(VT1);
   unsigned NumBits2 = MVT::getSizeInBits(VT2);
-  if (NumBits1 <= NumBits2 || NumBits2 < 8)
+  if (NumBits1 <= NumBits2)
     return false;
   return Subtarget->is64Bit() || NumBits1 < 64;
 }

diff --git a/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll b/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll
new file mode 100644 (file)
index 0000000..2fad32a
--- /dev/null
+++ b/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llc -march=x86
+
+define i32 @t() nounwind  {
+entry:
+       %tmp54 = add i32 0, 1           ; <i32> [#uses=1]
+       br i1 false, label %bb71, label %bb77
+bb71:          ; preds = %entry
+       %tmp74 = shl i32 %tmp54, 1              ; <i32> [#uses=1]
+       %tmp76 = ashr i32 %tmp74, 3             ; <i32> [#uses=1]
+       br label %bb77
+bb77:          ; preds = %bb71, %entry
+       %payLoadSize.0 = phi i32 [ %tmp76, %bb71 ], [ 0, %entry ]               ; <i32> [#uses=0]
+       unreachable
+}