From 260e07ec8ceb98337a9eeb5377d97dfcc0058a25 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 20 Mar 2008 02:18:41 +0000 Subject: [PATCH] Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_size - n - m))) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48578 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 +++- lib/Target/X86/X86ISelLowering.cpp | 4 ++-- test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll | 14 ++++++++++++++ 3 files changed, 19 insertions(+), 3 deletions(-) create mode 100644 test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index f33946cdcc6..f6318495e0f 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2400,7 +2400,9 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) { // If the shift wouldn't be a noop, the truncated type is an actual type, // and the truncate is free, then proceed with the transform. - if (ShiftAmt != 0 && TLI.isTruncateFree(VT, TruncVT)) { + if (ShiftAmt != 0 && + TLI.isTypeLegal(TruncVT) && + TLI.isTruncateFree(VT, TruncVT)) { SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 93fb802241c..5a05abac898 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -5662,7 +5662,7 @@ bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { return false; unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); - if (NumBits1 <= NumBits2 || NumBits2 < 8) + if (NumBits1 <= NumBits2) return false; return Subtarget->is64Bit() || NumBits1 < 64; } @@ -5673,7 +5673,7 @@ bool X86TargetLowering::isTruncateFree(MVT::ValueType VT1, return false; unsigned NumBits1 = MVT::getSizeInBits(VT1); unsigned NumBits2 = MVT::getSizeInBits(VT2); - if (NumBits1 <= NumBits2 || NumBits2 < 8) + if (NumBits1 <= NumBits2) return false; return Subtarget->is64Bit() || NumBits1 < 64; } diff --git a/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll b/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll new file mode 100644 index 00000000000..2fad32a36c3 --- /dev/null +++ b/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=x86 + +define i32 @t() nounwind { +entry: + %tmp54 = add i32 0, 1 ; [#uses=1] + br i1 false, label %bb71, label %bb77 +bb71: ; preds = %entry + %tmp74 = shl i32 %tmp54, 1 ; [#uses=1] + %tmp76 = ashr i32 %tmp74, 3 ; [#uses=1] + br label %bb77 +bb77: ; preds = %bb71, %entry + %payLoadSize.0 = phi i32 [ %tmp76, %bb71 ], [ 0, %entry ] ; [#uses=0] + unreachable +} -- 2.34.1