[DebugInfo] Add debug locations to constant SD nodes
authorSergey Dmitrouk <sdmitrouk@accesssoftek.com>
Tue, 28 Apr 2015 11:56:37 +0000 (11:56 +0000)
committerSergey Dmitrouk <sdmitrouk@accesssoftek.com>
Tue, 28 Apr 2015 11:56:37 +0000 (11:56 +0000)
commit716c5d8a308a2257298f1f227edf7f7ae102cf4f
treeac855e7824b48464ed01d5739ded98d00aacee40
parent44a0c9071a7f4b190d828bdac797af3fd4eff011
[DebugInfo] Add debug locations to constant SD nodes

This adds debug location to constant nodes of Selection DAG and updates
all places that create constants to pass debug locations
(see PR13269).

Can't guarantee that all locations are correct, but in a lot of cases choice
is obvious, so most of them should be. At least all tests pass.

Tests for these changes do not cover everything, instead just check it for
SDNodes, ARM and AArch64 where it's easy to get incorrect locations on
constants.

This is not complete fix as FastISel contains workaround for wrong debug
locations, which drops locations from instructions on processing constants,
but there isn't currently a way to use debug locations from constants there
as llvm::Constant doesn't cache it (yet). Although this is a bit different
issue, not directly related to these changes.

Differential Revision: http://reviews.llvm.org/D9084

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235977 91177308-0d34-0410-b5e6-96231b3b80d8
78 files changed:
include/llvm/CodeGen/SelectionDAG.h
include/llvm/CodeGen/SelectionDAGISel.h
include/llvm/CodeGen/SelectionDAGNodes.h
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
lib/CodeGen/SelectionDAG/StatepointLowering.cpp
lib/CodeGen/SelectionDAG/TargetLowering.cpp
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
lib/Target/AArch64/AArch64ISelLowering.cpp
lib/Target/AArch64/AArch64InstrFormats.td
lib/Target/AArch64/AArch64InstrInfo.td
lib/Target/ARM/ARMISelDAGToDAG.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/ARM/ARMInstrInfo.td
lib/Target/ARM/ARMInstrNEON.td
lib/Target/ARM/ARMInstrThumb.td
lib/Target/ARM/ARMInstrThumb2.td
lib/Target/ARM/ARMInstrVFP.td
lib/Target/ARM/ARMSelectionDAGInfo.cpp
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
lib/Target/Hexagon/HexagonISelLowering.cpp
lib/Target/Hexagon/HexagonInstrInfo.td
lib/Target/Hexagon/HexagonInstrInfoV4.td
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
lib/Target/MSP430/MSP430ISelLowering.cpp
lib/Target/Mips/Mips16ISelDAGToDAG.cpp
lib/Target/Mips/MipsISelDAGToDAG.h
lib/Target/Mips/MipsISelLowering.cpp
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
lib/Target/Mips/MipsSEISelLowering.cpp
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
lib/Target/NVPTX/NVPTXISelDAGToDAG.h
lib/Target/NVPTX/NVPTXISelLowering.cpp
lib/Target/NVPTX/NVPTXInstrInfo.td
lib/Target/NVPTX/NVPTXVector.td
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/PowerPC/PPCInstr64Bit.td
lib/Target/PowerPC/PPCInstrAltivec.td
lib/Target/PowerPC/PPCInstrHTM.td
lib/Target/PowerPC/PPCInstrInfo.td
lib/Target/R600/AMDGPUISelDAGToDAG.cpp
lib/Target/R600/AMDGPUISelLowering.cpp
lib/Target/R600/AMDGPUInstructions.td
lib/Target/R600/R600ISelLowering.cpp
lib/Target/R600/R600ISelLowering.h
lib/Target/R600/SIISelLowering.cpp
lib/Target/R600/SIInstrInfo.td
lib/Target/Sparc/SparcISelDAGToDAG.cpp
lib/Target/Sparc/SparcISelLowering.cpp
lib/Target/Sparc/SparcInstr64Bit.td
lib/Target/Sparc/SparcInstrInfo.td
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
lib/Target/SystemZ/SystemZISelLowering.cpp
lib/Target/SystemZ/SystemZOperands.td
lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
lib/Target/X86/X86ISelDAGToDAG.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrCompiler.td
lib/Target/X86/X86InstrFragmentsSIMD.td
lib/Target/X86/X86InstrInfo.td
lib/Target/X86/X86InstrShiftRotate.td
lib/Target/X86/X86SelectionDAGInfo.cpp
lib/Target/XCore/XCoreISelDAGToDAG.cpp
lib/Target/XCore/XCoreISelLowering.cpp
lib/Target/XCore/XCoreInstrInfo.td
test/DebugInfo/AArch64/constant-dbgloc.ll [new file with mode: 0644]
test/DebugInfo/ARM/constant-dbgloc.ll [new file with mode: 0644]
test/DebugInfo/constant-sdnodes-have-dbg-location.ll [new file with mode: 0644]