MIR Serialization: Change MIR syntax - use custom syntax for MBBs.

[oota-llvm.git] / test / CodeGen / MIR / AArch64 / multiple-lhs-operands.mir

diff --git a/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir b/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir
index d47c8ba47f65a4fb0ff7adf0be732a50e4804487..e23a352dff21056b033ecc916c243bcce33d25ca 100644 (file)
--- a/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir
+++ b/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir
@@ -15,15 +15,14 @@
 ...
 ---
 name:            trivial_fp_func
 ...
 ---
 name:            trivial_fp_func

-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%lr', '%fp', '%lr', '%fp' ]
-    instructions:
-      - '%sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2'
-      - '%fp = frame-setup ADDXri %sp, 0, 0'
-      - 'BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp'
-# CHECK: %sp, %fp, %lr = LDPXpost %sp, 2
-      - '%sp, %fp, %lr = LDPXpost %sp, 2'
-      - RET_ReallyLR
+body: |
+  bb.0.entry:
+    liveins: %lr, %fp, %lr, %fp
+
+    %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2
+    %fp = frame-setup ADDXri %sp, 0, 0
+    BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
+  ; CHECK: %sp, %fp, %lr = LDPXpost %sp, 2
+    %sp, %fp, %lr = LDPXpost %sp, 2
+    RET_ReallyLR

 ...
 ...