Added support for new condition code modeling scheme (i.e. physical register dependen...

[oota-llvm.git] / lib / Target / X86 / X86RegisterInfo.cpp

diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index f4907c14f5abd4fa92c66a3f7404798e05dc4bf4..08d88ac60e7d86d63954b278d66d92af306caf16 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -677,6 +677,30 @@ X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
       { X86::MUL32r,      X86::MUL32m },
       { X86::MUL64r,      X86::MUL64m },
       { X86::MUL8r,       X86::MUL8m },
+
+      // TEMPORARY
+      { X86::NEW_CMP16ri, X86::NEW_CMP16mi },
+      { X86::NEW_CMP16ri8,X86::NEW_CMP16mi8 },
+      { X86::NEW_CMP32ri, X86::NEW_CMP32mi },
+      { X86::NEW_CMP32ri8,X86::NEW_CMP32mi8 },
+      { X86::NEW_CMP64ri32,X86::NEW_CMP64mi32 },
+      { X86::NEW_CMP64ri8,X86::NEW_CMP64mi8 },
+      { X86::NEW_CMP8ri,  X86::NEW_CMP8mi },
+      { X86::NEW_SETAEr,  X86::NEW_SETAEm },
+      { X86::NEW_SETAr,   X86::NEW_SETAm },
+      { X86::NEW_SETBEr,  X86::NEW_SETBEm },
+      { X86::NEW_SETBr,   X86::NEW_SETBm },
+      { X86::NEW_SETEr,   X86::NEW_SETEm },
+      { X86::NEW_SETGEr,  X86::NEW_SETGEm },
+      { X86::NEW_SETGr,   X86::NEW_SETGm },
+      { X86::NEW_SETLEr,  X86::NEW_SETLEm },
+      { X86::NEW_SETLr,   X86::NEW_SETLm },
+      { X86::NEW_SETNEr,  X86::NEW_SETNEm },
+      { X86::NEW_SETNPr,  X86::NEW_SETNPm },
+      { X86::NEW_SETNSr,  X86::NEW_SETNSm },
+      { X86::NEW_SETPr,   X86::NEW_SETPm },
+      { X86::NEW_SETSr,   X86::NEW_SETSm },
+
       { X86::SETAEr,      X86::SETAEm },
       { X86::SETAr,       X86::SETAm },
       { X86::SETBEr,      X86::SETBEm },
@@ -787,6 +811,19 @@ X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
       { X86::MOVZX32rr8,      X86::MOVZX32rm8 },
       { X86::MOVZX64rr16,     X86::MOVZX64rm16 },
       { X86::MOVZX64rr8,      X86::MOVZX64rm8 },
+
+      // TEMPORARY
+      { X86::NEW_Int_COMISDrr,  X86::NEW_Int_COMISDrm },
+      { X86::NEW_Int_COMISSrr,  X86::NEW_Int_COMISSrm },
+      { X86::NEW_Int_UCOMISDrr, X86::NEW_Int_UCOMISDrm },
+      { X86::NEW_Int_UCOMISSrr, X86::NEW_Int_UCOMISSrm },
+      { X86::NEW_TEST16rr,    X86::NEW_TEST16rm },
+      { X86::NEW_TEST32rr,    X86::NEW_TEST32rm },
+      { X86::NEW_TEST64rr,    X86::NEW_TEST64rm },
+      { X86::NEW_TEST8rr,     X86::NEW_TEST8rm },
+      { X86::NEW_UCOMISDrr,   X86::NEW_UCOMISDrm },
+      { X86::NEW_UCOMISSrr,   X86::NEW_UCOMISSrm },
+
       { X86::PSHUFDri,        X86::PSHUFDmi },
       { X86::PSHUFHWri,       X86::PSHUFHWmi },
       { X86::PSHUFLWri,       X86::PSHUFLWmi },
@@ -920,6 +957,51 @@ X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
       { X86::MULPSrr,         X86::MULPSrm },
       { X86::MULSDrr,         X86::MULSDrm },
       { X86::MULSSrr,         X86::MULSSrm },
+
+      // TEMPORARY
+      { X86::NEW_CMOVA16rr,       X86::NEW_CMOVA16rm },
+      { X86::NEW_CMOVA32rr,       X86::NEW_CMOVA32rm },
+      { X86::NEW_CMOVA64rr,       X86::NEW_CMOVA64rm },
+      { X86::NEW_CMOVAE16rr,      X86::NEW_CMOVAE16rm },
+      { X86::NEW_CMOVAE32rr,      X86::NEW_CMOVAE32rm },
+      { X86::NEW_CMOVAE64rr,      X86::NEW_CMOVAE64rm },
+      { X86::NEW_CMOVB16rr,       X86::NEW_CMOVB16rm },
+      { X86::NEW_CMOVB32rr,       X86::NEW_CMOVB32rm },
+      { X86::NEW_CMOVB64rr,       X86::NEW_CMOVB64rm },
+      { X86::NEW_CMOVBE16rr,      X86::NEW_CMOVBE16rm },
+      { X86::NEW_CMOVBE32rr,      X86::NEW_CMOVBE32rm },
+      { X86::NEW_CMOVBE64rr,      X86::NEW_CMOVBE64rm },
+      { X86::NEW_CMOVE16rr,       X86::NEW_CMOVE16rm },
+      { X86::NEW_CMOVE32rr,       X86::NEW_CMOVE32rm },
+      { X86::NEW_CMOVE64rr,       X86::NEW_CMOVE64rm },
+      { X86::NEW_CMOVG16rr,       X86::NEW_CMOVG16rm },
+      { X86::NEW_CMOVG32rr,       X86::NEW_CMOVG32rm },
+      { X86::NEW_CMOVG64rr,       X86::NEW_CMOVG64rm },
+      { X86::NEW_CMOVGE16rr,      X86::NEW_CMOVGE16rm },
+      { X86::NEW_CMOVGE32rr,      X86::NEW_CMOVGE32rm },
+      { X86::NEW_CMOVGE64rr,      X86::NEW_CMOVGE64rm },
+      { X86::NEW_CMOVL16rr,       X86::NEW_CMOVL16rm },
+      { X86::NEW_CMOVL32rr,       X86::NEW_CMOVL32rm },
+      { X86::NEW_CMOVL64rr,       X86::NEW_CMOVL64rm },
+      { X86::NEW_CMOVLE16rr,      X86::NEW_CMOVLE16rm },
+      { X86::NEW_CMOVLE32rr,      X86::NEW_CMOVLE32rm },
+      { X86::NEW_CMOVLE64rr,      X86::NEW_CMOVLE64rm },
+      { X86::NEW_CMOVNE16rr,      X86::NEW_CMOVNE16rm },
+      { X86::NEW_CMOVNE32rr,      X86::NEW_CMOVNE32rm },
+      { X86::NEW_CMOVNE64rr,      X86::NEW_CMOVNE64rm },
+      { X86::NEW_CMOVNP16rr,      X86::NEW_CMOVNP16rm },
+      { X86::NEW_CMOVNP32rr,      X86::NEW_CMOVNP32rm },
+      { X86::NEW_CMOVNP64rr,      X86::NEW_CMOVNP64rm },
+      { X86::NEW_CMOVNS16rr,      X86::NEW_CMOVNS16rm },
+      { X86::NEW_CMOVNS32rr,      X86::NEW_CMOVNS32rm },
+      { X86::NEW_CMOVNS64rr,      X86::NEW_CMOVNS64rm },
+      { X86::NEW_CMOVP16rr,       X86::NEW_CMOVP16rm },
+      { X86::NEW_CMOVP32rr,       X86::NEW_CMOVP32rm },
+      { X86::NEW_CMOVP64rr,       X86::NEW_CMOVP64rm },
+      { X86::NEW_CMOVS16rr,       X86::NEW_CMOVS16rm },
+      { X86::NEW_CMOVS32rr,       X86::NEW_CMOVS32rm },
+      { X86::NEW_CMOVS64rr,       X86::NEW_CMOVS64rm },
+
       { X86::OR16rr,          X86::OR16rm },
       { X86::OR32rr,          X86::OR32rm },
       { X86::OR64rr,          X86::OR64rm },