def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
"Support POPCNT instruction">;
-// The MMX subtarget feature is separate from the rest of the SSE features
-// because it's important (for odd compatibility reasons) to be able to
-// turn it off explicitly while allowing SSE+ to be on.
-def FeatureMMX : SubtargetFeature<"mmx","HasMMX", "true",
- "Enable MMX instructions">;
+def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true",
+ "Support fxsave/fxrestore instructions">;
+
+def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true",
+ "Support xsave instructions">;
+
+def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
+ "Support xsaveopt instructions">;
+
+def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
+ "Support xsavec instructions">;
+
+def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true",
+ "Support xsaves instructions">;
def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
"Enable SSE instructions",
def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
"Enable SSE 4.2 instructions",
[FeatureSSE41]>;
+// The MMX subtarget feature is separate from the rest of the SSE features
+// because it's important (for odd compatibility reasons) to be able to
+// turn it off explicitly while allowing SSE+ to be on.
+def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
+ "Enable MMX instructions">;
def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
"Enable 3DNow! instructions",
[FeatureMMX]>;
def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
"Enable AVX-512 Vector Length eXtensions",
[FeatureAVX512]>;
+def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true",
+ "Enable protection keys">;
def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
"Enable packed carry-less multiplication instructions",
[FeatureSSE2]>;
"Support PRFCHW instructions">;
def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
"Support RDSEED instruction">;
+def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
+ "Support LAHF and SAHF instructions">;
def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
"Support MPX instructions">;
-def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
+def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
"Use LEA for adjusting the stack pointer">;
def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
"HasSlowDivide32", "true",
def : Proc<"pentium-mmx", [FeatureSlowUAMem16, FeatureMMX]>;
def : Proc<"i686", [FeatureSlowUAMem16]>;
def : Proc<"pentiumpro", [FeatureSlowUAMem16, FeatureCMOV]>;
-def : Proc<"pentium2", [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV]>;
-def : Proc<"pentium3", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1]>;
+def : Proc<"pentium2", [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV,
+ FeatureFXSR]>;
+def : Proc<"pentium3", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
+ FeatureFXSR]>;
def : Proc<"pentium3m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
- FeatureSlowBTMem]>;
+ FeatureFXSR, FeatureSlowBTMem]>;
def : Proc<"pentium-m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
- FeatureSlowBTMem]>;
-def : Proc<"pentium4", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2]>;
+ FeatureFXSR, FeatureSlowBTMem]>;
+def : Proc<"pentium4", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
+ FeatureFXSR]>;
def : Proc<"pentium4m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
- FeatureSlowBTMem]>;
+ FeatureFXSR, FeatureSlowBTMem]>;
// Intel Core Duo.
-def : ProcessorModel<
- "yonah", SandyBridgeModel,
- [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureSlowBTMem ]>;
+def : ProcessorModel<"yonah", SandyBridgeModel,
+ [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
+ FeatureSlowBTMem]>;
// NetBurst.
def : Proc<"prescott",
- [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureSlowBTMem ]>;
+ [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
+ FeatureSlowBTMem]>;
def : Proc<"nocona", [
FeatureSlowUAMem16,
FeatureMMX,
FeatureSSE3,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem
]>;
FeatureSlowUAMem16,
FeatureMMX,
FeatureSSSE3,
+ FeatureFXSR,
FeatureCMPXCHG16B,
- FeatureSlowBTMem
+ FeatureSlowBTMem,
+ FeatureLAHFSAHF
]>;
def : ProcessorModel<"penryn", SandyBridgeModel, [
FeatureSlowUAMem16,
FeatureMMX,
FeatureSSE41,
+ FeatureFXSR,
FeatureCMPXCHG16B,
- FeatureSlowBTMem
+ FeatureSlowBTMem,
+ FeatureLAHFSAHF
]>;
// Atom CPUs.
FeatureSlowUAMem16,
FeatureMMX,
FeatureSSSE3,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureMOVBE,
FeatureSlowBTMem,
- FeatureLeaForSP,
+ FeatureLEAForSP,
FeatureSlowDivide32,
FeatureSlowDivide64,
FeatureCallRegIndirect,
FeatureLEAUsesAG,
- FeaturePadShortFunctions
+ FeaturePadShortFunctions,
+ FeatureLAHFSAHF
]>;
def : BonnellProc<"bonnell">;
def : BonnellProc<"atom">; // Pin the generic name to the baseline.
ProcIntelSLM,
FeatureMMX,
FeatureSSE42,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureMOVBE,
FeaturePOPCNT,
FeaturePRFCHW,
FeatureSlowLEA,
FeatureSlowIncDec,
- FeatureSlowBTMem
+ FeatureSlowBTMem,
+ FeatureLAHFSAHF
]>;
def : SilvermontProc<"silvermont">;
def : SilvermontProc<"slm">; // Legacy alias.
class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
FeatureMMX,
FeatureSSE42,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
- FeaturePOPCNT
+ FeaturePOPCNT,
+ FeatureLAHFSAHF
]>;
def : NehalemProc<"nehalem">;
def : NehalemProc<"corei7">;
class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
FeatureMMX,
FeatureSSE42,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
FeaturePOPCNT,
FeatureAES,
- FeaturePCLMUL
+ FeaturePCLMUL,
+ FeatureLAHFSAHF
]>;
def : WestmereProc<"westmere">;
class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
FeatureMMX,
FeatureAVX,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
FeatureSlowUAMem32,
FeaturePOPCNT,
FeatureAES,
- FeaturePCLMUL
+ FeaturePCLMUL,
+ FeatureXSAVE,
+ FeatureXSAVEOPT,
+ FeatureLAHFSAHF
]>;
def : SandyBridgeProc<"sandybridge">;
def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
FeatureMMX,
FeatureAVX,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
FeatureSlowUAMem32,
FeaturePOPCNT,
FeatureAES,
FeaturePCLMUL,
+ FeatureXSAVE,
+ FeatureXSAVEOPT,
FeatureRDRAND,
FeatureF16C,
- FeatureFSGSBase
+ FeatureFSGSBase,
+ FeatureLAHFSAHF
]>;
def : IvyBridgeProc<"ivybridge">;
def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
FeatureMMX,
FeatureAVX2,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
FeaturePOPCNT,
FeatureAES,
FeaturePCLMUL,
FeatureRDRAND,
+ FeatureXSAVE,
+ FeatureXSAVEOPT,
FeatureF16C,
FeatureFSGSBase,
FeatureMOVBE,
FeatureFMA,
FeatureRTM,
FeatureHLE,
- FeatureSlowIncDec
+ FeatureSlowIncDec,
+ FeatureLAHFSAHF
]>;
def : HaswellProc<"haswell">;
def : HaswellProc<"core-avx2">; // Legacy alias.
class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
FeatureMMX,
FeatureAVX2,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
FeaturePOPCNT,
FeatureAES,
FeaturePCLMUL,
+ FeatureXSAVE,
+ FeatureXSAVEOPT,
FeatureRDRAND,
FeatureF16C,
FeatureFSGSBase,
FeatureHLE,
FeatureADX,
FeatureRDSEED,
- FeatureSlowIncDec
+ FeatureSlowIncDec,
+ FeatureLAHFSAHF
]>;
def : BroadwellProc<"broadwell">;
class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
FeatureMMX,
FeatureAVX512,
+ FeatureFXSR,
FeatureERI,
FeatureCDI,
FeaturePFI,
FeaturePOPCNT,
FeatureAES,
FeaturePCLMUL,
+ FeatureXSAVE,
+ FeatureXSAVEOPT,
FeatureRDRAND,
FeatureF16C,
FeatureFSGSBase,
FeatureRTM,
FeatureHLE,
FeatureSlowIncDec,
- FeatureMPX
+ FeatureMPX,
+ FeatureLAHFSAHF
]>;
def : KnightsLandingProc<"knl">;
class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
FeatureMMX,
FeatureAVX512,
+ FeatureFXSR,
FeatureCDI,
FeatureDQI,
FeatureBWI,
FeatureVLX,
+ FeaturePKU,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
FeaturePOPCNT,
FeatureAES,
FeaturePCLMUL,
+ FeatureXSAVE,
+ FeatureXSAVEOPT,
FeatureRDRAND,
FeatureF16C,
FeatureFSGSBase,
FeatureADX,
FeatureRDSEED,
FeatureSlowIncDec,
- FeatureMPX
+ FeatureMPX,
+ FeatureXSAVEC,
+ FeatureXSAVES,
+ FeatureLAHFSAHF
]>;
def : SkylakeProc<"skylake">;
def : SkylakeProc<"skx">; // Legacy alias.
def : Proc<"athlon-tbird", [FeatureSlowUAMem16, Feature3DNowA,
FeatureSlowBTMem, FeatureSlowSHLD]>;
def : Proc<"athlon-4", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
def : Proc<"athlon-xp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
def : Proc<"athlon-mp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
def : Proc<"k8", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
- Feature64Bit, FeatureSlowBTMem,
+ FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
FeatureSlowSHLD]>;
def : Proc<"opteron", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
- Feature64Bit, FeatureSlowBTMem,
+ FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
FeatureSlowSHLD]>;
def : Proc<"athlon64", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
- Feature64Bit, FeatureSlowBTMem,
+ FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
FeatureSlowSHLD]>;
def : Proc<"athlon-fx", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
- Feature64Bit, FeatureSlowBTMem,
+ FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
FeatureSlowSHLD]>;
def : Proc<"k8-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
- FeatureCMPXCHG16B, FeatureSlowBTMem,
+ FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
FeatureSlowSHLD]>;
def : Proc<"opteron-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
- FeatureCMPXCHG16B, FeatureSlowBTMem,
+ FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
FeatureSlowSHLD]>;
def : Proc<"athlon64-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
- FeatureCMPXCHG16B, FeatureSlowBTMem,
- FeatureSlowSHLD]>;
-def : Proc<"amdfam10", [FeatureSSE4A,
- Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
- FeaturePOPCNT, FeatureSlowBTMem,
- FeatureSlowSHLD]>;
-def : Proc<"barcelona", [FeatureSSE4A,
- Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
- FeaturePOPCNT, FeatureSlowBTMem,
+ FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
FeatureSlowSHLD]>;
+def : Proc<"amdfam10", [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
+ FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
+ FeatureSlowBTMem, FeatureSlowSHLD, FeatureLAHFSAHF]>;
+def : Proc<"barcelona", [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
+ FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
+ FeatureSlowBTMem, FeatureSlowSHLD, FeatureLAHFSAHF]>;
// Bobcat
def : Proc<"btver1", [
FeatureMMX,
FeatureSSSE3,
FeatureSSE4A,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeaturePRFCHW,
FeatureLZCNT,
FeaturePOPCNT,
- FeatureSlowSHLD
+ FeatureXSAVE,
+ FeatureSlowSHLD,
+ FeatureLAHFSAHF
]>;
// Jaguar
def : ProcessorModel<"btver2", BtVer2Model, [
FeatureMMX,
FeatureAVX,
+ FeatureFXSR,
FeatureSSE4A,
FeatureCMPXCHG16B,
FeaturePRFCHW,
FeatureMOVBE,
FeatureLZCNT,
FeaturePOPCNT,
- FeatureSlowSHLD
+ FeatureXSAVE,
+ FeatureXSAVEOPT,
+ FeatureSlowSHLD,
+ FeatureLAHFSAHF
]>;
// Bulldozer
FeaturePCLMUL,
FeatureMMX,
FeatureAVX,
+ FeatureFXSR,
FeatureSSE4A,
FeatureLZCNT,
FeaturePOPCNT,
- FeatureSlowSHLD
+ FeatureXSAVE,
+ FeatureSlowSHLD,
+ FeatureLAHFSAHF
]>;
// Piledriver
def : Proc<"bdver2", [
FeaturePCLMUL,
FeatureMMX,
FeatureAVX,
+ FeatureFXSR,
FeatureSSE4A,
FeatureF16C,
FeatureLZCNT,
FeaturePOPCNT,
+ FeatureXSAVE,
FeatureBMI,
FeatureTBM,
FeatureFMA,
- FeatureSlowSHLD
+ FeatureSlowSHLD,
+ FeatureLAHFSAHF
]>;
// Steamroller
FeaturePCLMUL,
FeatureMMX,
FeatureAVX,
+ FeatureFXSR,
FeatureSSE4A,
FeatureF16C,
FeatureLZCNT,
FeaturePOPCNT,
+ FeatureXSAVE,
FeatureBMI,
FeatureTBM,
FeatureFMA,
+ FeatureXSAVEOPT,
FeatureSlowSHLD,
- FeatureFSGSBase
+ FeatureFSGSBase,
+ FeatureLAHFSAHF
]>;
// Excavator
def : Proc<"bdver4", [
FeatureMMX,
FeatureAVX2,
+ FeatureFXSR,
FeatureXOP,
FeatureFMA4,
FeatureCMPXCHG16B,
FeatureF16C,
FeatureLZCNT,
FeaturePOPCNT,
+ FeatureXSAVE,
FeatureBMI,
FeatureBMI2,
FeatureTBM,
FeatureFMA,
- FeatureSSE4A,
- FeatureFSGSBase
+ FeatureXSAVEOPT,
+ FeatureFSGSBase,
+ FeatureLAHFSAHF
]>;
def : Proc<"geode", [FeatureSlowUAMem16, Feature3DNowA]>;
def : Proc<"winchip-c6", [FeatureSlowUAMem16, FeatureMMX]>;
def : Proc<"winchip2", [FeatureSlowUAMem16, Feature3DNow]>;
def : Proc<"c3", [FeatureSlowUAMem16, Feature3DNow]>;
-def : Proc<"c3-2", [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE1 ]>;
+def : Proc<"c3-2", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, FeatureFXSR]>;
// We also provide a generic 64-bit specific x86 processor model which tries to
// be good for modern chips without enabling instruction set encodings past the
// covers a huge swath of x86 processors. If there are specific scheduling
// knobs which need to be tuned differently for AMD chips, we might consider
// forming a common base for them.
-def : ProcessorModel<
- "x86-64", SandyBridgeModel,
- [ FeatureMMX, FeatureSSE2, Feature64Bit, FeatureSlowBTMem ]>;
+def : ProcessorModel<"x86-64", SandyBridgeModel,
+ [FeatureMMX, FeatureSSE2, FeatureFXSR, Feature64Bit,
+ FeatureSlowBTMem ]>;
//===----------------------------------------------------------------------===//
// Register File Description
projects / oota-llvm.git / blobdiff