1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26 "32-bit mode (80386)">;
27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28 "16-bit mode (i8086)">;
30 //===----------------------------------------------------------------------===//
31 // X86 Subtarget features
32 //===----------------------------------------------------------------------===//
34 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
35 "Enable conditional move instructions">;
37 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
38 "Support POPCNT instruction">;
40 // The MMX subtarget feature is separate from the rest of the SSE features
41 // because it's important (for odd compatibility reasons) to be able to
42 // turn it off explicitly while allowing SSE+ to be on.
43 def FeatureMMX : SubtargetFeature<"mmx","HasMMX", "true",
44 "Enable MMX instructions">;
46 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
47 "Enable SSE instructions",
48 // SSE codegen depends on cmovs, and all
49 // SSE1+ processors support them.
51 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
52 "Enable SSE2 instructions",
54 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
55 "Enable SSE3 instructions",
57 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
58 "Enable SSSE3 instructions",
60 def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
61 "Enable SSE 4.1 instructions",
63 def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
64 "Enable SSE 4.2 instructions",
66 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
67 "Enable 3DNow! instructions",
69 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
70 "Enable 3DNow! Athlon instructions",
72 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
73 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
74 // without disabling 64-bit mode.
75 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
76 "Support 64-bit instructions",
78 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
79 "64-bit with cmpxchg16b",
81 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
82 "Bit testing of memory is slow">;
83 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
84 "SHLD instruction is slow">;
85 // FIXME: This should not apply to CPUs that do not have SSE.
86 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
87 "IsUAMem16Slow", "true",
88 "Slow unaligned 16-byte memory access">;
89 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
90 "IsUAMem32Slow", "true",
91 "Slow unaligned 32-byte memory access">;
92 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
93 "Support SSE 4a instructions",
96 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
97 "Enable AVX instructions",
99 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
100 "Enable AVX2 instructions",
102 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
103 "Enable AVX-512 instructions",
105 def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
106 "Enable AVX-512 Exponential and Reciprocal Instructions",
108 def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
109 "Enable AVX-512 Conflict Detection Instructions",
111 def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
112 "Enable AVX-512 PreFetch Instructions",
114 def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
115 "Enable AVX-512 Doubleword and Quadword Instructions",
117 def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
118 "Enable AVX-512 Byte and Word Instructions",
120 def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
121 "Enable AVX-512 Vector Length eXtensions",
123 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
124 "Enable packed carry-less multiplication instructions",
126 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
127 "Enable three-operand fused multiple-add",
129 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
130 "Enable four-operand fused multiple-add",
131 [FeatureAVX, FeatureSSE4A]>;
132 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
133 "Enable XOP instructions",
135 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
136 "HasSSEUnalignedMem", "true",
137 "Allow unaligned memory operands with SSE instructions">;
138 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
139 "Enable AES instructions",
141 def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
142 "Enable TBM instructions">;
143 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
144 "Support MOVBE instruction">;
145 def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
146 "Support RDRAND instruction">;
147 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
148 "Support 16-bit floating point conversion instructions",
150 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
151 "Support FS/GS Base instructions">;
152 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
153 "Support LZCNT instruction">;
154 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
155 "Support BMI instructions">;
156 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
157 "Support BMI2 instructions">;
158 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
159 "Support RTM instructions">;
160 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
162 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
163 "Support ADX instructions">;
164 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
165 "Enable SHA instructions",
167 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
168 "Support PRFCHW instructions">;
169 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
170 "Support RDSEED instruction">;
171 def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
172 "Support MPX instructions">;
173 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
174 "Use LEA for adjusting the stack pointer">;
175 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
176 "HasSlowDivide32", "true",
177 "Use 8-bit divide for positive values less than 256">;
178 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
179 "HasSlowDivide64", "true",
180 "Use 16-bit divide for positive values less than 65536">;
181 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
182 "PadShortFunctions", "true",
183 "Pad short functions">;
184 // TODO: This feature ought to be renamed.
185 // What it really refers to are CPUs for which certain instructions
186 // (which ones besides the example below?) are microcoded.
187 // The best examples of this are the memory forms of CALL and PUSH
188 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
189 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
190 "CallRegIndirect", "true",
191 "Call register indirect">;
192 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
193 "LEA instruction needs inputs at AG stage">;
194 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
195 "LEA instruction with certain arguments is slow">;
196 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
197 "INC and DEC instructions are slower than ADD and SUB">;
199 : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
200 "Use software floating point features.">;
202 //===----------------------------------------------------------------------===//
203 // X86 processors supported.
204 //===----------------------------------------------------------------------===//
206 include "X86Schedule.td"
208 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
209 "Intel Atom processors">;
210 def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
211 "Intel Silvermont processors">;
213 class Proc<string Name, list<SubtargetFeature> Features>
214 : ProcessorModel<Name, GenericModel, Features>;
216 def : Proc<"generic", [FeatureSlowUAMem16]>;
217 def : Proc<"i386", [FeatureSlowUAMem16]>;
218 def : Proc<"i486", [FeatureSlowUAMem16]>;
219 def : Proc<"i586", [FeatureSlowUAMem16]>;
220 def : Proc<"pentium", [FeatureSlowUAMem16]>;
221 def : Proc<"pentium-mmx", [FeatureSlowUAMem16, FeatureMMX]>;
222 def : Proc<"i686", [FeatureSlowUAMem16]>;
223 def : Proc<"pentiumpro", [FeatureSlowUAMem16, FeatureCMOV]>;
224 def : Proc<"pentium2", [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV]>;
225 def : Proc<"pentium3", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1]>;
226 def : Proc<"pentium3m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
228 def : Proc<"pentium-m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
230 def : Proc<"pentium4", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2]>;
231 def : Proc<"pentium4m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
235 def : ProcessorModel<
236 "yonah", SandyBridgeModel,
237 [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureSlowBTMem ]>;
240 def : Proc<"prescott",
241 [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureSlowBTMem ]>;
242 def : Proc<"nocona", [
250 // Intel Core 2 Solo/Duo.
251 def : ProcessorModel<"core2", SandyBridgeModel, [
258 def : ProcessorModel<"penryn", SandyBridgeModel, [
267 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
278 FeatureCallRegIndirect,
280 FeaturePadShortFunctions
282 def : BonnellProc<"bonnell">;
283 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
285 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
295 FeatureCallRegIndirect,
301 def : SilvermontProc<"silvermont">;
302 def : SilvermontProc<"slm">; // Legacy alias.
304 // "Arrandale" along with corei3 and corei5
305 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
312 def : NehalemProc<"nehalem">;
313 def : NehalemProc<"corei7">;
315 // Westmere is a similar machine to nehalem with some additional features.
316 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
317 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
326 def : WestmereProc<"westmere">;
328 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
329 // rather than a superset.
330 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
340 def : SandyBridgeProc<"sandybridge">;
341 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
343 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
356 def : IvyBridgeProc<"ivybridge">;
357 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
359 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
379 def : HaswellProc<"haswell">;
380 def : HaswellProc<"core-avx2">; // Legacy alias.
382 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
404 def : BroadwellProc<"broadwell">;
406 // FIXME: define KNL model
407 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
430 def : KnightsLandingProc<"knl">;
432 // FIXME: define SKX model
433 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
460 def : SkylakeProc<"skylake">;
461 def : SkylakeProc<"skx">; // Legacy alias.
466 def : Proc<"k6", [FeatureSlowUAMem16, FeatureMMX]>;
467 def : Proc<"k6-2", [FeatureSlowUAMem16, Feature3DNow]>;
468 def : Proc<"k6-3", [FeatureSlowUAMem16, Feature3DNow]>;
469 def : Proc<"athlon", [FeatureSlowUAMem16, Feature3DNowA,
470 FeatureSlowBTMem, FeatureSlowSHLD]>;
471 def : Proc<"athlon-tbird", [FeatureSlowUAMem16, Feature3DNowA,
472 FeatureSlowBTMem, FeatureSlowSHLD]>;
473 def : Proc<"athlon-4", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
474 FeatureSlowBTMem, FeatureSlowSHLD]>;
475 def : Proc<"athlon-xp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
476 FeatureSlowBTMem, FeatureSlowSHLD]>;
477 def : Proc<"athlon-mp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
478 FeatureSlowBTMem, FeatureSlowSHLD]>;
479 def : Proc<"k8", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
480 Feature64Bit, FeatureSlowBTMem,
482 def : Proc<"opteron", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
483 Feature64Bit, FeatureSlowBTMem,
485 def : Proc<"athlon64", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
486 Feature64Bit, FeatureSlowBTMem,
488 def : Proc<"athlon-fx", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
489 Feature64Bit, FeatureSlowBTMem,
491 def : Proc<"k8-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
492 FeatureCMPXCHG16B, FeatureSlowBTMem,
494 def : Proc<"opteron-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
495 FeatureCMPXCHG16B, FeatureSlowBTMem,
497 def : Proc<"athlon64-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
498 FeatureCMPXCHG16B, FeatureSlowBTMem,
500 def : Proc<"amdfam10", [FeatureSSE4A,
501 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
502 FeaturePOPCNT, FeatureSlowBTMem,
504 def : Proc<"barcelona", [FeatureSSE4A,
505 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
506 FeaturePOPCNT, FeatureSlowBTMem,
510 def : Proc<"btver1", [
522 def : ProcessorModel<"btver2", BtVer2Model, [
539 def : Proc<"bdver1", [
554 def : Proc<"bdver2", [
574 def : Proc<"bdver3", [
595 def : Proc<"bdver4", [
615 def : Proc<"geode", [FeatureSlowUAMem16, Feature3DNowA]>;
617 def : Proc<"winchip-c6", [FeatureSlowUAMem16, FeatureMMX]>;
618 def : Proc<"winchip2", [FeatureSlowUAMem16, Feature3DNow]>;
619 def : Proc<"c3", [FeatureSlowUAMem16, Feature3DNow]>;
620 def : Proc<"c3-2", [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE1 ]>;
622 // We also provide a generic 64-bit specific x86 processor model which tries to
623 // be good for modern chips without enabling instruction set encodings past the
624 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
625 // modern 64-bit x86 chip, and enables features that are generally beneficial.
627 // We currently use the Sandy Bridge model as the default scheduling model as
628 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
629 // covers a huge swath of x86 processors. If there are specific scheduling
630 // knobs which need to be tuned differently for AMD chips, we might consider
631 // forming a common base for them.
632 def : ProcessorModel<
633 "x86-64", SandyBridgeModel,
634 [ FeatureMMX, FeatureSSE2, Feature64Bit, FeatureSlowBTMem ]>;
636 //===----------------------------------------------------------------------===//
637 // Register File Description
638 //===----------------------------------------------------------------------===//
640 include "X86RegisterInfo.td"
642 //===----------------------------------------------------------------------===//
643 // Instruction Descriptions
644 //===----------------------------------------------------------------------===//
646 include "X86InstrInfo.td"
648 def X86InstrInfo : InstrInfo;
650 //===----------------------------------------------------------------------===//
651 // Calling Conventions
652 //===----------------------------------------------------------------------===//
654 include "X86CallingConv.td"
657 //===----------------------------------------------------------------------===//
659 //===----------------------------------------------------------------------===//
661 def ATTAsmParser : AsmParser {
662 string AsmParserClassName = "AsmParser";
665 def ATTAsmParserVariant : AsmParserVariant {
671 // Discard comments in assembly strings.
672 string CommentDelimiter = "#";
674 // Recognize hard coded registers.
675 string RegisterPrefix = "%";
678 def IntelAsmParserVariant : AsmParserVariant {
682 string Name = "intel";
684 // Discard comments in assembly strings.
685 string CommentDelimiter = ";";
687 // Recognize hard coded registers.
688 string RegisterPrefix = "";
691 //===----------------------------------------------------------------------===//
693 //===----------------------------------------------------------------------===//
695 // The X86 target supports two different syntaxes for emitting machine code.
696 // This is controlled by the -x86-asm-syntax={att|intel}
697 def ATTAsmWriter : AsmWriter {
698 string AsmWriterClassName = "ATTInstPrinter";
701 def IntelAsmWriter : AsmWriter {
702 string AsmWriterClassName = "IntelInstPrinter";
707 // Information about the instructions...
708 let InstructionSet = X86InstrInfo;
709 let AssemblyParsers = [ATTAsmParser];
710 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
711 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];