CellSPU:

[oota-llvm.git] / lib / Target / CellSPU / SPU64InstrInfo.td

diff --git a/lib/Target/CellSPU/SPU64InstrInfo.td b/lib/Target/CellSPU/SPU64InstrInfo.td
index 33298946c52125eabd66737c012db78336aabea9..06eb1496def79d325c62813c4fcfbea6fab89d77 100644 (file)
--- a/lib/Target/CellSPU/SPU64InstrInfo.td
+++ b/lib/Target/CellSPU/SPU64InstrInfo.td
@@ -30,8 +30,8 @@
 // selb instruction definition for i64. Note that the selection mask is
 // a vector, produced by various forms of FSM:
 def SELBr64_cond:
-   SELBInst<(outs R64C:$rT), (ins R64C:$rA, R64C:$rB, VECREG:$rC),
-            [/* no pattern */]>;
+  SELBInst<(outs R64C:$rT), (ins R64C:$rA, R64C:$rB, VECREG:$rC),
+           [/* no pattern */]>;
 
 // The generic i64 select pattern, which assumes that the comparison result
 // is in a 32-bit register that contains a select mask pattern (i.e., gather