CellSPU:
authorScott Michel <scottm@aero.org>
Mon, 26 Jan 2009 03:31:40 +0000 (03:31 +0000)
committerScott Michel <scottm@aero.org>
Mon, 26 Jan 2009 03:31:40 +0000 (03:31 +0000)
commitc9c8b2a804b2cd3d33a6a965e06a21ff93968f97
tree6141f9f0ec12fefbdd984667613aaf33da6068af
parent5bf4b7556f025587a8d1a14bd0fb39c12fc9c170
CellSPU:
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
  selection (SPUISelDAGtoDAG.cpp).

  <rant>DAGCombiner will insert all kinds of 64-bit optimizations after
  operation legalization occurs and now we have to do most of the work that
  instruction selection should be doing twice (once to determine if v2i64
  build_vector can be handled by SelectCode(), which then runs all of the
  predicates a second time to select the necessary instructions.) But,
  CellSPU is a good citizen.</rant>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
12 files changed:
lib/Target/CellSPU/SPU64InstrInfo.td
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
lib/Target/CellSPU/SPUISelLowering.cpp
lib/Target/CellSPU/SPUISelLowering.h
lib/Target/CellSPU/SPUInstrInfo.cpp
lib/Target/CellSPU/SPUInstrInfo.td
test/CodeGen/CellSPU/fcmp.ll [deleted file]
test/CodeGen/CellSPU/fcmp32.ll [new file with mode: 0644]
test/CodeGen/CellSPU/fcmp64.ll [new file with mode: 0644]
test/CodeGen/CellSPU/fneg-fabs.ll
test/CodeGen/CellSPU/select_bits.ll
test/CodeGen/CellSPU/shift_ops.ll