//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
-// This file contains the Alpha implementation of the MRegisterInfo class.
+// This file contains the Alpha implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
using namespace llvm;
{
}
-void
-AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, int FrameIdx,
- const TargetRegisterClass *RC) const {
- //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
- // << FrameIdx << "\n";
- //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
- if (RC == Alpha::F4RCRegisterClass)
- BuildMI(MBB, MI, TII.get(Alpha::STS))
- .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else if (RC == Alpha::F8RCRegisterClass)
- BuildMI(MBB, MI, TII.get(Alpha::STT))
- .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else if (RC == Alpha::GPRCRegisterClass)
- BuildMI(MBB, MI, TII.get(Alpha::STQ))
- .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else
- abort();
-}
-
-void
-AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIdx,
- const TargetRegisterClass *RC) const {
- //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
- // << FrameIdx << "\n";
- if (RC == Alpha::F4RCRegisterClass)
- BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
- .addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else if (RC == Alpha::F8RCRegisterClass)
- BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
- .addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else if (RC == Alpha::GPRCRegisterClass)
- BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
- .addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else
- abort();
-}
-
-MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
- unsigned OpNum,
- int FrameIndex) const {
- // Make sure this is a reg-reg copy.
- unsigned Opc = MI->getOpcode();
-
- MachineInstr *NewMI = NULL;
- switch(Opc) {
- default:
- break;
- case Alpha::BISr:
- case Alpha::CPYSS:
- case Alpha::CPYST:
- if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
- if (OpNum == 0) { // move -> store
- unsigned InReg = MI->getOperand(1).getReg();
- Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
- ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
- NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
- .addReg(Alpha::F31);
- } else { // load -> move
- unsigned OutReg = MI->getOperand(0).getReg();
- Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
- ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
- NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
- .addReg(Alpha::F31);
- }
- }
- break;
- }
- if (NewMI)
- NewMI->copyKillDeadInfo(MI);
- return 0;
-}
-
-
-void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *RC) const {
- //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
- if (RC == Alpha::GPRCRegisterClass) {
- BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
- } else if (RC == Alpha::F4RCRegisterClass) {
- BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
- } else if (RC == Alpha::F8RCRegisterClass) {
- BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
- } else {
- cerr << "Attempt to copy register that is not GPR or FPR";
- abort();
- }
+void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ unsigned DestReg,
+ const MachineInstr *Orig) const {
+ MachineInstr *MI = Orig->clone();
+ MI->getOperand(0).setReg(DestReg);
+ MBB.insert(I, MI);
}
-const unsigned* AlphaRegisterInfo::getCalleeSavedRegs() const {
+const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
+ const {
static const unsigned CalleeSavedRegs[] = {
Alpha::R9, Alpha::R10,
Alpha::R11, Alpha::R12,
}
const TargetRegisterClass* const*
-AlphaRegisterInfo::getCalleeSavedRegClasses() const {
+AlphaRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
return CalleeSavedRegClasses;
}
+BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ BitVector Reserved(getNumRegs());
+ Reserved.set(Alpha::R15);
+ Reserved.set(Alpha::R30);
+ Reserved.set(Alpha::R31);
+ return Reserved;
+}
+
//===----------------------------------------------------------------------===//
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//
// 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
// <amt>'
MachineInstr *Old = I;
- uint64_t Amount = Old->getOperand(0).getImmedValue();
+ uint64_t Amount = Old->getOperand(0).getImm();
if (Amount != 0) {
// We need to keep the stack aligned properly. To do this, we round the
// amount of space needed for the outgoing arguments up to the next
//variable locals
//<- SP
-void
-AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
+void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ int SPAdj, RegScavenger *RS) const {
+ assert(SPAdj == 0 && "Unexpected");
+
unsigned i = 0;
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
}
- int FrameIndex = MI.getOperand(i).getFrameIndex();
+ int FrameIndex = MI.getOperand(i).getIndex();
// Add the base register of R30 (SP) or R15 (FP).
MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
// Get the number of bytes to allocate from the FrameInfo
long NumBytes = MFI->getStackSize();
- if (MFI->hasCalls() && !FP) {
- // We reserve argument space for call sites in the function immediately on
- // entry to the current function. This eliminates the need for add/sub
- // brackets around call sites.
- //If there is a frame pointer, then we don't do this
- NumBytes += MFI->getMaxCallFrameSize();
- DOUT << "Added " << MFI->getMaxCallFrameSize()
- << " to the stack due to calls\n";
- }
-
if (FP)
NumBytes += 8; //reserve space for the old FP
return hasFP(MF) ? Alpha::R15 : Alpha::R30;
}
+unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
+ assert(0 && "What is the exception register");
+ return 0;
+}
+
+unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
+ assert(0 && "What is the exception handler register");
+ return 0;
+}
+
+int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
+ assert(0 && "What is the dwarf register number");
+ return -1;
+}
+
#include "AlphaGenRegisterInfo.inc"
std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
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