1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
234 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
235 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
236 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
237 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
238 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
239 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
240 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
241 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
242 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
243 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
244 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
245 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
246 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
247 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
248 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
249 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
250 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
252 Name = Rec->getName();
253 AsmString = Rec->getValueAsString("AsmString");
255 Operands = &insn.Operands.OperandList;
257 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
258 (Name.find("CRC32") != Name.npos);
259 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
261 // Check for 64-bit inst which does not require REX
264 // FIXME: Is there some better way to check for In64BitMode?
265 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
266 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
267 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
268 Predicates[i]->getName().find("In32Bit") != Name.npos) {
272 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
278 ShouldBeEmitted = true;
281 void RecognizableInstr::processInstr(DisassemblerTables &tables,
282 const CodeGenInstruction &insn,
285 // Ignore "asm parser only" instructions.
286 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
289 RecognizableInstr recogInstr(tables, insn, uid);
291 recogInstr.emitInstructionSpecifier();
293 if (recogInstr.shouldBeEmitted())
294 recogInstr.emitDecodePath(tables);
297 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
298 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
299 (HasEVEX_KZ ? n##_KZ : \
300 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
302 InstructionContext RecognizableInstr::insnContext() const {
303 InstructionContext insnContext;
306 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
307 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
308 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
311 if (HasVEX_LPrefix && HasVEX_WPrefix) {
313 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
314 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
315 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
316 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
317 Prefix == X86Local::TAXD)
318 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
320 insnContext = EVEX_KB(IC_EVEX_L_W);
321 } else if (HasVEX_LPrefix) {
324 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
325 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
326 insnContext = EVEX_KB(IC_EVEX_L_XS);
327 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
328 Prefix == X86Local::TAXD)
329 insnContext = EVEX_KB(IC_EVEX_L_XD);
331 insnContext = EVEX_KB(IC_EVEX_L);
333 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
336 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
337 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
338 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
339 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
340 Prefix == X86Local::TAXD)
341 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
343 insnContext = EVEX_KB(IC_EVEX_L2_W);
344 } else if (HasEVEX_L2Prefix) {
347 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
348 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
349 Prefix == X86Local::TAXD)
350 insnContext = EVEX_KB(IC_EVEX_L2_XD);
351 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
352 insnContext = EVEX_KB(IC_EVEX_L2_XS);
354 insnContext = EVEX_KB(IC_EVEX_L2);
356 else if (HasVEX_WPrefix) {
359 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
360 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
361 insnContext = EVEX_KB(IC_EVEX_W_XS);
362 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
363 Prefix == X86Local::TAXD)
364 insnContext = EVEX_KB(IC_EVEX_W_XD);
366 insnContext = EVEX_KB(IC_EVEX_W);
369 else if (HasOpSizePrefix)
370 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
371 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
372 Prefix == X86Local::TAXD)
373 insnContext = EVEX_KB(IC_EVEX_XD);
374 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
375 insnContext = EVEX_KB(IC_EVEX_XS);
377 insnContext = EVEX_KB(IC_EVEX);
379 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
380 if (HasVEX_LPrefix && HasVEX_WPrefix) {
382 insnContext = IC_VEX_L_W_OPSIZE;
383 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
384 insnContext = IC_VEX_L_W_XS;
385 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
386 Prefix == X86Local::TAXD)
387 insnContext = IC_VEX_L_W_XD;
389 insnContext = IC_VEX_L_W;
390 } else if (HasOpSizePrefix && HasVEX_LPrefix)
391 insnContext = IC_VEX_L_OPSIZE;
392 else if (HasOpSizePrefix && HasVEX_WPrefix)
393 insnContext = IC_VEX_W_OPSIZE;
394 else if (HasOpSizePrefix)
395 insnContext = IC_VEX_OPSIZE;
396 else if (HasVEX_LPrefix &&
397 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
398 insnContext = IC_VEX_L_XS;
399 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
400 Prefix == X86Local::T8XD ||
401 Prefix == X86Local::TAXD))
402 insnContext = IC_VEX_L_XD;
403 else if (HasVEX_WPrefix &&
404 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
405 insnContext = IC_VEX_W_XS;
406 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
407 Prefix == X86Local::T8XD ||
408 Prefix == X86Local::TAXD))
409 insnContext = IC_VEX_W_XD;
410 else if (HasVEX_WPrefix)
411 insnContext = IC_VEX_W;
412 else if (HasVEX_LPrefix)
413 insnContext = IC_VEX_L;
414 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
415 Prefix == X86Local::TAXD)
416 insnContext = IC_VEX_XD;
417 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
418 insnContext = IC_VEX_XS;
420 insnContext = IC_VEX;
421 } else if (Is64Bit || HasREX_WPrefix) {
422 if (HasREX_WPrefix && HasOpSizePrefix)
423 insnContext = IC_64BIT_REXW_OPSIZE;
424 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
425 Prefix == X86Local::T8XD ||
426 Prefix == X86Local::TAXD))
427 insnContext = IC_64BIT_XD_OPSIZE;
428 else if (HasOpSizePrefix &&
429 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
430 insnContext = IC_64BIT_XS_OPSIZE;
431 else if (HasOpSizePrefix)
432 insnContext = IC_64BIT_OPSIZE;
433 else if (HasAdSizePrefix)
434 insnContext = IC_64BIT_ADSIZE;
435 else if (HasREX_WPrefix &&
436 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
437 insnContext = IC_64BIT_REXW_XS;
438 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
439 Prefix == X86Local::T8XD ||
440 Prefix == X86Local::TAXD))
441 insnContext = IC_64BIT_REXW_XD;
442 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
443 Prefix == X86Local::TAXD)
444 insnContext = IC_64BIT_XD;
445 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
446 insnContext = IC_64BIT_XS;
447 else if (HasREX_WPrefix)
448 insnContext = IC_64BIT_REXW;
450 insnContext = IC_64BIT;
452 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
453 Prefix == X86Local::T8XD ||
454 Prefix == X86Local::TAXD))
455 insnContext = IC_XD_OPSIZE;
456 else if (HasOpSizePrefix &&
457 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
458 insnContext = IC_XS_OPSIZE;
459 else if (HasOpSizePrefix && HasAdSizePrefix)
460 insnContext = IC_OPSIZE_ADSIZE;
461 else if (HasOpSizePrefix)
462 insnContext = IC_OPSIZE;
463 else if (HasAdSizePrefix)
464 insnContext = IC_ADSIZE;
465 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
466 Prefix == X86Local::TAXD)
468 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
469 Prefix == X86Local::REP)
478 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
483 // Filter out intrinsics
485 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
487 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
488 return FILTER_STRONG;
491 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
492 // printed as a separate "instruction".
500 // Filter out instructions with a LOCK prefix;
501 // prefer forms that do not have the prefix
507 if (Name == "VMASKMOVDQU64")
510 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
511 // For now, just prefer the REP versions.
512 if (Name == "XACQUIRE_PREFIX" ||
513 Name == "XRELEASE_PREFIX")
516 return FILTER_NORMAL;
519 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
520 unsigned &physicalOperandIndex,
521 unsigned &numPhysicalOperands,
522 const unsigned *operandMapping,
523 OperandEncoding (*encodingFromString)
525 bool hasOpSizePrefix)) {
527 if (physicalOperandIndex >= numPhysicalOperands)
530 assert(physicalOperandIndex < numPhysicalOperands);
533 while (operandMapping[operandIndex] != operandIndex) {
534 Spec->operands[operandIndex].encoding = ENCODING_DUP;
535 Spec->operands[operandIndex].type =
536 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
540 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
542 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
544 Spec->operands[operandIndex].type = typeFromString(typeName,
550 ++physicalOperandIndex;
553 void RecognizableInstr::emitInstructionSpecifier() {
556 if (!ShouldBeEmitted)
561 Spec->filtered = true;
564 ShouldBeEmitted = false;
570 Spec->insnContext = insnContext();
572 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
574 unsigned numOperands = OperandList.size();
575 unsigned numPhysicalOperands = 0;
577 // operandMapping maps from operands in OperandList to their originals.
578 // If operandMapping[i] != i, then the entry is a duplicate.
579 unsigned operandMapping[X86_MAX_OPERANDS];
580 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
582 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
583 if (OperandList[operandIndex].Constraints.size()) {
584 const CGIOperandList::ConstraintInfo &Constraint =
585 OperandList[operandIndex].Constraints[0];
586 if (Constraint.isTied()) {
587 operandMapping[operandIndex] = operandIndex;
588 operandMapping[Constraint.getTiedOperand()] = operandIndex;
590 ++numPhysicalOperands;
591 operandMapping[operandIndex] = operandIndex;
594 ++numPhysicalOperands;
595 operandMapping[operandIndex] = operandIndex;
599 #define HANDLE_OPERAND(class) \
600 handleOperand(false, \
602 physicalOperandIndex, \
603 numPhysicalOperands, \
605 class##EncodingFromString);
607 #define HANDLE_OPTIONAL(class) \
608 handleOperand(true, \
610 physicalOperandIndex, \
611 numPhysicalOperands, \
613 class##EncodingFromString);
615 // operandIndex should always be < numOperands
616 unsigned operandIndex = 0;
617 // physicalOperandIndex should always be < numPhysicalOperands
618 unsigned physicalOperandIndex = 0;
621 case X86Local::RawFrm:
622 // Operand 1 (optional) is an address or immediate.
623 // Operand 2 (optional) is an immediate.
624 assert(numPhysicalOperands <= 2 &&
625 "Unexpected number of operands for RawFrm");
626 HANDLE_OPTIONAL(relocation)
627 HANDLE_OPTIONAL(immediate)
629 case X86Local::AddRegFrm:
630 // Operand 1 is added to the opcode.
631 // Operand 2 (optional) is an address.
632 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
633 "Unexpected number of operands for AddRegFrm");
634 HANDLE_OPERAND(opcodeModifier)
635 HANDLE_OPTIONAL(relocation)
637 case X86Local::MRMDestReg:
638 // Operand 1 is a register operand in the R/M field.
639 // Operand 2 is a register operand in the Reg/Opcode field.
640 // - In AVX, there is a register operand in the VEX.vvvv field here -
641 // Operand 3 (optional) is an immediate.
643 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
644 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
646 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
647 "Unexpected number of operands for MRMDestRegFrm");
649 HANDLE_OPERAND(rmRegister)
652 // FIXME: In AVX, the register below becomes the one encoded
653 // in ModRMVEX and the one above the one in the VEX.VVVV field
654 HANDLE_OPERAND(vvvvRegister)
656 HANDLE_OPERAND(roRegister)
657 HANDLE_OPTIONAL(immediate)
659 case X86Local::MRMDestMem:
660 // Operand 1 is a memory operand (possibly SIB-extended)
661 // Operand 2 is a register operand in the Reg/Opcode field.
662 // - In AVX, there is a register operand in the VEX.vvvv field here -
663 // Operand 3 (optional) is an immediate.
665 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
666 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
668 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
669 "Unexpected number of operands for MRMDestMemFrm");
670 HANDLE_OPERAND(memory)
673 HANDLE_OPERAND(writemaskRegister)
676 // FIXME: In AVX, the register below becomes the one encoded
677 // in ModRMVEX and the one above the one in the VEX.VVVV field
678 HANDLE_OPERAND(vvvvRegister)
680 HANDLE_OPERAND(roRegister)
681 HANDLE_OPTIONAL(immediate)
683 case X86Local::MRMSrcReg:
684 // Operand 1 is a register operand in the Reg/Opcode field.
685 // Operand 2 is a register operand in the R/M field.
686 // - In AVX, there is a register operand in the VEX.vvvv field here -
687 // Operand 3 (optional) is an immediate.
688 // Operand 4 (optional) is an immediate.
690 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
691 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
692 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
694 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
695 "Unexpected number of operands for MRMSrcRegFrm");
697 HANDLE_OPERAND(roRegister)
700 HANDLE_OPERAND(writemaskRegister)
703 // FIXME: In AVX, the register below becomes the one encoded
704 // in ModRMVEX and the one above the one in the VEX.VVVV field
705 HANDLE_OPERAND(vvvvRegister)
708 HANDLE_OPERAND(immediate)
710 HANDLE_OPERAND(rmRegister)
712 if (HasVEX_4VOp3Prefix)
713 HANDLE_OPERAND(vvvvRegister)
715 if (!HasMemOp4Prefix)
716 HANDLE_OPTIONAL(immediate)
717 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
718 HANDLE_OPTIONAL(immediate)
720 case X86Local::MRMSrcMem:
721 // Operand 1 is a register operand in the Reg/Opcode field.
722 // Operand 2 is a memory operand (possibly SIB-extended)
723 // - In AVX, there is a register operand in the VEX.vvvv field here -
724 // Operand 3 (optional) is an immediate.
726 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
727 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
728 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
730 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
731 "Unexpected number of operands for MRMSrcMemFrm");
733 HANDLE_OPERAND(roRegister)
736 HANDLE_OPERAND(writemaskRegister)
739 // FIXME: In AVX, the register below becomes the one encoded
740 // in ModRMVEX and the one above the one in the VEX.VVVV field
741 HANDLE_OPERAND(vvvvRegister)
744 HANDLE_OPERAND(immediate)
746 HANDLE_OPERAND(memory)
748 if (HasVEX_4VOp3Prefix)
749 HANDLE_OPERAND(vvvvRegister)
751 if (!HasMemOp4Prefix)
752 HANDLE_OPTIONAL(immediate)
753 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
755 case X86Local::MRM0r:
756 case X86Local::MRM1r:
757 case X86Local::MRM2r:
758 case X86Local::MRM3r:
759 case X86Local::MRM4r:
760 case X86Local::MRM5r:
761 case X86Local::MRM6r:
762 case X86Local::MRM7r:
764 // Operand 1 is a register operand in the R/M field.
765 // Operand 2 (optional) is an immediate or relocation.
766 // Operand 3 (optional) is an immediate.
767 unsigned kOp = (HasEVEX_K) ? 1:0;
768 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
769 if (numPhysicalOperands > 3 + kOp + Op4v)
770 llvm_unreachable("Unexpected number of operands for MRMnr");
773 HANDLE_OPERAND(vvvvRegister)
776 HANDLE_OPERAND(writemaskRegister)
777 HANDLE_OPTIONAL(rmRegister)
778 HANDLE_OPTIONAL(relocation)
779 HANDLE_OPTIONAL(immediate)
781 case X86Local::MRM0m:
782 case X86Local::MRM1m:
783 case X86Local::MRM2m:
784 case X86Local::MRM3m:
785 case X86Local::MRM4m:
786 case X86Local::MRM5m:
787 case X86Local::MRM6m:
788 case X86Local::MRM7m:
790 // Operand 1 is a memory operand (possibly SIB-extended)
791 // Operand 2 (optional) is an immediate or relocation.
792 unsigned kOp = (HasEVEX_K) ? 1:0;
793 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
794 if (numPhysicalOperands < 1 + kOp + Op4v ||
795 numPhysicalOperands > 2 + kOp + Op4v)
796 llvm_unreachable("Unexpected number of operands for MRMnm");
799 HANDLE_OPERAND(vvvvRegister)
801 HANDLE_OPERAND(writemaskRegister)
802 HANDLE_OPERAND(memory)
803 HANDLE_OPTIONAL(relocation)
805 case X86Local::RawFrmImm8:
806 // operand 1 is a 16-bit immediate
807 // operand 2 is an 8-bit immediate
808 assert(numPhysicalOperands == 2 &&
809 "Unexpected number of operands for X86Local::RawFrmImm8");
810 HANDLE_OPERAND(immediate)
811 HANDLE_OPERAND(immediate)
813 case X86Local::RawFrmImm16:
814 // operand 1 is a 16-bit immediate
815 // operand 2 is a 16-bit immediate
816 HANDLE_OPERAND(immediate)
817 HANDLE_OPERAND(immediate)
819 case X86Local::MRM_F8:
820 if (Opcode == 0xc6) {
821 assert(numPhysicalOperands == 1 &&
822 "Unexpected number of operands for X86Local::MRM_F8");
823 HANDLE_OPERAND(immediate)
824 } else if (Opcode == 0xc7) {
825 assert(numPhysicalOperands == 1 &&
826 "Unexpected number of operands for X86Local::MRM_F8");
827 HANDLE_OPERAND(relocation)
830 case X86Local::MRMInitReg:
835 #undef HANDLE_OPERAND
836 #undef HANDLE_OPTIONAL
839 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
840 // Special cases where the LLVM tables are not complete
842 #define MAP(from, to) \
843 case X86Local::MRM_##from: \
844 filter = new ExactFilter(0x##from); \
847 OpcodeType opcodeType = (OpcodeType)-1;
849 ModRMFilter* filter = NULL;
850 uint8_t opcodeToSet = 0;
853 default: llvm_unreachable("Invalid prefix!");
854 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
858 opcodeType = TWOBYTE;
862 if (needsModRMForDecode(Form))
863 filter = new ModFilter(isRegFormat(Form));
865 filter = new DumbFilter();
867 #define EXTENSION_TABLE(n) case 0x##n:
868 TWO_BYTE_EXTENSION_TABLES
869 #undef EXTENSION_TABLE
872 llvm_unreachable("Unhandled two-byte extended opcode");
873 case X86Local::MRM0r:
874 case X86Local::MRM1r:
875 case X86Local::MRM2r:
876 case X86Local::MRM3r:
877 case X86Local::MRM4r:
878 case X86Local::MRM5r:
879 case X86Local::MRM6r:
880 case X86Local::MRM7r:
881 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
883 case X86Local::MRM0m:
884 case X86Local::MRM1m:
885 case X86Local::MRM2m:
886 case X86Local::MRM3m:
887 case X86Local::MRM4m:
888 case X86Local::MRM5m:
889 case X86Local::MRM6m:
890 case X86Local::MRM7m:
891 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
897 opcodeToSet = Opcode;
902 opcodeType = THREEBYTE_38;
905 if (needsModRMForDecode(Form))
906 filter = new ModFilter(isRegFormat(Form));
908 filter = new DumbFilter();
910 #define EXTENSION_TABLE(n) case 0x##n:
911 THREE_BYTE_38_EXTENSION_TABLES
912 #undef EXTENSION_TABLE
915 llvm_unreachable("Unhandled two-byte extended opcode");
916 case X86Local::MRM0r:
917 case X86Local::MRM1r:
918 case X86Local::MRM2r:
919 case X86Local::MRM3r:
920 case X86Local::MRM4r:
921 case X86Local::MRM5r:
922 case X86Local::MRM6r:
923 case X86Local::MRM7r:
924 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
926 case X86Local::MRM0m:
927 case X86Local::MRM1m:
928 case X86Local::MRM2m:
929 case X86Local::MRM3m:
930 case X86Local::MRM4m:
931 case X86Local::MRM5m:
932 case X86Local::MRM6m:
933 case X86Local::MRM7m:
934 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
940 opcodeToSet = Opcode;
944 opcodeType = THREEBYTE_3A;
945 if (needsModRMForDecode(Form))
946 filter = new ModFilter(isRegFormat(Form));
948 filter = new DumbFilter();
949 opcodeToSet = Opcode;
952 opcodeType = THREEBYTE_A6;
953 if (needsModRMForDecode(Form))
954 filter = new ModFilter(isRegFormat(Form));
956 filter = new DumbFilter();
957 opcodeToSet = Opcode;
960 opcodeType = THREEBYTE_A7;
961 if (needsModRMForDecode(Form))
962 filter = new ModFilter(isRegFormat(Form));
964 filter = new DumbFilter();
965 opcodeToSet = Opcode;
968 opcodeType = XOP8_MAP;
969 if (needsModRMForDecode(Form))
970 filter = new ModFilter(isRegFormat(Form));
972 filter = new DumbFilter();
973 opcodeToSet = Opcode;
976 opcodeType = XOP9_MAP;
979 if (needsModRMForDecode(Form))
980 filter = new ModFilter(isRegFormat(Form));
982 filter = new DumbFilter();
984 #define EXTENSION_TABLE(n) case 0x##n:
985 XOP9_MAP_EXTENSION_TABLES
986 #undef EXTENSION_TABLE
989 llvm_unreachable("Unhandled XOP9 extended opcode");
990 case X86Local::MRM0r:
991 case X86Local::MRM1r:
992 case X86Local::MRM2r:
993 case X86Local::MRM3r:
994 case X86Local::MRM4r:
995 case X86Local::MRM5r:
996 case X86Local::MRM6r:
997 case X86Local::MRM7r:
998 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1000 case X86Local::MRM0m:
1001 case X86Local::MRM1m:
1002 case X86Local::MRM2m:
1003 case X86Local::MRM3m:
1004 case X86Local::MRM4m:
1005 case X86Local::MRM5m:
1006 case X86Local::MRM6m:
1007 case X86Local::MRM7m:
1008 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1013 } // switch (Opcode)
1014 opcodeToSet = Opcode;
1016 case X86Local::XOPA:
1017 opcodeType = XOPA_MAP;
1018 if (needsModRMForDecode(Form))
1019 filter = new ModFilter(isRegFormat(Form));
1021 filter = new DumbFilter();
1022 opcodeToSet = Opcode;
1032 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1033 assert(Form == X86Local::RawFrm);
1034 opcodeType = ONEBYTE;
1035 filter = new ExactFilter(Opcode);
1036 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1040 opcodeType = ONEBYTE;
1042 #define EXTENSION_TABLE(n) case 0x##n:
1043 ONE_BYTE_EXTENSION_TABLES
1044 #undef EXTENSION_TABLE
1047 llvm_unreachable("Fell through the cracks of a single-byte "
1049 case X86Local::MRM0r:
1050 case X86Local::MRM1r:
1051 case X86Local::MRM2r:
1052 case X86Local::MRM3r:
1053 case X86Local::MRM4r:
1054 case X86Local::MRM5r:
1055 case X86Local::MRM6r:
1056 case X86Local::MRM7r:
1057 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1059 case X86Local::MRM0m:
1060 case X86Local::MRM1m:
1061 case X86Local::MRM2m:
1062 case X86Local::MRM3m:
1063 case X86Local::MRM4m:
1064 case X86Local::MRM5m:
1065 case X86Local::MRM6m:
1066 case X86Local::MRM7m:
1067 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1082 llvm_unreachable("Unhandled escape opcode form");
1083 case X86Local::MRM0r:
1084 case X86Local::MRM1r:
1085 case X86Local::MRM2r:
1086 case X86Local::MRM3r:
1087 case X86Local::MRM4r:
1088 case X86Local::MRM5r:
1089 case X86Local::MRM6r:
1090 case X86Local::MRM7r:
1091 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1093 case X86Local::MRM0m:
1094 case X86Local::MRM1m:
1095 case X86Local::MRM2m:
1096 case X86Local::MRM3m:
1097 case X86Local::MRM4m:
1098 case X86Local::MRM5m:
1099 case X86Local::MRM6m:
1100 case X86Local::MRM7m:
1101 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1106 if (needsModRMForDecode(Form))
1107 filter = new ModFilter(isRegFormat(Form));
1109 filter = new DumbFilter();
1111 } // switch (Opcode)
1112 opcodeToSet = Opcode;
1113 } // switch (Prefix)
1115 assert(opcodeType != (OpcodeType)-1 &&
1116 "Opcode type not set");
1117 assert(filter && "Filter not set");
1119 if (Form == X86Local::AddRegFrm) {
1120 assert(((opcodeToSet & 7) == 0) &&
1121 "ADDREG_FRM opcode not aligned");
1123 uint8_t currentOpcode;
1125 for (currentOpcode = opcodeToSet;
1126 currentOpcode < opcodeToSet + 8;
1128 tables.setTableFields(opcodeType,
1132 UID, Is32Bit, IgnoresVEX_L);
1134 tables.setTableFields(opcodeType,
1138 UID, Is32Bit, IgnoresVEX_L);
1146 #define TYPE(str, type) if (s == str) return type;
1147 OperandType RecognizableInstr::typeFromString(const std::string &s,
1149 bool hasREX_WPrefix,
1150 bool hasOpSizePrefix) {
1152 // For SSE instructions, we ignore the OpSize prefix and force operand
1154 TYPE("GR16", TYPE_R16)
1155 TYPE("GR32", TYPE_R32)
1156 TYPE("GR64", TYPE_R64)
1158 if(hasREX_WPrefix) {
1159 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1161 TYPE("GR32", TYPE_R32)
1163 if(!hasOpSizePrefix) {
1164 // For instructions without an OpSize prefix, a declared 16-bit register or
1165 // immediate encoding is special.
1166 TYPE("GR16", TYPE_R16)
1167 TYPE("i16imm", TYPE_IMM16)
1169 TYPE("i16mem", TYPE_Mv)
1170 TYPE("i16imm", TYPE_IMMv)
1171 TYPE("i16i8imm", TYPE_IMMv)
1172 TYPE("GR16", TYPE_Rv)
1173 TYPE("i32mem", TYPE_Mv)
1174 TYPE("i32imm", TYPE_IMMv)
1175 TYPE("i32i8imm", TYPE_IMM32)
1176 TYPE("u32u8imm", TYPE_IMM32)
1177 TYPE("GR32", TYPE_Rv)
1178 TYPE("GR32orGR64", TYPE_R32)
1179 TYPE("i64mem", TYPE_Mv)
1180 TYPE("i64i32imm", TYPE_IMM64)
1181 TYPE("i64i8imm", TYPE_IMM64)
1182 TYPE("GR64", TYPE_R64)
1183 TYPE("i8mem", TYPE_M8)
1184 TYPE("i8imm", TYPE_IMM8)
1185 TYPE("GR8", TYPE_R8)
1186 TYPE("VR128", TYPE_XMM128)
1187 TYPE("VR128X", TYPE_XMM128)
1188 TYPE("f128mem", TYPE_M128)
1189 TYPE("f256mem", TYPE_M256)
1190 TYPE("f512mem", TYPE_M512)
1191 TYPE("FR64", TYPE_XMM64)
1192 TYPE("FR64X", TYPE_XMM64)
1193 TYPE("f64mem", TYPE_M64FP)
1194 TYPE("sdmem", TYPE_M64FP)
1195 TYPE("FR32", TYPE_XMM32)
1196 TYPE("FR32X", TYPE_XMM32)
1197 TYPE("f32mem", TYPE_M32FP)
1198 TYPE("ssmem", TYPE_M32FP)
1199 TYPE("RST", TYPE_ST)
1200 TYPE("i128mem", TYPE_M128)
1201 TYPE("i256mem", TYPE_M256)
1202 TYPE("i512mem", TYPE_M512)
1203 TYPE("i64i32imm_pcrel", TYPE_REL64)
1204 TYPE("i16imm_pcrel", TYPE_REL16)
1205 TYPE("i32imm_pcrel", TYPE_REL32)
1206 TYPE("SSECC", TYPE_IMM3)
1207 TYPE("AVXCC", TYPE_IMM5)
1208 TYPE("AVX512RC", TYPE_IMM32)
1209 TYPE("brtarget", TYPE_RELv)
1210 TYPE("uncondbrtarget", TYPE_RELv)
1211 TYPE("brtarget8", TYPE_REL8)
1212 TYPE("f80mem", TYPE_M80FP)
1213 TYPE("lea32mem", TYPE_LEA)
1214 TYPE("lea64_32mem", TYPE_LEA)
1215 TYPE("lea64mem", TYPE_LEA)
1216 TYPE("VR64", TYPE_MM64)
1217 TYPE("i64imm", TYPE_IMMv)
1218 TYPE("opaque32mem", TYPE_M1616)
1219 TYPE("opaque48mem", TYPE_M1632)
1220 TYPE("opaque80mem", TYPE_M1664)
1221 TYPE("opaque512mem", TYPE_M512)
1222 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1223 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1224 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1225 TYPE("offset8", TYPE_MOFFS8)
1226 TYPE("offset16", TYPE_MOFFS16)
1227 TYPE("offset32", TYPE_MOFFS32)
1228 TYPE("offset64", TYPE_MOFFS64)
1229 TYPE("VR256", TYPE_XMM256)
1230 TYPE("VR256X", TYPE_XMM256)
1231 TYPE("VR512", TYPE_XMM512)
1232 TYPE("VK1", TYPE_VK1)
1233 TYPE("VK1WM", TYPE_VK1)
1234 TYPE("VK8", TYPE_VK8)
1235 TYPE("VK8WM", TYPE_VK8)
1236 TYPE("VK16", TYPE_VK16)
1237 TYPE("VK16WM", TYPE_VK16)
1238 TYPE("GR16_NOAX", TYPE_Rv)
1239 TYPE("GR32_NOAX", TYPE_Rv)
1240 TYPE("GR64_NOAX", TYPE_R64)
1241 TYPE("vx32mem", TYPE_M32)
1242 TYPE("vy32mem", TYPE_M32)
1243 TYPE("vz32mem", TYPE_M32)
1244 TYPE("vx64mem", TYPE_M64)
1245 TYPE("vy64mem", TYPE_M64)
1246 TYPE("vy64xmem", TYPE_M64)
1247 TYPE("vz64mem", TYPE_M64)
1248 errs() << "Unhandled type string " << s << "\n";
1249 llvm_unreachable("Unhandled type string");
1253 #define ENCODING(str, encoding) if (s == str) return encoding;
1254 OperandEncoding RecognizableInstr::immediateEncodingFromString
1255 (const std::string &s,
1256 bool hasOpSizePrefix) {
1257 if(!hasOpSizePrefix) {
1258 // For instructions without an OpSize prefix, a declared 16-bit register or
1259 // immediate encoding is special.
1260 ENCODING("i16imm", ENCODING_IW)
1262 ENCODING("i32i8imm", ENCODING_IB)
1263 ENCODING("u32u8imm", ENCODING_IB)
1264 ENCODING("SSECC", ENCODING_IB)
1265 ENCODING("AVXCC", ENCODING_IB)
1266 ENCODING("AVX512RC", ENCODING_IB)
1267 ENCODING("i16imm", ENCODING_Iv)
1268 ENCODING("i16i8imm", ENCODING_IB)
1269 ENCODING("i32imm", ENCODING_Iv)
1270 ENCODING("i64i32imm", ENCODING_ID)
1271 ENCODING("i64i8imm", ENCODING_IB)
1272 ENCODING("i8imm", ENCODING_IB)
1273 // This is not a typo. Instructions like BLENDVPD put
1274 // register IDs in 8-bit immediates nowadays.
1275 ENCODING("FR32", ENCODING_IB)
1276 ENCODING("FR64", ENCODING_IB)
1277 ENCODING("VR128", ENCODING_IB)
1278 ENCODING("VR256", ENCODING_IB)
1279 ENCODING("FR32X", ENCODING_IB)
1280 ENCODING("FR64X", ENCODING_IB)
1281 ENCODING("VR128X", ENCODING_IB)
1282 ENCODING("VR256X", ENCODING_IB)
1283 ENCODING("VR512", ENCODING_IB)
1284 errs() << "Unhandled immediate encoding " << s << "\n";
1285 llvm_unreachable("Unhandled immediate encoding");
1288 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1289 (const std::string &s,
1290 bool hasOpSizePrefix) {
1291 ENCODING("RST", ENCODING_FP)
1292 ENCODING("GR16", ENCODING_RM)
1293 ENCODING("GR32", ENCODING_RM)
1294 ENCODING("GR32orGR64", ENCODING_RM)
1295 ENCODING("GR64", ENCODING_RM)
1296 ENCODING("GR8", ENCODING_RM)
1297 ENCODING("VR128", ENCODING_RM)
1298 ENCODING("VR128X", ENCODING_RM)
1299 ENCODING("FR64", ENCODING_RM)
1300 ENCODING("FR32", ENCODING_RM)
1301 ENCODING("FR64X", ENCODING_RM)
1302 ENCODING("FR32X", ENCODING_RM)
1303 ENCODING("VR64", ENCODING_RM)
1304 ENCODING("VR256", ENCODING_RM)
1305 ENCODING("VR256X", ENCODING_RM)
1306 ENCODING("VR512", ENCODING_RM)
1307 ENCODING("VK1", ENCODING_RM)
1308 ENCODING("VK8", ENCODING_RM)
1309 ENCODING("VK16", ENCODING_RM)
1310 errs() << "Unhandled R/M register encoding " << s << "\n";
1311 llvm_unreachable("Unhandled R/M register encoding");
1314 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1315 (const std::string &s,
1316 bool hasOpSizePrefix) {
1317 ENCODING("GR16", ENCODING_REG)
1318 ENCODING("GR32", ENCODING_REG)
1319 ENCODING("GR32orGR64", ENCODING_REG)
1320 ENCODING("GR64", ENCODING_REG)
1321 ENCODING("GR8", ENCODING_REG)
1322 ENCODING("VR128", ENCODING_REG)
1323 ENCODING("FR64", ENCODING_REG)
1324 ENCODING("FR32", ENCODING_REG)
1325 ENCODING("VR64", ENCODING_REG)
1326 ENCODING("SEGMENT_REG", ENCODING_REG)
1327 ENCODING("DEBUG_REG", ENCODING_REG)
1328 ENCODING("CONTROL_REG", ENCODING_REG)
1329 ENCODING("VR256", ENCODING_REG)
1330 ENCODING("VR256X", ENCODING_REG)
1331 ENCODING("VR128X", ENCODING_REG)
1332 ENCODING("FR64X", ENCODING_REG)
1333 ENCODING("FR32X", ENCODING_REG)
1334 ENCODING("VR512", ENCODING_REG)
1335 ENCODING("VK1", ENCODING_REG)
1336 ENCODING("VK8", ENCODING_REG)
1337 ENCODING("VK16", ENCODING_REG)
1338 ENCODING("VK1WM", ENCODING_REG)
1339 ENCODING("VK8WM", ENCODING_REG)
1340 ENCODING("VK16WM", ENCODING_REG)
1341 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1342 llvm_unreachable("Unhandled reg/opcode register encoding");
1345 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1346 (const std::string &s,
1347 bool hasOpSizePrefix) {
1348 ENCODING("GR32", ENCODING_VVVV)
1349 ENCODING("GR64", ENCODING_VVVV)
1350 ENCODING("FR32", ENCODING_VVVV)
1351 ENCODING("FR64", ENCODING_VVVV)
1352 ENCODING("VR128", ENCODING_VVVV)
1353 ENCODING("VR256", ENCODING_VVVV)
1354 ENCODING("FR32X", ENCODING_VVVV)
1355 ENCODING("FR64X", ENCODING_VVVV)
1356 ENCODING("VR128X", ENCODING_VVVV)
1357 ENCODING("VR256X", ENCODING_VVVV)
1358 ENCODING("VR512", ENCODING_VVVV)
1359 ENCODING("VK1", ENCODING_VVVV)
1360 ENCODING("VK8", ENCODING_VVVV)
1361 ENCODING("VK16", ENCODING_VVVV)
1362 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1363 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1366 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1367 (const std::string &s,
1368 bool hasOpSizePrefix) {
1369 ENCODING("VK1WM", ENCODING_WRITEMASK)
1370 ENCODING("VK8WM", ENCODING_WRITEMASK)
1371 ENCODING("VK16WM", ENCODING_WRITEMASK)
1372 errs() << "Unhandled mask register encoding " << s << "\n";
1373 llvm_unreachable("Unhandled mask register encoding");
1376 OperandEncoding RecognizableInstr::memoryEncodingFromString
1377 (const std::string &s,
1378 bool hasOpSizePrefix) {
1379 ENCODING("i16mem", ENCODING_RM)
1380 ENCODING("i32mem", ENCODING_RM)
1381 ENCODING("i64mem", ENCODING_RM)
1382 ENCODING("i8mem", ENCODING_RM)
1383 ENCODING("ssmem", ENCODING_RM)
1384 ENCODING("sdmem", ENCODING_RM)
1385 ENCODING("f128mem", ENCODING_RM)
1386 ENCODING("f256mem", ENCODING_RM)
1387 ENCODING("f512mem", ENCODING_RM)
1388 ENCODING("f64mem", ENCODING_RM)
1389 ENCODING("f32mem", ENCODING_RM)
1390 ENCODING("i128mem", ENCODING_RM)
1391 ENCODING("i256mem", ENCODING_RM)
1392 ENCODING("i512mem", ENCODING_RM)
1393 ENCODING("f80mem", ENCODING_RM)
1394 ENCODING("lea32mem", ENCODING_RM)
1395 ENCODING("lea64_32mem", ENCODING_RM)
1396 ENCODING("lea64mem", ENCODING_RM)
1397 ENCODING("opaque32mem", ENCODING_RM)
1398 ENCODING("opaque48mem", ENCODING_RM)
1399 ENCODING("opaque80mem", ENCODING_RM)
1400 ENCODING("opaque512mem", ENCODING_RM)
1401 ENCODING("vx32mem", ENCODING_RM)
1402 ENCODING("vy32mem", ENCODING_RM)
1403 ENCODING("vz32mem", ENCODING_RM)
1404 ENCODING("vx64mem", ENCODING_RM)
1405 ENCODING("vy64mem", ENCODING_RM)
1406 ENCODING("vy64xmem", ENCODING_RM)
1407 ENCODING("vz64mem", ENCODING_RM)
1408 errs() << "Unhandled memory encoding " << s << "\n";
1409 llvm_unreachable("Unhandled memory encoding");
1412 OperandEncoding RecognizableInstr::relocationEncodingFromString
1413 (const std::string &s,
1414 bool hasOpSizePrefix) {
1415 if(!hasOpSizePrefix) {
1416 // For instructions without an OpSize prefix, a declared 16-bit register or
1417 // immediate encoding is special.
1418 ENCODING("i16imm", ENCODING_IW)
1420 ENCODING("i16imm", ENCODING_Iv)
1421 ENCODING("i16i8imm", ENCODING_IB)
1422 ENCODING("i32imm", ENCODING_Iv)
1423 ENCODING("i32i8imm", ENCODING_IB)
1424 ENCODING("i64i32imm", ENCODING_ID)
1425 ENCODING("i64i8imm", ENCODING_IB)
1426 ENCODING("i8imm", ENCODING_IB)
1427 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1428 ENCODING("i16imm_pcrel", ENCODING_IW)
1429 ENCODING("i32imm_pcrel", ENCODING_ID)
1430 ENCODING("brtarget", ENCODING_Iv)
1431 ENCODING("brtarget8", ENCODING_IB)
1432 ENCODING("i64imm", ENCODING_IO)
1433 ENCODING("offset8", ENCODING_Ia)
1434 ENCODING("offset16", ENCODING_Ia)
1435 ENCODING("offset32", ENCODING_Ia)
1436 ENCODING("offset64", ENCODING_Ia)
1437 errs() << "Unhandled relocation encoding " << s << "\n";
1438 llvm_unreachable("Unhandled relocation encoding");
1441 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1442 (const std::string &s,
1443 bool hasOpSizePrefix) {
1444 ENCODING("GR32", ENCODING_Rv)
1445 ENCODING("GR64", ENCODING_RO)
1446 ENCODING("GR16", ENCODING_Rv)
1447 ENCODING("GR8", ENCODING_RB)
1448 ENCODING("GR16_NOAX", ENCODING_Rv)
1449 ENCODING("GR32_NOAX", ENCODING_Rv)
1450 ENCODING("GR64_NOAX", ENCODING_RO)
1451 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1452 llvm_unreachable("Unhandled opcode modifier encoding");