1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86DisassemblerTables.h"
20 #include "llvm/TableGen/TableGenBackend.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/Format.h"
26 using namespace X86Disassembler;
28 /// inheritsFrom - Indicates whether all instructions in one class also belong
31 /// @param child - The class that may be the subset
32 /// @param parent - The class that may be the superset
33 /// @return - True if child is a subset of parent, false otherwise.
34 static inline bool inheritsFrom(InstructionContext child,
35 InstructionContext parent,
36 bool VEX_LIG = false) {
42 return(inheritsFrom(child, IC_64BIT) ||
43 inheritsFrom(child, IC_OPSIZE) ||
44 inheritsFrom(child, IC_XD) ||
45 inheritsFrom(child, IC_XS));
47 return(inheritsFrom(child, IC_64BIT_REXW) ||
48 inheritsFrom(child, IC_64BIT_OPSIZE) ||
49 inheritsFrom(child, IC_64BIT_XD) ||
50 inheritsFrom(child, IC_64BIT_XS));
52 return inheritsFrom(child, IC_64BIT_OPSIZE);
54 return inheritsFrom(child, IC_64BIT_XD);
56 return inheritsFrom(child, IC_64BIT_XS);
58 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
60 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
62 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
63 inheritsFrom(child, IC_64BIT_REXW_XD) ||
64 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
66 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
68 return(inheritsFrom(child, IC_64BIT_REXW_XD));
70 return(inheritsFrom(child, IC_64BIT_REXW_XS));
71 case IC_64BIT_XD_OPSIZE:
72 case IC_64BIT_XS_OPSIZE:
74 case IC_64BIT_REXW_XD:
75 case IC_64BIT_REXW_XS:
76 case IC_64BIT_REXW_OPSIZE:
79 return inheritsFrom(child, IC_VEX_W) ||
80 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
82 return inheritsFrom(child, IC_VEX_W_XS) ||
83 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
85 return inheritsFrom(child, IC_VEX_W_XD) ||
86 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
88 return inheritsFrom(child, IC_VEX_W_OPSIZE) ||
89 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
100 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
101 case IC_VEX_L_W_OPSIZE:
104 llvm_unreachable("Unknown instruction class");
108 /// outranks - Indicates whether, if an instruction has two different applicable
109 /// classes, which class should be preferred when performing decode. This
110 /// imposes a total ordering (ties are resolved toward "lower")
112 /// @param upper - The class that may be preferable
113 /// @param lower - The class that may be less preferable
114 /// @return - True if upper is to be preferred, false otherwise.
115 static inline bool outranks(InstructionContext upper,
116 InstructionContext lower) {
117 assert(upper < IC_max);
118 assert(lower < IC_max);
120 #define ENUM_ENTRY(n, r, d) r,
121 static int ranks[IC_max] = {
126 return (ranks[upper] > ranks[lower]);
129 /// stringForContext - Returns a string containing the name of a particular
130 /// InstructionContext, usually for diagnostic purposes.
132 /// @param insnContext - The instruction class to transform to a string.
133 /// @return - A statically-allocated string constant that contains the
134 /// name of the instruction class.
135 static inline const char* stringForContext(InstructionContext insnContext) {
136 switch (insnContext) {
138 llvm_unreachable("Unhandled instruction class");
139 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
147 /// stringForOperandType - Like stringForContext, but for OperandTypes.
148 static inline const char* stringForOperandType(OperandType type) {
151 llvm_unreachable("Unhandled type");
152 #define ENUM_ENTRY(i, d) case i: return #i;
158 /// stringForOperandEncoding - like stringForContext, but for
159 /// OperandEncodings.
160 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
163 llvm_unreachable("Unhandled encoding");
164 #define ENUM_ENTRY(i, d) case i: return #i;
170 void DisassemblerTables::emitOneID(raw_ostream &o,
173 bool addComma) const {
175 o.indent(i * 2) << format("0x%hx", id);
177 o.indent(i * 2) << 0;
185 o << InstructionSpecifiers[id].name;
191 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by
192 /// all ModR/M decisions for instructions that are invalid for all possible
193 /// ModR/M byte values.
195 /// @param o - The output stream on which to emit the table.
196 /// @param i - The indentation level for that output stream.
197 static void emitEmptyTable(raw_ostream &o, uint32_t &i)
199 o.indent(i * 2) << "0x0, /* EmptyTable */\n";
202 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
203 /// be compacted by eliminating redundant information.
205 /// @param decision - The decision to be compacted.
206 /// @return - The compactest available representation for the decision.
207 static ModRMDecisionType getDecisionType(ModRMDecision &decision)
209 bool satisfiesOneEntry = true;
210 bool satisfiesSplitRM = true;
214 for (index = 0; index < 256; ++index) {
215 if (decision.instructionIDs[index] != decision.instructionIDs[0])
216 satisfiesOneEntry = false;
218 if (((index & 0xc0) == 0xc0) &&
219 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
220 satisfiesSplitRM = false;
222 if (((index & 0xc0) != 0xc0) &&
223 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
224 satisfiesSplitRM = false;
227 if (satisfiesOneEntry)
228 return MODRM_ONEENTRY;
230 if (satisfiesSplitRM)
231 return MODRM_SPLITRM;
236 /// stringForDecisionType - Returns a statically-allocated string corresponding
237 /// to a particular decision type.
239 /// @param dt - The decision type.
240 /// @return - A pointer to the statically-allocated string (e.g.,
241 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
242 static const char* stringForDecisionType(ModRMDecisionType dt)
244 #define ENUM_ENTRY(n) case n: return #n;
247 llvm_unreachable("Unknown decision type");
253 /// stringForModifierType - Returns a statically-allocated string corresponding
254 /// to an opcode modifier type.
256 /// @param mt - The modifier type.
257 /// @return - A pointer to the statically-allocated string (e.g.,
258 /// "MODIFIER_NONE" for MODIFIER_NONE).
259 static const char* stringForModifierType(ModifierType mt)
261 #define ENUM_ENTRY(n) case n: return #n;
264 llvm_unreachable("Unknown modifier type");
270 DisassemblerTables::DisassemblerTables() {
273 for (i = 0; i < array_lengthof(Tables); i++) {
274 Tables[i] = new ContextDecision;
275 memset(Tables[i], 0, sizeof(ContextDecision));
278 HasConflicts = false;
281 DisassemblerTables::~DisassemblerTables() {
284 for (i = 0; i < array_lengthof(Tables); i++)
288 void DisassemblerTables::emitModRMDecision(raw_ostream &o1,
292 ModRMDecision &decision)
294 static uint64_t sTableNumber = 0;
295 static uint64_t sEntryNumber = 1;
296 ModRMDecisionType dt = getDecisionType(decision);
299 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
301 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
304 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
305 o2.indent(i2) << 0 << " /* EmptyTable */\n";
308 o2.indent(i2) << "}";
312 o1 << "/* Table" << sTableNumber << " */\n";
317 llvm_unreachable("Unknown decision type");
319 emitOneID(o1, i1, decision.instructionIDs[0], true);
322 emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00
323 emitOneID(o1, i1, decision.instructionIDs[0xc0], true); // mod = 0b11
326 for (index = 0; index < 256; ++index)
327 emitOneID(o1, i1, decision.instructionIDs[index], true);
333 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
336 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
337 o2.indent(i2) << sEntryNumber << " /* Table" << sTableNumber << " */\n";
340 o2.indent(i2) << "}";
344 llvm_unreachable("Unknown decision type");
359 void DisassemblerTables::emitOpcodeDecision(
364 OpcodeDecision &decision) const {
367 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
369 o2.indent(i2) << "{" << "\n";
372 for (index = 0; index < 256; ++index) {
375 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
377 emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]);
386 o2.indent(i2) << "}" << "\n";
388 o2.indent(i2) << "}" << "\n";
391 void DisassemblerTables::emitContextDecision(
396 ContextDecision &decision,
397 const char* name) const {
398 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
400 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
405 for (index = 0; index < IC_max; ++index) {
406 o2.indent(i2) << "/* ";
407 o2 << stringForContext((InstructionContext)index);
411 emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]);
413 if (index + 1 < IC_max)
418 o2.indent(i2) << "}" << "\n";
420 o2.indent(i2) << "};" << "\n";
423 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, uint32_t &i)
425 o.indent(i * 2) << "static const struct InstructionSpecifier ";
426 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
430 uint16_t numInstructions = InstructionSpecifiers.size();
431 uint16_t index, operandIndex;
433 for (index = 0; index < numInstructions; ++index) {
434 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
438 stringForModifierType(InstructionSpecifiers[index].modifierType);
441 o.indent(i * 2) << "0x";
442 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
445 o.indent(i * 2) << "{" << "\n";
448 for (operandIndex = 0; operandIndex < X86_MAX_OPERANDS; ++operandIndex) {
449 o.indent(i * 2) << "{ ";
450 o << stringForOperandEncoding(InstructionSpecifiers[index]
451 .operands[operandIndex]
454 o << stringForOperandType(InstructionSpecifiers[index]
455 .operands[operandIndex]
459 if (operandIndex < X86_MAX_OPERANDS - 1)
466 o.indent(i * 2) << "}," << "\n";
468 o.indent(i * 2) << "\"" << InstructionSpecifiers[index].name << "\"";
472 o.indent(i * 2) << "}";
474 if (index + 1 < numInstructions)
481 o.indent(i * 2) << "};" << "\n";
484 void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
487 o.indent(i * 2) << "static const InstructionContext " CONTEXTS_STR
491 for (index = 0; index < 256; ++index) {
494 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
495 o << "IC_VEX_L_W_OPSIZE";
496 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
497 o << "IC_VEX_L_OPSIZE";
498 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
500 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
502 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
503 o << "IC_VEX_W_OPSIZE";
504 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
506 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
508 else if (index & ATTR_VEXL)
510 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
512 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
513 o << "IC_VEX_OPSIZE";
514 else if ((index & ATTR_VEX) && (index & ATTR_XD))
516 else if ((index & ATTR_VEX) && (index & ATTR_XS))
518 else if (index & ATTR_VEX)
520 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
521 o << "IC_64BIT_REXW_XS";
522 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
523 o << "IC_64BIT_REXW_XD";
524 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
525 (index & ATTR_OPSIZE))
526 o << "IC_64BIT_REXW_OPSIZE";
527 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
528 o << "IC_64BIT_XD_OPSIZE";
529 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
530 o << "IC_64BIT_XS_OPSIZE";
531 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
533 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
535 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
536 o << "IC_64BIT_OPSIZE";
537 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
538 o << "IC_64BIT_REXW";
539 else if ((index & ATTR_64BIT))
541 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
543 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
545 else if (index & ATTR_XS)
547 else if (index & ATTR_XD)
549 else if (index & ATTR_OPSIZE)
559 o << " /* " << index << " */";
565 o.indent(i * 2) << "};" << "\n";
568 void DisassemblerTables::emitContextDecisions(raw_ostream &o1,
573 emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR);
574 emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
575 emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
576 emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
577 emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR);
578 emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR);
581 void DisassemblerTables::emit(raw_ostream &o) const {
588 raw_string_ostream o1(s1);
589 raw_string_ostream o2(s2);
591 emitInstructionInfo(o, i2);
594 emitContextTable(o, i2);
597 o << "static const InstrUID modRMTable[] = {\n";
599 emitEmptyTable(o1, i1);
601 emitContextDecisions(o1, o2, i1, i2);
612 void DisassemblerTables::setTableFields(ModRMDecision &decision,
613 const ModRMFilter &filter,
618 for (index = 0; index < 256; ++index) {
619 if (filter.accepts(index)) {
620 if (decision.instructionIDs[index] == uid)
623 if (decision.instructionIDs[index] != 0) {
624 InstructionSpecifier &newInfo =
625 InstructionSpecifiers[uid];
626 InstructionSpecifier &previousInfo =
627 InstructionSpecifiers[decision.instructionIDs[index]];
630 continue; // filtered instructions get lowest priority
632 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
633 newInfo.name == "XCHG32ar" ||
634 newInfo.name == "XCHG32ar64" ||
635 newInfo.name == "XCHG64ar"))
636 continue; // special case for XCHG*ar and NOOP
638 if (outranks(previousInfo.insnContext, newInfo.insnContext))
641 if (previousInfo.insnContext == newInfo.insnContext &&
642 !previousInfo.filtered) {
643 errs() << "Error: Primary decode conflict: ";
644 errs() << newInfo.name << " would overwrite " << previousInfo.name;
646 errs() << "ModRM " << index << "\n";
647 errs() << "Opcode " << (uint16_t)opcode << "\n";
648 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
653 decision.instructionIDs[index] = uid;
658 void DisassemblerTables::setTableFields(OpcodeType type,
659 InstructionContext insnContext,
661 const ModRMFilter &filter,
667 ContextDecision &decision = *Tables[type];
669 for (index = 0; index < IC_max; ++index) {
670 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
673 if (inheritsFrom((InstructionContext)index,
674 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
675 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],