1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
25 using namespace X86Disassembler;
27 /// stringForContext - Returns a string containing the name of a particular
28 /// InstructionContext, usually for diagnostic purposes.
30 /// @param insnContext - The instruction class to transform to a string.
31 /// @return - A statically-allocated string constant that contains the
32 /// name of the instruction class.
33 static inline const char* stringForContext(InstructionContext insnContext) {
34 switch (insnContext) {
36 llvm_unreachable("Unhandled instruction class");
37 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
40 ENUM_ENTRY(n##_KZ_B, r, d)
47 /// stringForOperandType - Like stringForContext, but for OperandTypes.
48 static inline const char* stringForOperandType(OperandType type) {
51 llvm_unreachable("Unhandled type");
52 #define ENUM_ENTRY(i, d) case i: return #i;
58 /// stringForOperandEncoding - like stringForContext, but for
60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
63 llvm_unreachable("Unhandled encoding");
64 #define ENUM_ENTRY(i, d) case i: return #i;
70 /// inheritsFrom - Indicates whether all instructions in one class also belong
73 /// @param child - The class that may be the subset
74 /// @param parent - The class that may be the superset
75 /// @return - True if child is a subset of parent, false otherwise.
76 static inline bool inheritsFrom(InstructionContext child,
77 InstructionContext parent,
78 bool VEX_LIG = false, bool AdSize64 = false) {
84 return(inheritsFrom(child, IC_64BIT, AdSize64) ||
85 inheritsFrom(child, IC_OPSIZE) ||
86 inheritsFrom(child, IC_ADSIZE) ||
87 inheritsFrom(child, IC_XD) ||
88 inheritsFrom(child, IC_XS));
90 return(inheritsFrom(child, IC_64BIT_REXW) ||
91 inheritsFrom(child, IC_64BIT_OPSIZE) ||
92 (!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) ||
93 inheritsFrom(child, IC_64BIT_XD) ||
94 inheritsFrom(child, IC_64BIT_XS));
96 return inheritsFrom(child, IC_64BIT_OPSIZE) ||
97 inheritsFrom(child, IC_OPSIZE_ADSIZE);
99 return inheritsFrom(child, IC_OPSIZE_ADSIZE);
100 case IC_OPSIZE_ADSIZE:
102 case IC_64BIT_ADSIZE:
103 return inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE);
104 case IC_64BIT_OPSIZE_ADSIZE:
107 return inheritsFrom(child, IC_64BIT_XD);
109 return inheritsFrom(child, IC_64BIT_XS);
111 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
113 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
115 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
116 inheritsFrom(child, IC_64BIT_REXW_XD) ||
117 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
118 case IC_64BIT_OPSIZE:
119 return inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
120 (!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE));
122 return(inheritsFrom(child, IC_64BIT_REXW_XD));
124 return(inheritsFrom(child, IC_64BIT_REXW_XS));
125 case IC_64BIT_XD_OPSIZE:
126 case IC_64BIT_XS_OPSIZE:
128 case IC_64BIT_REXW_XD:
129 case IC_64BIT_REXW_XS:
130 case IC_64BIT_REXW_OPSIZE:
133 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
134 inheritsFrom(child, IC_VEX_W) ||
135 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
137 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
138 inheritsFrom(child, IC_VEX_W_XS) ||
139 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
141 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
142 inheritsFrom(child, IC_VEX_W_XD) ||
143 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
145 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
146 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
147 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
149 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
151 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
153 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
154 case IC_VEX_W_OPSIZE:
155 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
157 return inheritsFrom(child, IC_VEX_L_W);
159 return inheritsFrom(child, IC_VEX_L_W_XS);
161 return inheritsFrom(child, IC_VEX_L_W_XD);
162 case IC_VEX_L_OPSIZE:
163 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
167 case IC_VEX_L_W_OPSIZE:
170 return inheritsFrom(child, IC_EVEX_W) ||
171 inheritsFrom(child, IC_EVEX_L_W);
173 return inheritsFrom(child, IC_EVEX_W_XS) ||
174 inheritsFrom(child, IC_EVEX_L_W_XS);
176 return inheritsFrom(child, IC_EVEX_W_XD) ||
177 inheritsFrom(child, IC_EVEX_L_W_XD);
179 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
180 inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
186 case IC_EVEX_W_OPSIZE:
194 case IC_EVEX_L_OPSIZE:
199 case IC_EVEX_L_W_OPSIZE:
204 case IC_EVEX_L2_OPSIZE:
207 case IC_EVEX_L2_W_XS:
208 case IC_EVEX_L2_W_XD:
209 case IC_EVEX_L2_W_OPSIZE:
212 return inheritsFrom(child, IC_EVEX_W_K) ||
213 inheritsFrom(child, IC_EVEX_L_W_K);
215 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
216 inheritsFrom(child, IC_EVEX_L_W_XS_K);
218 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
219 inheritsFrom(child, IC_EVEX_L_W_XD_K);
224 return inheritsFrom(child, IC_EVEX_W_XS_KZ) ||
225 inheritsFrom(child, IC_EVEX_L_W_XS_KZ);
227 return inheritsFrom(child, IC_EVEX_W_XD_KZ) ||
228 inheritsFrom(child, IC_EVEX_L_W_XD_KZ);
230 case IC_EVEX_OPSIZE_K:
231 case IC_EVEX_OPSIZE_B:
232 case IC_EVEX_OPSIZE_K_B:
233 case IC_EVEX_OPSIZE_KZ:
234 case IC_EVEX_OPSIZE_KZ_B:
239 case IC_EVEX_W_OPSIZE_K:
240 case IC_EVEX_W_OPSIZE_B:
241 case IC_EVEX_W_OPSIZE_K_B:
246 case IC_EVEX_L_OPSIZE_K:
247 case IC_EVEX_L_OPSIZE_B:
248 case IC_EVEX_L_OPSIZE_K_B:
251 case IC_EVEX_W_XS_KZ:
252 case IC_EVEX_W_XD_KZ:
253 case IC_EVEX_W_OPSIZE_KZ:
254 case IC_EVEX_W_OPSIZE_KZ_B:
257 case IC_EVEX_L_XS_KZ:
258 case IC_EVEX_L_XD_KZ:
259 case IC_EVEX_L_OPSIZE_KZ:
260 case IC_EVEX_L_OPSIZE_KZ_B:
263 case IC_EVEX_L_W_XS_K:
264 case IC_EVEX_L_W_XD_K:
265 case IC_EVEX_L_W_OPSIZE_K:
266 case IC_EVEX_L_W_OPSIZE_B:
267 case IC_EVEX_L_W_OPSIZE_K_B:
269 case IC_EVEX_L_W_XS_KZ:
270 case IC_EVEX_L_W_XD_KZ:
271 case IC_EVEX_L_W_OPSIZE_KZ:
272 case IC_EVEX_L_W_OPSIZE_KZ_B:
277 case IC_EVEX_L2_KZ_B:
278 case IC_EVEX_L2_XS_K:
279 case IC_EVEX_L2_XS_B:
280 case IC_EVEX_L2_XD_B:
281 case IC_EVEX_L2_XD_K:
282 case IC_EVEX_L2_OPSIZE_K:
283 case IC_EVEX_L2_OPSIZE_B:
284 case IC_EVEX_L2_OPSIZE_K_B:
286 case IC_EVEX_L2_XS_KZ:
287 case IC_EVEX_L2_XD_KZ:
288 case IC_EVEX_L2_OPSIZE_KZ:
289 case IC_EVEX_L2_OPSIZE_KZ_B:
293 case IC_EVEX_L2_W_XS_K:
294 case IC_EVEX_L2_W_XD_K:
295 case IC_EVEX_L2_W_XD_B:
296 case IC_EVEX_L2_W_OPSIZE_K:
297 case IC_EVEX_L2_W_OPSIZE_B:
298 case IC_EVEX_L2_W_OPSIZE_K_B:
299 case IC_EVEX_L2_W_KZ:
300 case IC_EVEX_L2_W_XS_KZ:
301 case IC_EVEX_L2_W_XD_KZ:
302 case IC_EVEX_L2_W_OPSIZE_KZ:
303 case IC_EVEX_L2_W_OPSIZE_KZ_B:
306 errs() << "Unknown instruction class: " <<
307 stringForContext((InstructionContext)parent) << "\n";
308 llvm_unreachable("Unknown instruction class");
312 /// outranks - Indicates whether, if an instruction has two different applicable
313 /// classes, which class should be preferred when performing decode. This
314 /// imposes a total ordering (ties are resolved toward "lower")
316 /// @param upper - The class that may be preferable
317 /// @param lower - The class that may be less preferable
318 /// @return - True if upper is to be preferred, false otherwise.
319 static inline bool outranks(InstructionContext upper,
320 InstructionContext lower) {
321 assert(upper < IC_max);
322 assert(lower < IC_max);
324 #define ENUM_ENTRY(n, r, d) r,
325 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
326 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
327 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
328 static int ranks[IC_max] = {
332 #undef ENUM_ENTRY_K_B
334 return (ranks[upper] > ranks[lower]);
337 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
338 /// be compacted by eliminating redundant information.
340 /// @param decision - The decision to be compacted.
341 /// @return - The compactest available representation for the decision.
342 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
343 bool satisfiesOneEntry = true;
344 bool satisfiesSplitRM = true;
345 bool satisfiesSplitReg = true;
346 bool satisfiesSplitMisc = true;
348 for (unsigned index = 0; index < 256; ++index) {
349 if (decision.instructionIDs[index] != decision.instructionIDs[0])
350 satisfiesOneEntry = false;
352 if (((index & 0xc0) == 0xc0) &&
353 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
354 satisfiesSplitRM = false;
356 if (((index & 0xc0) != 0xc0) &&
357 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
358 satisfiesSplitRM = false;
360 if (((index & 0xc0) == 0xc0) &&
361 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
362 satisfiesSplitReg = false;
364 if (((index & 0xc0) != 0xc0) &&
365 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
366 satisfiesSplitMisc = false;
369 if (satisfiesOneEntry)
370 return MODRM_ONEENTRY;
372 if (satisfiesSplitRM)
373 return MODRM_SPLITRM;
375 if (satisfiesSplitReg && satisfiesSplitMisc)
376 return MODRM_SPLITREG;
378 if (satisfiesSplitMisc)
379 return MODRM_SPLITMISC;
384 /// stringForDecisionType - Returns a statically-allocated string corresponding
385 /// to a particular decision type.
387 /// @param dt - The decision type.
388 /// @return - A pointer to the statically-allocated string (e.g.,
389 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
390 static const char* stringForDecisionType(ModRMDecisionType dt) {
391 #define ENUM_ENTRY(n) case n: return #n;
394 llvm_unreachable("Unknown decision type");
400 DisassemblerTables::DisassemblerTables() {
403 for (i = 0; i < array_lengthof(Tables); i++) {
404 Tables[i] = new ContextDecision;
405 memset(Tables[i], 0, sizeof(ContextDecision));
408 HasConflicts = false;
411 DisassemblerTables::~DisassemblerTables() {
414 for (i = 0; i < array_lengthof(Tables); i++)
418 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
419 unsigned &i1, unsigned &i2,
420 unsigned &ModRMTableNum,
421 ModRMDecision &decision) const {
422 static uint32_t sTableNumber = 0;
423 static uint32_t sEntryNumber = 1;
424 ModRMDecisionType dt = getDecisionType(decision);
426 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
428 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
431 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
432 o2.indent(i2) << 0 << " /* EmptyTable */\n";
435 o2.indent(i2) << "}";
439 std::vector<unsigned> ModRMDecision;
443 llvm_unreachable("Unknown decision type");
445 ModRMDecision.push_back(decision.instructionIDs[0]);
448 ModRMDecision.push_back(decision.instructionIDs[0x00]);
449 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
452 for (unsigned index = 0; index < 64; index += 8)
453 ModRMDecision.push_back(decision.instructionIDs[index]);
454 for (unsigned index = 0xc0; index < 256; index += 8)
455 ModRMDecision.push_back(decision.instructionIDs[index]);
457 case MODRM_SPLITMISC:
458 for (unsigned index = 0; index < 64; index += 8)
459 ModRMDecision.push_back(decision.instructionIDs[index]);
460 for (unsigned index = 0xc0; index < 256; ++index)
461 ModRMDecision.push_back(decision.instructionIDs[index]);
464 for (unsigned index = 0; index < 256; ++index)
465 ModRMDecision.push_back(decision.instructionIDs[index]);
469 unsigned &EntryNumber = ModRMTable[ModRMDecision];
470 if (EntryNumber == 0) {
471 EntryNumber = ModRMTableNum;
473 ModRMTableNum += ModRMDecision.size();
474 o1 << "/* Table" << EntryNumber << " */\n";
476 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
477 E = ModRMDecision.end(); I != E; ++I) {
478 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
479 << InstructionSpecifiers[*I].name << " */\n";
484 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
487 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
488 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
491 o2.indent(i2) << "}";
495 llvm_unreachable("Unknown decision type");
505 case MODRM_SPLITMISC:
506 sEntryNumber += 8 + 64;
513 // We assume that the index can fit into uint16_t.
514 assert(sEntryNumber < 65536U &&
515 "Index into ModRMDecision is too large for uint16_t!");
520 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
521 unsigned &i1, unsigned &i2,
522 unsigned &ModRMTableNum,
523 OpcodeDecision &decision) const {
524 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
526 o2.indent(i2) << "{" << "\n";
529 for (unsigned index = 0; index < 256; ++index) {
532 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
534 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
535 decision.modRMDecisions[index]);
544 o2.indent(i2) << "}" << "\n";
546 o2.indent(i2) << "}" << "\n";
549 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
550 unsigned &i1, unsigned &i2,
551 unsigned &ModRMTableNum,
552 ContextDecision &decision,
553 const char* name) const {
554 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
556 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
559 for (unsigned index = 0; index < IC_max; ++index) {
560 o2.indent(i2) << "/* ";
561 o2 << stringForContext((InstructionContext)index);
565 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
566 decision.opcodeDecisions[index]);
568 if (index + 1 < IC_max)
573 o2.indent(i2) << "}" << "\n";
575 o2.indent(i2) << "};" << "\n";
578 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
580 unsigned NumInstructions = InstructionSpecifiers.size();
582 o << "static const struct OperandSpecifier x86OperandSets[]["
583 << X86_MAX_OPERANDS << "] = {\n";
585 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
586 std::map<OperandListTy, unsigned> OperandSets;
588 unsigned OperandSetNum = 0;
589 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
590 OperandListTy OperandList;
592 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
594 const char *Encoding =
595 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
596 .operands[OperandIndex].encoding);
598 stringForOperandType((OperandType)InstructionSpecifiers[Index]
599 .operands[OperandIndex].type);
600 OperandList.push_back(std::make_pair(Encoding, Type));
602 unsigned &N = OperandSets[OperandList];
603 if (N != 0) continue;
607 o << " { /* " << (OperandSetNum - 1) << " */\n";
608 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
609 o << " { " << OperandList[i].first << ", "
610 << OperandList[i].second << " },\n";
616 o.indent(i * 2) << "static const struct InstructionSpecifier ";
617 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
621 for (unsigned index = 0; index < NumInstructions; ++index) {
622 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
625 OperandListTy OperandList;
626 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
628 const char *Encoding =
629 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
630 .operands[OperandIndex].encoding);
632 stringForOperandType((OperandType)InstructionSpecifiers[index]
633 .operands[OperandIndex].type);
634 OperandList.push_back(std::make_pair(Encoding, Type));
636 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
638 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
642 o.indent(i * 2) << "}";
644 if (index + 1 < NumInstructions)
651 o.indent(i * 2) << "};" << "\n";
654 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
655 const unsigned int tableSize = 16384;
656 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
657 "[" << tableSize << "] = {\n";
660 for (unsigned index = 0; index < tableSize; ++index) {
663 if (index & ATTR_EVEX) {
665 if (index & ATTR_EVEXL2)
667 else if (index & ATTR_EVEXL)
669 if (index & ATTR_REXW)
671 if (index & ATTR_OPSIZE)
673 else if (index & ATTR_XD)
675 else if (index & ATTR_XS)
677 if (index & ATTR_EVEXKZ)
679 else if (index & ATTR_EVEXK)
681 if (index & ATTR_EVEXB)
684 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
685 o << "IC_VEX_L_W_OPSIZE";
686 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
687 o << "IC_VEX_L_W_XD";
688 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
689 o << "IC_VEX_L_W_XS";
690 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
692 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
693 o << "IC_VEX_L_OPSIZE";
694 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
696 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
698 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
699 o << "IC_VEX_W_OPSIZE";
700 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
702 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
704 else if (index & ATTR_VEXL)
706 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
708 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
709 o << "IC_VEX_OPSIZE";
710 else if ((index & ATTR_VEX) && (index & ATTR_XD))
712 else if ((index & ATTR_VEX) && (index & ATTR_XS))
714 else if (index & ATTR_VEX)
716 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
717 o << "IC_64BIT_REXW_XS";
718 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
719 o << "IC_64BIT_REXW_XD";
720 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
721 (index & ATTR_OPSIZE))
722 o << "IC_64BIT_REXW_OPSIZE";
723 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
724 o << "IC_64BIT_XD_OPSIZE";
725 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
726 o << "IC_64BIT_XS_OPSIZE";
727 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
729 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
731 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE) &&
732 (index & ATTR_ADSIZE))
733 o << "IC_64BIT_OPSIZE_ADSIZE";
734 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
735 o << "IC_64BIT_OPSIZE";
736 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
737 o << "IC_64BIT_ADSIZE";
738 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
739 o << "IC_64BIT_REXW";
740 else if ((index & ATTR_64BIT))
742 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
744 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
746 else if (index & ATTR_XS)
748 else if (index & ATTR_XD)
750 else if ((index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
751 o << "IC_OPSIZE_ADSIZE";
752 else if (index & ATTR_OPSIZE)
754 else if (index & ATTR_ADSIZE)
759 if (index < tableSize - 1)
764 o << " /* " << index << " */";
770 o.indent(i * 2) << "};" << "\n";
773 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
774 unsigned &i1, unsigned &i2,
775 unsigned &ModRMTableNum) const {
776 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
777 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
778 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
779 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
780 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR);
781 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR);
782 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR);
785 void DisassemblerTables::emit(raw_ostream &o) const {
792 raw_string_ostream o1(s1);
793 raw_string_ostream o2(s2);
795 emitInstructionInfo(o, i2);
798 emitContextTable(o, i2);
801 unsigned ModRMTableNum = 0;
803 o << "static const InstrUID modRMTable[] = {\n";
805 std::vector<unsigned> EmptyTable(1, 0);
806 ModRMTable[EmptyTable] = ModRMTableNum;
807 ModRMTableNum += EmptyTable.size();
808 o1 << "/* EmptyTable */\n";
809 o1.indent(i1 * 2) << "0x0,\n";
811 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
822 void DisassemblerTables::setTableFields(ModRMDecision &decision,
823 const ModRMFilter &filter,
826 for (unsigned index = 0; index < 256; ++index) {
827 if (filter.accepts(index)) {
828 if (decision.instructionIDs[index] == uid)
831 if (decision.instructionIDs[index] != 0) {
832 InstructionSpecifier &newInfo =
833 InstructionSpecifiers[uid];
834 InstructionSpecifier &previousInfo =
835 InstructionSpecifiers[decision.instructionIDs[index]];
837 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
838 newInfo.name == "XCHG32ar" ||
839 newInfo.name == "XCHG32ar64" ||
840 newInfo.name == "XCHG64ar"))
841 continue; // special case for XCHG*ar and NOOP
843 if (outranks(previousInfo.insnContext, newInfo.insnContext))
846 if (previousInfo.insnContext == newInfo.insnContext) {
847 errs() << "Error: Primary decode conflict: ";
848 errs() << newInfo.name << " would overwrite " << previousInfo.name;
850 errs() << "ModRM " << index << "\n";
851 errs() << "Opcode " << (uint16_t)opcode << "\n";
852 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
857 decision.instructionIDs[index] = uid;
862 void DisassemblerTables::setTableFields(OpcodeType type,
863 InstructionContext insnContext,
865 const ModRMFilter &filter,
869 unsigned addressSize) {
870 ContextDecision &decision = *Tables[type];
872 for (unsigned index = 0; index < IC_max; ++index) {
873 if ((is32bit || addressSize == 16) &&
874 inheritsFrom((InstructionContext)index, IC_64BIT))
877 bool adSize64 = addressSize == 64;
878 if (inheritsFrom((InstructionContext)index,
879 InstructionSpecifiers[uid].insnContext, ignoresVEX_L,
881 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],