1 //===- DAGISelMatcherGen.cpp - Matcher generator --------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "DAGISelMatcher.h"
11 #include "CodeGenDAGPatterns.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/ADT/StringMap.h"
19 /// getRegisterValueType - Look up and return the ValueType of the specified
20 /// register. If the register is a member of multiple register classes which
21 /// have different associated types, return MVT::Other.
22 static MVT::SimpleValueType getRegisterValueType(Record *R,
23 const CodeGenTarget &T) {
25 MVT::SimpleValueType VT = MVT::Other;
26 const std::vector<CodeGenRegisterClass> &RCs = T.getRegisterClasses();
27 std::vector<Record*>::const_iterator Element;
29 for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) {
30 const CodeGenRegisterClass &RC = RCs[rc];
31 if (!std::count(RC.Elements.begin(), RC.Elements.end(), R))
36 VT = RC.getValueTypeNum(0);
40 // If this occurs in multiple register classes, they all have to agree.
41 assert(VT == RC.getValueTypeNum(0));
49 const PatternToMatch &Pattern;
50 const CodeGenDAGPatterns &CGP;
52 /// PatWithNoTypes - This is a clone of Pattern.getSrcPattern() that starts
53 /// out with all of the types removed. This allows us to insert type checks
54 /// as we scan the tree.
55 TreePatternNode *PatWithNoTypes;
57 /// VariableMap - A map from variable names ('$dst') to the recorded operand
58 /// number that they were captured as. These are biased by 1 to make
60 StringMap<unsigned> VariableMap;
62 /// NextRecordedOperandNo - As we emit opcodes to record matched values in
63 /// the RecordedNodes array, this keeps track of which slot will be next to
65 unsigned NextRecordedOperandNo;
67 /// MatchedChainNodes - This maintains the position in the recorded nodes
68 /// array of all of the recorded input nodes that have chains.
69 SmallVector<unsigned, 2> MatchedChainNodes;
71 /// MatchedFlagResultNodes - This maintains the position in the recorded
72 /// nodes array of all of the recorded input nodes that have flag results.
73 SmallVector<unsigned, 2> MatchedFlagResultNodes;
75 /// MatchedComplexPatterns - This maintains a list of all of the
76 /// ComplexPatterns that we need to check. The patterns are known to have
77 /// names which were recorded. The second element of each pair is the first
78 /// slot number that the OPC_CheckComplexPat opcode drops the matched
80 SmallVector<std::pair<const TreePatternNode*,
81 unsigned>, 2> MatchedComplexPatterns;
83 /// PhysRegInputs - List list has an entry for each explicitly specified
84 /// physreg input to the pattern. The first elt is the Register node, the
85 /// second is the recorded slot number the input pattern match saved it in.
86 SmallVector<std::pair<Record*, unsigned>, 2> PhysRegInputs;
88 /// Matcher - This is the top level of the generated matcher, the result.
91 /// CurPredicate - As we emit matcher nodes, this points to the latest check
92 /// which should have future checks stuck into its Next position.
93 Matcher *CurPredicate;
95 MatcherGen(const PatternToMatch &pattern, const CodeGenDAGPatterns &cgp);
98 delete PatWithNoTypes;
101 bool EmitMatcherCode(unsigned Variant);
102 void EmitResultCode();
104 Matcher *GetMatcher() const { return TheMatcher; }
105 Matcher *GetCurPredicate() const { return CurPredicate; }
107 void AddMatcher(Matcher *NewNode);
108 void InferPossibleTypes();
110 // Matcher Generation.
111 void EmitMatchCode(const TreePatternNode *N, TreePatternNode *NodeNoTypes);
112 void EmitLeafMatchCode(const TreePatternNode *N);
113 void EmitOperatorMatchCode(const TreePatternNode *N,
114 TreePatternNode *NodeNoTypes);
116 // Result Code Generation.
117 unsigned getNamedArgumentSlot(StringRef Name) {
118 unsigned VarMapEntry = VariableMap[Name];
119 assert(VarMapEntry != 0 &&
120 "Variable referenced but not defined and not caught earlier!");
121 return VarMapEntry-1;
124 /// GetInstPatternNode - Get the pattern for an instruction.
125 const TreePatternNode *GetInstPatternNode(const DAGInstruction &Ins,
126 const TreePatternNode *N);
128 void EmitResultOperand(const TreePatternNode *N,
129 SmallVectorImpl<unsigned> &ResultOps);
130 void EmitResultOfNamedOperand(const TreePatternNode *N,
131 SmallVectorImpl<unsigned> &ResultOps);
132 void EmitResultLeafAsOperand(const TreePatternNode *N,
133 SmallVectorImpl<unsigned> &ResultOps);
134 void EmitResultInstructionAsOperand(const TreePatternNode *N,
135 SmallVectorImpl<unsigned> &ResultOps);
136 void EmitResultSDNodeXFormAsOperand(const TreePatternNode *N,
137 SmallVectorImpl<unsigned> &ResultOps);
140 } // end anon namespace.
142 MatcherGen::MatcherGen(const PatternToMatch &pattern,
143 const CodeGenDAGPatterns &cgp)
144 : Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0),
145 TheMatcher(0), CurPredicate(0) {
146 // We need to produce the matcher tree for the patterns source pattern. To do
147 // this we need to match the structure as well as the types. To do the type
148 // matching, we want to figure out the fewest number of type checks we need to
149 // emit. For example, if there is only one integer type supported by a
150 // target, there should be no type comparisons at all for integer patterns!
152 // To figure out the fewest number of type checks needed, clone the pattern,
153 // remove the types, then perform type inference on the pattern as a whole.
154 // If there are unresolved types, emit an explicit check for those types,
155 // apply the type to the tree, then rerun type inference. Iterate until all
156 // types are resolved.
158 PatWithNoTypes = Pattern.getSrcPattern()->clone();
159 PatWithNoTypes->RemoveAllTypes();
161 // If there are types that are manifestly known, infer them.
162 InferPossibleTypes();
165 /// InferPossibleTypes - As we emit the pattern, we end up generating type
166 /// checks and applying them to the 'PatWithNoTypes' tree. As we do this, we
167 /// want to propagate implied types as far throughout the tree as possible so
168 /// that we avoid doing redundant type checks. This does the type propagation.
169 void MatcherGen::InferPossibleTypes() {
170 // TP - Get *SOME* tree pattern, we don't care which. It is only used for
171 // diagnostics, which we know are impossible at this point.
172 TreePattern &TP = *CGP.pf_begin()->second;
175 bool MadeChange = true;
177 MadeChange = PatWithNoTypes->ApplyTypeConstraints(TP,
178 true/*Ignore reg constraints*/);
180 errs() << "Type constraint application shouldn't fail!";
186 /// AddMatcher - Add a matcher node to the current graph we're building.
187 void MatcherGen::AddMatcher(Matcher *NewNode) {
188 if (CurPredicate != 0)
189 CurPredicate->setNext(NewNode);
191 TheMatcher = NewNode;
192 CurPredicate = NewNode;
196 //===----------------------------------------------------------------------===//
197 // Pattern Match Generation
198 //===----------------------------------------------------------------------===//
200 /// EmitLeafMatchCode - Generate matching code for leaf nodes.
201 void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) {
202 assert(N->isLeaf() && "Not a leaf?");
204 // If there are node predicates for this node, generate their checks.
205 for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i)
206 AddMatcher(new CheckPredicateMatcher(N->getPredicateFns()[i]));
208 // Direct match against an integer constant.
209 if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
210 // If this is the root of the dag we're matching, we emit a redundant opcode
211 // check to ensure that this gets folded into the normal top-level
213 if (N == Pattern.getSrcPattern()) {
214 const SDNodeInfo &NI = CGP.getSDNodeInfo(CGP.getSDNodeNamed("imm"));
215 AddMatcher(new CheckOpcodeMatcher(NI));
218 return AddMatcher(new CheckIntegerMatcher(II->getValue()));
221 DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue());
223 errs() << "Unknown leaf kind: " << *DI << "\n";
227 Record *LeafRec = DI->getDef();
228 if (// Handle register references. Nothing to do here, they always match.
229 LeafRec->isSubClassOf("RegisterClass") ||
230 LeafRec->isSubClassOf("PointerLikeRegClass") ||
231 // Place holder for SRCVALUE nodes. Nothing to do here.
232 LeafRec->getName() == "srcvalue")
235 // If we have a physreg reference like (mul gpr:$src, EAX) then we need to
236 // record the register
237 if (LeafRec->isSubClassOf("Register")) {
238 AddMatcher(new RecordMatcher("physreg input "+LeafRec->getName(),
239 NextRecordedOperandNo));
240 PhysRegInputs.push_back(std::make_pair(LeafRec, NextRecordedOperandNo++));
244 if (LeafRec->isSubClassOf("ValueType"))
245 return AddMatcher(new CheckValueTypeMatcher(LeafRec->getName()));
247 if (LeafRec->isSubClassOf("CondCode"))
248 return AddMatcher(new CheckCondCodeMatcher(LeafRec->getName()));
250 if (LeafRec->isSubClassOf("ComplexPattern")) {
251 // We can't model ComplexPattern uses that don't have their name taken yet.
252 // The OPC_CheckComplexPattern operation implicitly records the results.
253 if (N->getName().empty()) {
254 errs() << "We expect complex pattern uses to have names: " << *N << "\n";
258 // Remember this ComplexPattern so that we can emit it after all the other
259 // structural matches are done.
260 MatchedComplexPatterns.push_back(std::make_pair(N, 0));
264 errs() << "Unknown leaf kind: " << *N << "\n";
268 void MatcherGen::EmitOperatorMatchCode(const TreePatternNode *N,
269 TreePatternNode *NodeNoTypes) {
270 assert(!N->isLeaf() && "Not an operator?");
271 const SDNodeInfo &CInfo = CGP.getSDNodeInfo(N->getOperator());
273 // If this is an 'and R, 1234' where the operation is AND/OR and the RHS is
274 // a constant without a predicate fn that has more that one bit set, handle
275 // this as a special case. This is usually for targets that have special
276 // handling of certain large constants (e.g. alpha with it's 8/16/32-bit
277 // handling stuff). Using these instructions is often far more efficient
278 // than materializing the constant. Unfortunately, both the instcombiner
279 // and the dag combiner can often infer that bits are dead, and thus drop
280 // them from the mask in the dag. For example, it might turn 'AND X, 255'
281 // into 'AND X, 254' if it knows the low bit is set. Emit code that checks
283 if ((N->getOperator()->getName() == "and" ||
284 N->getOperator()->getName() == "or") &&
285 N->getChild(1)->isLeaf() && N->getChild(1)->getPredicateFns().empty() &&
286 N->getPredicateFns().empty()) {
287 if (IntInit *II = dynamic_cast<IntInit*>(N->getChild(1)->getLeafValue())) {
288 if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits.
289 // If this is at the root of the pattern, we emit a redundant
290 // CheckOpcode so that the following checks get factored properly under
291 // a single opcode check.
292 if (N == Pattern.getSrcPattern())
293 AddMatcher(new CheckOpcodeMatcher(CInfo));
295 // Emit the CheckAndImm/CheckOrImm node.
296 if (N->getOperator()->getName() == "and")
297 AddMatcher(new CheckAndImmMatcher(II->getValue()));
299 AddMatcher(new CheckOrImmMatcher(II->getValue()));
301 // Match the LHS of the AND as appropriate.
302 AddMatcher(new MoveChildMatcher(0));
303 EmitMatchCode(N->getChild(0), NodeNoTypes->getChild(0));
304 AddMatcher(new MoveParentMatcher());
310 // Check that the current opcode lines up.
311 AddMatcher(new CheckOpcodeMatcher(CInfo));
313 // If there are node predicates for this node, generate their checks.
314 for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i)
315 AddMatcher(new CheckPredicateMatcher(N->getPredicateFns()[i]));
318 // If this node has memory references (i.e. is a load or store), tell the
319 // interpreter to capture them in the memref array.
320 if (N->NodeHasProperty(SDNPMemOperand, CGP))
321 AddMatcher(new RecordMemRefMatcher());
323 // If this node has a chain, then the chain is operand #0 is the SDNode, and
324 // the child numbers of the node are all offset by one.
326 if (N->NodeHasProperty(SDNPHasChain, CGP)) {
327 // Record the node and remember it in our chained nodes list.
328 AddMatcher(new RecordMatcher("'" + N->getOperator()->getName() +
330 NextRecordedOperandNo));
331 // Remember all of the input chains our pattern will match.
332 MatchedChainNodes.push_back(NextRecordedOperandNo++);
334 // Don't look at the input chain when matching the tree pattern to the
338 // If this node is not the root and the subtree underneath it produces a
339 // chain, then the result of matching the node is also produce a chain.
340 // Beyond that, this means that we're also folding (at least) the root node
341 // into the node that produce the chain (for example, matching
342 // "(add reg, (load ptr))" as a add_with_memory on X86). This is
343 // problematic, if the 'reg' node also uses the load (say, its chain).
348 // | \ DAG's like cheese.
354 // It would be invalid to fold XX and LD. In this case, folding the two
355 // nodes together would induce a cycle in the DAG, making it a 'cyclic DAG'
356 // To prevent this, we emit a dynamic check for legality before allowing
357 // this to be folded.
359 const TreePatternNode *Root = Pattern.getSrcPattern();
360 if (N != Root) { // Not the root of the pattern.
361 // If there is a node between the root and this node, then we definitely
362 // need to emit the check.
363 bool NeedCheck = !Root->hasChild(N);
365 // If it *is* an immediate child of the root, we can still need a check if
366 // the root SDNode has multiple inputs. For us, this means that it is an
367 // intrinsic, has multiple operands, or has other inputs like chain or
370 const SDNodeInfo &PInfo = CGP.getSDNodeInfo(Root->getOperator());
372 Root->getOperator() == CGP.get_intrinsic_void_sdnode() ||
373 Root->getOperator() == CGP.get_intrinsic_w_chain_sdnode() ||
374 Root->getOperator() == CGP.get_intrinsic_wo_chain_sdnode() ||
375 PInfo.getNumOperands() > 1 ||
376 PInfo.hasProperty(SDNPHasChain) ||
377 PInfo.hasProperty(SDNPInFlag) ||
378 PInfo.hasProperty(SDNPOptInFlag);
382 AddMatcher(new CheckFoldableChainNodeMatcher());
386 // If this node has an output flag and isn't the root, remember it.
387 if (N->NodeHasProperty(SDNPOutFlag, CGP) &&
388 N != Pattern.getSrcPattern()) {
389 // TODO: This redundantly records nodes with both flags and chains.
391 // Record the node and remember it in our chained nodes list.
392 AddMatcher(new RecordMatcher("'" + N->getOperator()->getName() +
393 "' flag output node",
394 NextRecordedOperandNo));
395 // Remember all of the nodes with output flags our pattern will match.
396 MatchedFlagResultNodes.push_back(NextRecordedOperandNo++);
399 // If this node is known to have an input flag or if it *might* have an input
400 // flag, capture it as the flag input of the pattern.
401 if (N->NodeHasProperty(SDNPOptInFlag, CGP) ||
402 N->NodeHasProperty(SDNPInFlag, CGP))
403 AddMatcher(new CaptureFlagInputMatcher());
405 for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
406 // Get the code suitable for matching this child. Move to the child, check
407 // it then move back to the parent.
408 AddMatcher(new MoveChildMatcher(OpNo));
409 EmitMatchCode(N->getChild(i), NodeNoTypes->getChild(i));
410 AddMatcher(new MoveParentMatcher());
415 void MatcherGen::EmitMatchCode(const TreePatternNode *N,
416 TreePatternNode *NodeNoTypes) {
417 // If N and NodeNoTypes don't agree on a type, then this is a case where we
418 // need to do a type check. Emit the check, apply the tyep to NodeNoTypes and
419 // reinfer any correlated types.
420 unsigned NodeType = EEVT::isUnknown;
421 if (NodeNoTypes->getExtTypes() != N->getExtTypes()) {
422 NodeType = N->getTypeNum(0);
423 NodeNoTypes->setTypes(N->getExtTypes());
424 InferPossibleTypes();
427 // If this node has a name associated with it, capture it in VariableMap. If
428 // we already saw this in the pattern, emit code to verify dagness.
429 if (!N->getName().empty()) {
430 unsigned &VarMapEntry = VariableMap[N->getName()];
431 if (VarMapEntry == 0) {
432 // If it is a named node, we must emit a 'Record' opcode.
433 AddMatcher(new RecordMatcher("$" + N->getName(), NextRecordedOperandNo));
434 VarMapEntry = ++NextRecordedOperandNo;
436 // If we get here, this is a second reference to a specific name. Since
437 // we already have checked that the first reference is valid, we don't
438 // have to recursively match it, just check that it's the same as the
439 // previously named thing.
440 AddMatcher(new CheckSameMatcher(VarMapEntry-1));
446 EmitLeafMatchCode(N);
448 EmitOperatorMatchCode(N, NodeNoTypes);
450 if (NodeType != EEVT::isUnknown)
451 AddMatcher(new CheckTypeMatcher((MVT::SimpleValueType)NodeType));
455 /// EmitMatcherCode - Generate the code that matches the predicate of this
456 /// pattern for the specified Variant. If the variant is invalid this returns
457 /// true and does not generate code, if it is valid, it returns false.
458 bool MatcherGen::EmitMatcherCode(unsigned Variant) {
459 // If the root of the pattern is a ComplexPattern and if it is specified to
460 // match some number of root opcodes, these are considered to be our variants.
461 // Depending on which variant we're generating code for, emit the root opcode
463 if (const ComplexPattern *CP =
464 Pattern.getSrcPattern()->getComplexPatternInfo(CGP)) {
465 const std::vector<Record*> &OpNodes = CP->getRootNodes();
466 assert(!OpNodes.empty() &&"Complex Pattern must specify what it can match");
467 if (Variant >= OpNodes.size()) return true;
469 AddMatcher(new CheckOpcodeMatcher(CGP.getSDNodeInfo(OpNodes[Variant])));
471 if (Variant != 0) return true;
474 // Emit the matcher for the pattern structure and types.
475 EmitMatchCode(Pattern.getSrcPattern(), PatWithNoTypes);
477 // If the pattern has a predicate on it (e.g. only enabled when a subtarget
478 // feature is around, do the check).
479 // FIXME: This should get emitted after the match code below to encourage
480 // sharing. This can't happen until we get an X86ISD::AddrMode node made by
481 // dag combine, eliminating the horrible side-effect-full stuff from
482 // X86's MatchAddress.
483 if (!Pattern.getPredicateCheck().empty())
484 AddMatcher(new CheckPatternPredicateMatcher(Pattern.getPredicateCheck()));
486 // Now that we've completed the structural type match, emit any ComplexPattern
487 // checks (e.g. addrmode matches). We emit this after the structural match
488 // because they are generally more expensive to evaluate and more difficult to
490 for (unsigned i = 0, e = MatchedComplexPatterns.size(); i != e; ++i) {
491 const TreePatternNode *N = MatchedComplexPatterns[i].first;
493 // Remember where the results of this match get stuck.
494 MatchedComplexPatterns[i].second = NextRecordedOperandNo;
496 // Get the slot we recorded the value in from the name on the node.
497 unsigned RecNodeEntry = VariableMap[N->getName()];
498 assert(!N->getName().empty() && RecNodeEntry &&
499 "Complex pattern should have a name and slot");
500 --RecNodeEntry; // Entries in VariableMap are biased.
502 const ComplexPattern &CP =
503 CGP.getComplexPattern(((DefInit*)N->getLeafValue())->getDef());
505 // Emit a CheckComplexPat operation, which does the match (aborting if it
506 // fails) and pushes the matched operands onto the recorded nodes list.
507 AddMatcher(new CheckComplexPatMatcher(CP, RecNodeEntry,
508 N->getName(), NextRecordedOperandNo));
510 // Record the right number of operands.
511 NextRecordedOperandNo += CP.getNumOperands();
512 if (CP.hasProperty(SDNPHasChain)) {
513 // If the complex pattern has a chain, then we need to keep track of the
514 // fact that we just recorded a chain input. The chain input will be
515 // matched as the last operand of the predicate if it was successful.
516 ++NextRecordedOperandNo; // Chained node operand.
518 // It is the last operand recorded.
519 assert(NextRecordedOperandNo > 1 &&
520 "Should have recorded input/result chains at least!");
521 MatchedChainNodes.push_back(NextRecordedOperandNo-1);
524 // TODO: Complex patterns can't have output flags, if they did, we'd want
532 //===----------------------------------------------------------------------===//
533 // Node Result Generation
534 //===----------------------------------------------------------------------===//
536 void MatcherGen::EmitResultOfNamedOperand(const TreePatternNode *N,
537 SmallVectorImpl<unsigned> &ResultOps){
538 assert(!N->getName().empty() && "Operand not named!");
540 // A reference to a complex pattern gets all of the results of the complex
542 if (const ComplexPattern *CP = N->getComplexPatternInfo(CGP)) {
544 for (unsigned i = 0, e = MatchedComplexPatterns.size(); i != e; ++i)
545 if (MatchedComplexPatterns[i].first->getName() == N->getName()) {
546 SlotNo = MatchedComplexPatterns[i].second;
549 assert(SlotNo != 0 && "Didn't get a slot number assigned?");
551 // The first slot entry is the node itself, the subsequent entries are the
553 for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i)
554 ResultOps.push_back(SlotNo+i);
558 unsigned SlotNo = getNamedArgumentSlot(N->getName());
560 // If this is an 'imm' or 'fpimm' node, make sure to convert it to the target
561 // version of the immediate so that it doesn't get selected due to some other
564 StringRef OperatorName = N->getOperator()->getName();
565 if (OperatorName == "imm" || OperatorName == "fpimm") {
566 AddMatcher(new EmitConvertToTargetMatcher(SlotNo));
567 ResultOps.push_back(NextRecordedOperandNo++);
572 ResultOps.push_back(SlotNo);
575 void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N,
576 SmallVectorImpl<unsigned> &ResultOps) {
577 assert(N->isLeaf() && "Must be a leaf");
579 if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
580 AddMatcher(new EmitIntegerMatcher(II->getValue(),N->getTypeNum(0)));
581 ResultOps.push_back(NextRecordedOperandNo++);
585 // If this is an explicit register reference, handle it.
586 if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
587 if (DI->getDef()->isSubClassOf("Register")) {
588 AddMatcher(new EmitRegisterMatcher(DI->getDef(),
590 ResultOps.push_back(NextRecordedOperandNo++);
594 if (DI->getDef()->getName() == "zero_reg") {
595 AddMatcher(new EmitRegisterMatcher(0, N->getTypeNum(0)));
596 ResultOps.push_back(NextRecordedOperandNo++);
600 // Handle a reference to a register class. This is used
601 // in COPY_TO_SUBREG instructions.
602 if (DI->getDef()->isSubClassOf("RegisterClass")) {
603 std::string Value = getQualifiedName(DI->getDef()) + "RegClassID";
604 AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
605 ResultOps.push_back(NextRecordedOperandNo++);
610 errs() << "unhandled leaf node: \n";
614 /// GetInstPatternNode - Get the pattern for an instruction.
616 const TreePatternNode *MatcherGen::
617 GetInstPatternNode(const DAGInstruction &Inst, const TreePatternNode *N) {
618 const TreePattern *InstPat = Inst.getPattern();
620 // FIXME2?: Assume actual pattern comes before "implicit".
621 TreePatternNode *InstPatNode;
623 InstPatNode = InstPat->getTree(0);
624 else if (/*isRoot*/ N == Pattern.getDstPattern())
625 InstPatNode = Pattern.getSrcPattern();
629 if (InstPatNode && !InstPatNode->isLeaf() &&
630 InstPatNode->getOperator()->getName() == "set")
631 InstPatNode = InstPatNode->getChild(InstPatNode->getNumChildren()-1);
637 EmitResultInstructionAsOperand(const TreePatternNode *N,
638 SmallVectorImpl<unsigned> &OutputOps) {
639 Record *Op = N->getOperator();
640 const CodeGenTarget &CGT = CGP.getTargetInfo();
641 CodeGenInstruction &II = CGT.getInstruction(Op->getName());
642 const DAGInstruction &Inst = CGP.getInstruction(Op);
644 // If we can, get the pattern for the instruction we're generating. We derive
645 // a variety of information from this pattern, such as whether it has a chain.
647 // FIXME2: This is extremely dubious for several reasons, not the least of
648 // which it gives special status to instructions with patterns that Pat<>
649 // nodes can't duplicate.
650 const TreePatternNode *InstPatNode = GetInstPatternNode(Inst, N);
652 // NodeHasChain - Whether the instruction node we're creating takes chains.
653 bool NodeHasChain = InstPatNode &&
654 InstPatNode->TreeHasProperty(SDNPHasChain, CGP);
656 bool isRoot = N == Pattern.getDstPattern();
658 // TreeHasOutFlag - True if this tree has a flag.
659 bool TreeHasInFlag = false, TreeHasOutFlag = false;
661 const TreePatternNode *SrcPat = Pattern.getSrcPattern();
662 TreeHasInFlag = SrcPat->TreeHasProperty(SDNPOptInFlag, CGP) ||
663 SrcPat->TreeHasProperty(SDNPInFlag, CGP);
665 // FIXME2: this is checking the entire pattern, not just the node in
666 // question, doing this just for the root seems like a total hack.
667 TreeHasOutFlag = SrcPat->TreeHasProperty(SDNPOutFlag, CGP);
670 // NumResults - This is the number of results produced by the instruction in
672 unsigned NumResults = Inst.getNumResults();
674 // Loop over all of the operands of the instruction pattern, emitting code
675 // to fill them all in. The node 'N' usually has number children equal to
676 // the number of input operands of the instruction. However, in cases
677 // where there are predicate operands for an instruction, we need to fill
678 // in the 'execute always' values. Match up the node operands to the
679 // instruction operands to do this.
680 SmallVector<unsigned, 8> InstOps;
681 for (unsigned ChildNo = 0, InstOpNo = NumResults, e = II.OperandList.size();
682 InstOpNo != e; ++InstOpNo) {
684 // Determine what to emit for this operand.
685 Record *OperandNode = II.OperandList[InstOpNo].Rec;
686 if ((OperandNode->isSubClassOf("PredicateOperand") ||
687 OperandNode->isSubClassOf("OptionalDefOperand")) &&
688 !CGP.getDefaultOperand(OperandNode).DefaultOps.empty()) {
689 // This is a predicate or optional def operand; emit the
690 // 'default ops' operands.
691 const DAGDefaultOperand &DefaultOp =
692 CGP.getDefaultOperand(II.OperandList[InstOpNo].Rec);
693 for (unsigned i = 0, e = DefaultOp.DefaultOps.size(); i != e; ++i)
694 EmitResultOperand(DefaultOp.DefaultOps[i], InstOps);
698 // Otherwise this is a normal operand or a predicate operand without
699 // 'execute always'; emit it.
700 EmitResultOperand(N->getChild(ChildNo), InstOps);
704 // If this node has an input flag or explicitly specified input physregs, we
705 // need to add chained and flagged copyfromreg nodes and materialize the flag
707 if (isRoot && !PhysRegInputs.empty()) {
708 // Emit all of the CopyToReg nodes for the input physical registers. These
709 // occur in patterns like (mul:i8 AL:i8, GR8:i8:$src).
710 for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i)
711 AddMatcher(new EmitCopyToRegMatcher(PhysRegInputs[i].second,
712 PhysRegInputs[i].first));
713 // Even if the node has no other flag inputs, the resultant node must be
714 // flagged to the CopyFromReg nodes we just generated.
715 TreeHasInFlag = true;
718 // Result order: node results, chain, flags
720 // Determine the result types.
721 SmallVector<MVT::SimpleValueType, 4> ResultVTs;
722 if (NumResults != 0 && N->getTypeNum(0) != MVT::isVoid) {
723 // FIXME2: If the node has multiple results, we should add them. For now,
724 // preserve existing behavior?!
725 ResultVTs.push_back(N->getTypeNum(0));
729 // If this is the root instruction of a pattern that has physical registers in
730 // its result pattern, add output VTs for them. For example, X86 has:
731 // (set AL, (mul ...))
732 // This also handles implicit results like:
734 if (isRoot && Pattern.getDstRegs().size() != 0) {
735 for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i)
736 if (Pattern.getDstRegs()[i]->isSubClassOf("Register"))
737 ResultVTs.push_back(getRegisterValueType(Pattern.getDstRegs()[i], CGT));
740 // FIXME2: Instead of using the isVariadic flag on the instruction, we should
741 // have an SDNP that indicates variadicism. The TargetInstrInfo isVariadic
742 // property should be inferred from this when an instruction has a pattern.
743 int NumFixedArityOperands = -1;
744 if (isRoot && II.isVariadic)
745 NumFixedArityOperands = Pattern.getSrcPattern()->getNumChildren();
747 // If this is the root node and any of the nodes matched nodes in the input
748 // pattern have MemRefs in them, have the interpreter collect them and plop
749 // them onto this node.
751 // FIXME3: This is actively incorrect for result patterns where the root of
752 // the pattern is not the memory reference and is also incorrect when the
753 // result pattern has multiple memory-referencing instructions. For example,
754 // in the X86 backend, this pattern causes the memrefs to get attached to the
755 // CVTSS2SDrr instead of the MOVSSrm:
757 // def : Pat<(extloadf32 addr:$src),
758 // (CVTSS2SDrr (MOVSSrm addr:$src))>;
760 bool NodeHasMemRefs =
761 isRoot && Pattern.getSrcPattern()->TreeHasProperty(SDNPMemOperand, CGP);
763 AddMatcher(new EmitNodeMatcher(II.Namespace+"::"+II.TheDef->getName(),
764 ResultVTs.data(), ResultVTs.size(),
765 InstOps.data(), InstOps.size(),
766 NodeHasChain, TreeHasInFlag, TreeHasOutFlag,
767 NodeHasMemRefs, NumFixedArityOperands,
768 NextRecordedOperandNo));
770 // The non-chain and non-flag results of the newly emitted node get recorded.
771 for (unsigned i = 0, e = ResultVTs.size(); i != e; ++i) {
772 if (ResultVTs[i] == MVT::Other || ResultVTs[i] == MVT::Flag) break;
773 OutputOps.push_back(NextRecordedOperandNo++);
778 EmitResultSDNodeXFormAsOperand(const TreePatternNode *N,
779 SmallVectorImpl<unsigned> &ResultOps) {
780 assert(N->getOperator()->isSubClassOf("SDNodeXForm") && "Not SDNodeXForm?");
783 SmallVector<unsigned, 8> InputOps;
785 // FIXME2: Could easily generalize this to support multiple inputs and outputs
786 // to the SDNodeXForm. For now we just support one input and one output like
787 // the old instruction selector.
788 assert(N->getNumChildren() == 1);
789 EmitResultOperand(N->getChild(0), InputOps);
791 // The input currently must have produced exactly one result.
792 assert(InputOps.size() == 1 && "Unexpected input to SDNodeXForm");
794 AddMatcher(new EmitNodeXFormMatcher(InputOps[0], N->getOperator()));
795 ResultOps.push_back(NextRecordedOperandNo++);
798 void MatcherGen::EmitResultOperand(const TreePatternNode *N,
799 SmallVectorImpl<unsigned> &ResultOps) {
800 // This is something selected from the pattern we matched.
801 if (!N->getName().empty())
802 return EmitResultOfNamedOperand(N, ResultOps);
805 return EmitResultLeafAsOperand(N, ResultOps);
807 Record *OpRec = N->getOperator();
808 if (OpRec->isSubClassOf("Instruction"))
809 return EmitResultInstructionAsOperand(N, ResultOps);
810 if (OpRec->isSubClassOf("SDNodeXForm"))
811 return EmitResultSDNodeXFormAsOperand(N, ResultOps);
812 errs() << "Unknown result node to emit code for: " << *N << '\n';
813 throw std::string("Unknown node in result pattern!");
816 void MatcherGen::EmitResultCode() {
817 // Patterns that match nodes with (potentially multiple) chain inputs have to
818 // merge them together into a token factor. This informs the generated code
819 // what all the chained nodes are.
820 if (!MatchedChainNodes.empty())
821 AddMatcher(new EmitMergeInputChainsMatcher
822 (MatchedChainNodes.data(), MatchedChainNodes.size()));
824 // Codegen the root of the result pattern, capturing the resulting values.
825 SmallVector<unsigned, 8> Ops;
826 EmitResultOperand(Pattern.getDstPattern(), Ops);
828 // At this point, we have however many values the result pattern produces.
829 // However, the input pattern might not need all of these. If there are
830 // excess values at the end (such as condition codes etc) just lop them off.
831 // This doesn't need to worry about flags or chains, just explicit results.
833 // FIXME2: This doesn't work because there is currently no way to get an
834 // accurate count of the # results the source pattern sets. This is because
835 // of the "parallel" construct in X86 land, which looks like this:
837 //def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
838 // (implicit EFLAGS)),
839 // (AND8rr GR8:$src1, GR8:$src2)>;
841 // This idiom means to match the two-result node X86and_flag (which is
842 // declared as returning a single result, because we can't match multi-result
843 // nodes yet). In this case, we would have to know that the input has two
844 // results. However, mul8r is modelled exactly the same way, but without
845 // implicit defs included. The fix is to support multiple results directly
846 // and eliminate 'parallel'.
848 // FIXME2: When this is fixed, we should revert the terrible hack in the
849 // OPC_EmitNode code in the interpreter.
851 const TreePatternNode *Src = Pattern.getSrcPattern();
852 unsigned NumSrcResults = Src->getTypeNum(0) != MVT::isVoid ? 1 : 0;
853 NumSrcResults += Pattern.getDstRegs().size();
854 assert(Ops.size() >= NumSrcResults && "Didn't provide enough results");
855 Ops.resize(NumSrcResults);
858 // If the matched pattern covers nodes which define a flag result, emit a node
859 // that tells the matcher about them so that it can update their results.
860 if (!MatchedFlagResultNodes.empty())
861 AddMatcher(new MarkFlagResultsMatcher(MatchedFlagResultNodes.data(),
862 MatchedFlagResultNodes.size()));
864 AddMatcher(new CompleteMatchMatcher(Ops.data(), Ops.size(), Pattern));
868 /// ConvertPatternToMatcher - Create the matcher for the specified pattern with
869 /// the specified variant. If the variant number is invalid, this returns null.
870 Matcher *llvm::ConvertPatternToMatcher(const PatternToMatch &Pattern,
872 const CodeGenDAGPatterns &CGP) {
873 MatcherGen Gen(Pattern, CGP);
875 // Generate the code for the matcher.
876 if (Gen.EmitMatcherCode(Variant))
879 // FIXME2: Kill extra MoveParent commands at the end of the matcher sequence.
880 // FIXME2: Split result code out to another table, and make the matcher end
881 // with an "Emit <index>" command. This allows result generation stuff to be
882 // shared and factored?
884 // If the match succeeds, then we generate Pattern.
885 Gen.EmitResultCode();
887 // Unconditional match.
888 return Gen.GetMatcher();