1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines wrappers for the Target class and related global
11 // functionality. This makes it easier to access the data and provides a single
12 // place that needs to check it for validity. All of these classes throw
13 // exceptions on error conditions.
15 //===----------------------------------------------------------------------===//
17 #ifndef CODEGEN_TARGET_H
18 #define CODEGEN_TARGET_H
20 #include "CodeGenRegisters.h"
21 #include "CodeGenInstruction.h"
23 #include "llvm/Support/raw_ostream.h"
28 struct CodeGenRegister;
31 // SelectionDAG node properties.
32 // SDNPMemOperand: indicates that a node touches memory and therefore must
33 // have an associated memory operand that describes the access.
50 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
51 /// record corresponds to.
52 MVT::SimpleValueType getValueType(Record *Rec);
54 std::string getName(MVT::SimpleValueType T);
55 std::string getEnumName(MVT::SimpleValueType T);
57 /// getQualifiedName - Return the name of the specified record, with a
58 /// namespace qualifier if the record contains one.
59 std::string getQualifiedName(const Record *R);
61 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
64 RecordKeeper &Records;
67 mutable DenseMap<const Record*, CodeGenInstruction*> Instructions;
68 mutable CodeGenRegBank *RegBank;
69 mutable std::vector<CodeGenRegisterClass> RegisterClasses;
70 mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
71 void ReadRegisterClasses() const;
72 void ReadInstructions() const;
73 void ReadLegalValueTypes() const;
75 mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
77 CodeGenTarget(RecordKeeper &Records);
79 Record *getTargetRecord() const { return TargetRec; }
80 const std::string &getName() const;
82 /// getInstNamespace - Return the target-specific instruction namespace.
84 std::string getInstNamespace() const;
86 /// getInstructionSet - Return the InstructionSet object.
88 Record *getInstructionSet() const;
90 /// getAsmParser - Return the AssemblyParser definition for this target.
92 Record *getAsmParser() const;
94 /// getAsmWriter - Return the AssemblyWriter definition for this target.
96 Record *getAsmWriter() const;
98 /// getRegBank - Return the register bank description.
99 CodeGenRegBank &getRegBank() const;
101 const std::vector<CodeGenRegister> &getRegisters() const {
102 return getRegBank().getRegisters();
105 /// getRegisterByName - If there is a register with the specific AsmName,
107 const CodeGenRegister *getRegisterByName(StringRef Name) const;
109 const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
110 if (RegisterClasses.empty()) ReadRegisterClasses();
111 return RegisterClasses;
114 const CodeGenRegisterClass &getRegisterClass(Record *R) const {
115 const std::vector<CodeGenRegisterClass> &RC = getRegisterClasses();
116 for (unsigned i = 0, e = RC.size(); i != e; ++i)
117 if (RC[i].TheDef == R)
119 assert(0 && "Didn't find the register class");
123 /// getRegisterClassForRegister - Find the register class that contains the
124 /// specified physical register. If the register is not in a register
125 /// class, return null. If the register is in multiple classes, and the
126 /// classes have a superset-subset relationship and the same set of
127 /// types, return the superclass. Otherwise return null.
128 const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const {
129 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
130 const CodeGenRegisterClass *FoundRC = 0;
131 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
132 const CodeGenRegisterClass &RC = RegisterClasses[i];
133 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
134 if (R != RC.Elements[ei])
137 // If a register's classes have different types, return null.
138 if (FoundRC && RC.getValueTypes() != FoundRC->getValueTypes())
141 // If this is the first class that contains the register,
142 // make a note of it and go on to the next class.
148 std::vector<Record *> Elements(RC.Elements);
149 std::vector<Record *> FoundElements(FoundRC->Elements);
150 std::sort(Elements.begin(), Elements.end());
151 std::sort(FoundElements.begin(), FoundElements.end());
153 // Check to see if the previously found class that contains
154 // the register is a subclass of the current class. If so,
155 // prefer the superclass.
156 if (std::includes(Elements.begin(), Elements.end(),
157 FoundElements.begin(), FoundElements.end())) {
162 // Check to see if the previously found class that contains
163 // the register is a superclass of the current class. If so,
164 // prefer the superclass.
165 if (std::includes(FoundElements.begin(), FoundElements.end(),
166 Elements.begin(), Elements.end()))
169 // Multiple classes, and neither is a superclass of the other.
177 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
178 /// specified physical register.
179 std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const;
181 const std::vector<MVT::SimpleValueType> &getLegalValueTypes() const {
182 if (LegalValueTypes.empty()) ReadLegalValueTypes();
183 return LegalValueTypes;
186 /// isLegalValueType - Return true if the specified value type is natively
187 /// supported by the target (i.e. there are registers that directly hold it).
188 bool isLegalValueType(MVT::SimpleValueType VT) const {
189 const std::vector<MVT::SimpleValueType> &LegalVTs = getLegalValueTypes();
190 for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
191 if (LegalVTs[i] == VT) return true;
196 DenseMap<const Record*, CodeGenInstruction*> &getInstructions() const {
197 if (Instructions.empty()) ReadInstructions();
202 CodeGenInstruction &getInstruction(const Record *InstRec) const {
203 if (Instructions.empty()) ReadInstructions();
204 DenseMap<const Record*, CodeGenInstruction*>::iterator I =
205 Instructions.find(InstRec);
206 assert(I != Instructions.end() && "Not an instruction");
210 /// getInstructionsByEnumValue - Return all of the instructions defined by the
211 /// target, ordered by their enum value.
212 const std::vector<const CodeGenInstruction*> &
213 getInstructionsByEnumValue() const {
214 if (InstrsByEnum.empty()) ComputeInstrsByEnum();
218 typedef std::vector<const CodeGenInstruction*>::const_iterator inst_iterator;
219 inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
220 inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
223 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
225 bool isLittleEndianEncoding() const;
228 void ComputeInstrsByEnum() const;
231 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
232 /// tablegen class in TargetSelectionDAG.td
233 class ComplexPattern {
234 MVT::SimpleValueType Ty;
235 unsigned NumOperands;
236 std::string SelectFunc;
237 std::vector<Record*> RootNodes;
238 unsigned Properties; // Node properties
240 ComplexPattern() : NumOperands(0) {}
241 ComplexPattern(Record *R);
243 MVT::SimpleValueType getValueType() const { return Ty; }
244 unsigned getNumOperands() const { return NumOperands; }
245 const std::string &getSelectFunc() const { return SelectFunc; }
246 const std::vector<Record*> &getRootNodes() const {
249 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
252 } // End llvm namespace