1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_REGISTERS_H
16 #define CODEGEN_REGISTERS_H
18 #include "SetTheory.h"
19 #include "llvm/TableGen/Record.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/SetVector.h"
34 /// CodeGenSubRegIndex - Represents a sub-register index.
35 class CodeGenSubRegIndex {
37 const unsigned EnumValue;
40 CodeGenSubRegIndex(Record *R, unsigned Enum);
42 const std::string &getName() const;
43 std::string getNamespace() const;
44 std::string getQualifiedName() const;
46 // Order CodeGenSubRegIndex pointers by EnumValue.
48 bool operator()(const CodeGenSubRegIndex *A,
49 const CodeGenSubRegIndex *B) const {
51 return A->EnumValue < B->EnumValue;
55 // Map of composite subreg indices.
56 typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap;
58 // Returns the subreg index that results from composing this with Idx.
59 // Returns NULL if this and Idx don't compose.
60 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
61 CompMap::const_iterator I = Composed.find(Idx);
62 return I == Composed.end() ? 0 : I->second;
65 // Add a composite subreg index: this+A = B.
66 // Return a conflicting composite, or NULL
67 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
68 CodeGenSubRegIndex *B) {
69 std::pair<CompMap::iterator, bool> Ins =
70 Composed.insert(std::make_pair(A, B));
71 return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second;
74 // Clean out redundant composite mappings.
75 void cleanComposites();
77 // Return the map of composites.
78 const CompMap &getComposites() const { return Composed; }
84 /// CodeGenRegister - Represents a register definition.
85 struct CodeGenRegister {
89 bool CoveredBySubRegs;
91 // Map SubRegIndex -> Register.
92 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
93 CodeGenSubRegIndex::Less> SubRegMap;
95 CodeGenRegister(Record *R, unsigned Enum);
97 const std::string &getName() const;
99 // Get a map of sub-registers computed lazily.
100 // This includes unique entries for all sub-sub-registers.
101 const SubRegMap &getSubRegs(CodeGenRegBank&);
103 const SubRegMap &getSubRegs() const {
104 assert(SubRegsComplete && "Must precompute sub-registers");
108 // Add sub-registers to OSet following a pre-order defined by the .td file.
109 void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet,
110 CodeGenRegBank&) const;
112 // List of super-registers in topological order, small to large.
113 typedef std::vector<CodeGenRegister*> SuperRegList;
115 // Get the list of super-registers.
116 // This is only valid after computeDerivedInfo has visited all registers.
117 const SuperRegList &getSuperRegs() const {
118 assert(SubRegsComplete && "Must precompute sub-registers");
122 // Order CodeGenRegister pointers by EnumValue.
124 bool operator()(const CodeGenRegister *A,
125 const CodeGenRegister *B) const {
127 return A->EnumValue < B->EnumValue;
131 // Canonically ordered set.
132 typedef std::set<const CodeGenRegister*, Less> Set;
135 bool SubRegsComplete;
137 SuperRegList SuperRegs;
141 class CodeGenRegisterClass {
142 CodeGenRegister::Set Members;
143 // Allocation orders. Order[0] always contains all registers in Members.
144 std::vector<SmallVector<Record*, 16> > Orders;
145 // Bit mask of sub-classes including this, indexed by their EnumValue.
146 BitVector SubClasses;
147 // List of super-classes, topologocally ordered to have the larger classes
148 // first. This is the same as sorting by EnumValue.
149 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
153 // For a synthesized class, inherit missing properties from the nearest
155 void inheritProperties(CodeGenRegBank&);
157 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
158 // registers have a SubRegIndex sub-register.
159 DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg;
161 // Map SubRegIndex -> set of super-reg classes. This is all register
162 // classes SuperRC such that:
164 // R:SubRegIndex in this RC for all R in SuperRC.
166 DenseMap<CodeGenSubRegIndex*,
167 SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
170 std::string Namespace;
171 std::vector<MVT::SimpleValueType> VTs;
173 unsigned SpillAlignment;
176 // Map SubRegIndex -> RegisterClass
177 DenseMap<Record*,Record*> SubRegClasses;
178 std::string AltOrderSelect;
180 // Return the Record that defined this class, or NULL if the class was
181 // created by TableGen.
182 Record *getDef() const { return TheDef; }
184 const std::string &getName() const { return Name; }
185 std::string getQualifiedName() const;
186 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
187 unsigned getNumValueTypes() const { return VTs.size(); }
189 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
190 if (VTNum < VTs.size())
192 assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
196 // Return true if this this class contains the register.
197 bool contains(const CodeGenRegister*) const;
199 // Returns true if RC is a subclass.
200 // RC is a sub-class of this class if it is a valid replacement for any
201 // instruction operand where a register of this classis required. It must
202 // satisfy these conditions:
204 // 1. All RC registers are also in this.
205 // 2. The RC spill size must not be smaller than our spill size.
206 // 3. RC spill alignment must be compatible with ours.
208 bool hasSubClass(const CodeGenRegisterClass *RC) const {
209 return SubClasses.test(RC->EnumValue);
212 // getSubClassWithSubReg - Returns the largest sub-class where all
213 // registers have a SubIdx sub-register.
214 CodeGenRegisterClass*
215 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
216 return SubClassWithSubReg.lookup(SubIdx);
219 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
220 CodeGenRegisterClass *SubRC) {
221 SubClassWithSubReg[SubIdx] = SubRC;
224 // getSuperRegClasses - Returns a bit vector of all register classes
225 // containing only SubIdx super-registers of this class.
226 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
228 // addSuperRegClass - Add a class containing only SudIdx super-registers.
229 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
230 CodeGenRegisterClass *SuperRC) {
231 SuperRegClasses[SubIdx].insert(SuperRC);
234 // getSubClasses - Returns a constant BitVector of subclasses indexed by
236 // The SubClasses vector includs an entry for this class.
237 const BitVector &getSubClasses() const { return SubClasses; }
239 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
240 // The array does not include an entry for this class.
241 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
245 // Returns an ordered list of class members.
246 // The order of registers is the same as in the .td file.
247 // No = 0 is the default allocation order, No = 1 is the first alternative.
248 ArrayRef<Record*> getOrder(unsigned No = 0) const {
252 // Return the total number of allocation orders available.
253 unsigned getNumOrders() const { return Orders.size(); }
255 // Get the set of registers. This set contains the same registers as
257 const CodeGenRegister::Set &getMembers() const { return Members; }
259 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
261 // A key representing the parts of a register class used for forming
262 // sub-classes. Note the ordering provided by this key is not the same as
263 // the topological order used for the EnumValues.
265 const CodeGenRegister::Set *Members;
267 unsigned SpillAlignment;
270 : Members(O.Members),
271 SpillSize(O.SpillSize),
272 SpillAlignment(O.SpillAlignment) {}
274 Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
275 : Members(M), SpillSize(S), SpillAlignment(A) {}
277 Key(const CodeGenRegisterClass &RC)
278 : Members(&RC.getMembers()),
279 SpillSize(RC.SpillSize),
280 SpillAlignment(RC.SpillAlignment) {}
282 // Lexicographical order of (Members, SpillSize, SpillAlignment).
283 bool operator<(const Key&) const;
286 // Create a non-user defined register class.
287 CodeGenRegisterClass(StringRef Name, Key Props);
289 // Called by CodeGenRegBank::CodeGenRegBank().
290 static void computeSubClasses(CodeGenRegBank&);
293 // CodeGenRegBank - Represent a target's registers and the relations between
295 class CodeGenRegBank {
296 RecordKeeper &Records;
300 std::vector<CodeGenSubRegIndex*> SubRegIndices;
301 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
302 unsigned NumNamedIndices;
305 std::vector<CodeGenRegister*> Registers;
306 DenseMap<Record*, CodeGenRegister*> Def2Reg;
309 std::vector<CodeGenRegisterClass*> RegClasses;
310 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
311 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
314 // Add RC to *2RC maps.
315 void addToMaps(CodeGenRegisterClass*);
317 // Create a synthetic sub-class if it is missing.
318 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
319 const CodeGenRegister::Set *Membs,
322 // Infer missing register classes.
323 void computeInferredRegisterClasses();
324 void inferCommonSubClass(CodeGenRegisterClass *RC);
325 void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
326 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
327 unsigned FirstSubRegRC = 0);
329 // Populate the Composite map from sub-register relationships.
330 void computeComposites();
333 CodeGenRegBank(RecordKeeper&);
335 SetTheory &getSets() { return Sets; }
337 // Sub-register indices. The first NumNamedIndices are defined by the user
338 // in the .td files. The rest are synthesized such that all sub-registers
339 // have a unique name.
340 ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; }
341 unsigned getNumNamedIndices() { return NumNamedIndices; }
343 // Find a SubRegIndex form its Record def.
344 CodeGenSubRegIndex *getSubRegIdx(Record*);
346 // Find or create a sub-register index representing the A+B composition.
347 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
348 CodeGenSubRegIndex *B);
350 const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
352 // Find a register from its Record def.
353 CodeGenRegister *getReg(Record*);
355 ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
359 // Find a register class from its def.
360 CodeGenRegisterClass *getRegClass(Record*);
362 /// getRegisterClassForRegister - Find the register class that contains the
363 /// specified physical register. If the register is not in a register
364 /// class, return null. If the register is in multiple classes, and the
365 /// classes have a superset-subset relationship and the same set of types,
366 /// return the superclass. Otherwise return null.
367 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
369 // Computed derived records such as missing sub-register indices.
370 void computeDerivedInfo();
372 // Compute full overlap sets for every register. These sets include the
373 // rarely used aliases that are neither sub nor super-registers.
375 // Map[R1].count(R2) is reflexive and symmetric, but not transitive.
377 // If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2].
378 void computeOverlaps(std::map<const CodeGenRegister*,
379 CodeGenRegister::Set> &Map);
381 // Compute the set of registers completely covered by the registers in Regs.
382 // The returned BitVector will have a bit set for each register in Regs,
383 // all sub-registers, and all super-registers that are covered by the
384 // registers in Regs.
386 // This is used to compute the mask of call-preserved registers from a list
388 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);