1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterEmitter.h"
16 #include "CodeGenTarget.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/MathExtras.h"
26 static bool isIdentChar(char C) {
27 return (C >= 'a' && C <= 'z') ||
28 (C >= 'A' && C <= 'Z') ||
29 (C >= '0' && C <= '9') ||
33 // This should be an anon namespace, this works around a GCC warning.
35 struct AsmWriterOperand {
37 // Output this text surrounded by quotes to the asm.
39 // This is the name of a routine to call to print the operand.
40 isMachineInstrOperand,
41 // Output this text verbatim to the asm writer. It is code that
42 // will output some text to the asm.
43 isLiteralStatementOperand
46 /// Str - For isLiteralTextOperand, this IS the literal text. For
47 /// isMachineInstrOperand, this is the PrinterMethodName for the operand..
48 /// For isLiteralStatementOperand, this is the code to insert verbatim
49 /// into the asm writer.
52 /// MiOpNo - For isMachineInstrOperand, this is the operand number of the
53 /// machine instruction.
56 /// MiModifier - For isMachineInstrOperand, this is the modifier string for
57 /// an operand, specified with syntax like ${opname:modifier}.
58 std::string MiModifier;
60 // To make VS STL happy
61 AsmWriterOperand(OpType op = isLiteralTextOperand):OperandType(op) {}
63 AsmWriterOperand(const std::string &LitStr,
64 OpType op = isLiteralTextOperand)
65 : OperandType(op), Str(LitStr) {}
67 AsmWriterOperand(const std::string &Printer, unsigned OpNo,
68 const std::string &Modifier,
69 OpType op = isMachineInstrOperand)
70 : OperandType(op), Str(Printer), MIOpNo(OpNo),
71 MiModifier(Modifier) {}
73 bool operator!=(const AsmWriterOperand &Other) const {
74 if (OperandType != Other.OperandType || Str != Other.Str) return true;
75 if (OperandType == isMachineInstrOperand)
76 return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier;
79 bool operator==(const AsmWriterOperand &Other) const {
80 return !operator!=(Other);
83 /// getCode - Return the code that prints this operand.
84 std::string getCode() const;
91 std::vector<AsmWriterOperand> Operands;
92 const CodeGenInstruction *CGI;
94 AsmWriterInst(const CodeGenInstruction &CGI, Record *AsmWriter);
96 /// MatchesAllButOneOp - If this instruction is exactly identical to the
97 /// specified instruction except for one differing operand, return the
98 /// differing operand number. Otherwise return ~0.
99 unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const;
102 void AddLiteralString(const std::string &Str) {
103 // If the last operand was already a literal text string, append this to
104 // it, otherwise add a new operand.
105 if (!Operands.empty() &&
106 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
107 Operands.back().Str.append(Str);
109 Operands.push_back(AsmWriterOperand(Str));
115 std::string AsmWriterOperand::getCode() const {
116 if (OperandType == isLiteralTextOperand) {
118 return "O << '" + Str + "'; ";
119 return "O << \"" + Str + "\"; ";
122 if (OperandType == isLiteralStatementOperand)
125 std::string Result = Str + "(MI";
127 Result += ", " + utostr(MIOpNo);
128 if (!MiModifier.empty())
129 Result += ", \"" + MiModifier + '"';
130 return Result + "); ";
134 /// ParseAsmString - Parse the specified Instruction's AsmString into this
137 AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, Record *AsmWriter) {
140 unsigned Variant = AsmWriter->getValueAsInt("Variant");
141 int FirstOperandColumn = AsmWriter->getValueAsInt("FirstOperandColumn");
142 int OperandSpacing = AsmWriter->getValueAsInt("OperandSpacing");
144 unsigned CurVariant = ~0U; // ~0 if we are outside a {.|.|.} region, other #.
146 // This is the number of tabs we've seen if we're doing columnar layout.
147 unsigned CurColumn = 0;
150 // NOTE: Any extensions to this code need to be mirrored in the
151 // AsmPrinter::printInlineAsm code that executes as compile time (assuming
152 // that inline asm strings should also get the new feature)!
153 const std::string &AsmString = CGI.AsmString;
154 std::string::size_type LastEmitted = 0;
155 while (LastEmitted != AsmString.size()) {
156 std::string::size_type DollarPos =
157 AsmString.find_first_of("${|}\\", LastEmitted);
158 if (DollarPos == std::string::npos) DollarPos = AsmString.size();
160 // Emit a constant string fragment.
162 if (DollarPos != LastEmitted) {
163 if (CurVariant == Variant || CurVariant == ~0U) {
164 for (; LastEmitted != DollarPos; ++LastEmitted)
165 switch (AsmString[LastEmitted]) {
167 AddLiteralString("\\n");
170 // If the asm writer is not using a columnar layout, \t is not
172 if (FirstOperandColumn == -1 || OperandSpacing == -1) {
173 AddLiteralString("\\t");
175 // We recognize a tab as an operand delimeter.
176 unsigned DestColumn = FirstOperandColumn +
177 CurColumn++ * OperandSpacing;
179 AsmWriterOperand("O.PadToColumn(" +
180 utostr(DestColumn) + ");\n",
181 AsmWriterOperand::isLiteralStatementOperand));
185 AddLiteralString("\\\"");
188 AddLiteralString("\\\\");
191 AddLiteralString(std::string(1, AsmString[LastEmitted]));
195 LastEmitted = DollarPos;
197 } else if (AsmString[DollarPos] == '\\') {
198 if (DollarPos+1 != AsmString.size() &&
199 (CurVariant == Variant || CurVariant == ~0U)) {
200 if (AsmString[DollarPos+1] == 'n') {
201 AddLiteralString("\\n");
202 } else if (AsmString[DollarPos+1] == 't') {
203 // If the asm writer is not using a columnar layout, \t is not
205 if (FirstOperandColumn == -1 || OperandSpacing == -1) {
206 AddLiteralString("\\t");
210 // We recognize a tab as an operand delimeter.
211 unsigned DestColumn = FirstOperandColumn +
212 CurColumn++ * OperandSpacing;
214 AsmWriterOperand("O.PadToColumn(" + utostr(DestColumn) + ");\n",
215 AsmWriterOperand::isLiteralStatementOperand));
217 } else if (std::string("${|}\\").find(AsmString[DollarPos+1])
218 != std::string::npos) {
219 AddLiteralString(std::string(1, AsmString[DollarPos+1]));
221 throw "Non-supported escaped character found in instruction '" +
222 CGI.TheDef->getName() + "'!";
224 LastEmitted = DollarPos+2;
227 } else if (AsmString[DollarPos] == '{') {
228 if (CurVariant != ~0U)
229 throw "Nested variants found for instruction '" +
230 CGI.TheDef->getName() + "'!";
231 LastEmitted = DollarPos+1;
232 CurVariant = 0; // We are now inside of the variant!
233 } else if (AsmString[DollarPos] == '|') {
234 if (CurVariant == ~0U)
235 throw "'|' character found outside of a variant in instruction '"
236 + CGI.TheDef->getName() + "'!";
239 } else if (AsmString[DollarPos] == '}') {
240 if (CurVariant == ~0U)
241 throw "'}' character found outside of a variant in instruction '"
242 + CGI.TheDef->getName() + "'!";
245 } else if (DollarPos+1 != AsmString.size() &&
246 AsmString[DollarPos+1] == '$') {
247 if (CurVariant == Variant || CurVariant == ~0U) {
248 AddLiteralString("$"); // "$$" -> $
250 LastEmitted = DollarPos+2;
252 // Get the name of the variable.
253 std::string::size_type VarEnd = DollarPos+1;
255 // handle ${foo}bar as $foo by detecting whether the character following
256 // the dollar sign is a curly brace. If so, advance VarEnd and DollarPos
257 // so the variable name does not contain the leading curly brace.
258 bool hasCurlyBraces = false;
259 if (VarEnd < AsmString.size() && '{' == AsmString[VarEnd]) {
260 hasCurlyBraces = true;
265 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
267 std::string VarName(AsmString.begin()+DollarPos+1,
268 AsmString.begin()+VarEnd);
270 // Modifier - Support ${foo:modifier} syntax, where "modifier" is passed
271 // into printOperand. Also support ${:feature}, which is passed into
273 std::string Modifier;
275 // In order to avoid starting the next string at the terminating curly
276 // brace, advance the end position past it if we found an opening curly
278 if (hasCurlyBraces) {
279 if (VarEnd >= AsmString.size())
280 throw "Reached end of string before terminating curly brace in '"
281 + CGI.TheDef->getName() + "'";
283 // Look for a modifier string.
284 if (AsmString[VarEnd] == ':') {
286 if (VarEnd >= AsmString.size())
287 throw "Reached end of string before terminating curly brace in '"
288 + CGI.TheDef->getName() + "'";
290 unsigned ModifierStart = VarEnd;
291 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
293 Modifier = std::string(AsmString.begin()+ModifierStart,
294 AsmString.begin()+VarEnd);
295 if (Modifier.empty())
296 throw "Bad operand modifier name in '"+ CGI.TheDef->getName() + "'";
299 if (AsmString[VarEnd] != '}')
300 throw "Variable name beginning with '{' did not end with '}' in '"
301 + CGI.TheDef->getName() + "'";
304 if (VarName.empty() && Modifier.empty())
305 throw "Stray '$' in '" + CGI.TheDef->getName() +
306 "' asm string, maybe you want $$?";
308 if (VarName.empty()) {
309 // Just a modifier, pass this into PrintSpecial.
310 Operands.push_back(AsmWriterOperand("PrintSpecial", ~0U, Modifier));
312 // Otherwise, normal operand.
313 unsigned OpNo = CGI.getOperandNamed(VarName);
314 CodeGenInstruction::OperandInfo OpInfo = CGI.OperandList[OpNo];
316 if (CurVariant == Variant || CurVariant == ~0U) {
317 unsigned MIOp = OpInfo.MIOperandNo;
318 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, MIOp,
322 LastEmitted = VarEnd;
326 Operands.push_back(AsmWriterOperand("return;",
327 AsmWriterOperand::isLiteralStatementOperand));
330 /// MatchesAllButOneOp - If this instruction is exactly identical to the
331 /// specified instruction except for one differing operand, return the differing
332 /// operand number. If more than one operand mismatches, return ~1, otherwise
333 /// if the instructions are identical return ~0.
334 unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{
335 if (Operands.size() != Other.Operands.size()) return ~1;
337 unsigned MismatchOperand = ~0U;
338 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
339 if (Operands[i] != Other.Operands[i]) {
340 if (MismatchOperand != ~0U) // Already have one mismatch?
346 return MismatchOperand;
349 static void PrintCases(std::vector<std::pair<std::string,
350 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
351 O << " case " << OpsToPrint.back().first << ": ";
352 AsmWriterOperand TheOp = OpsToPrint.back().second;
353 OpsToPrint.pop_back();
355 // Check to see if any other operands are identical in this list, and if so,
356 // emit a case label for them.
357 for (unsigned i = OpsToPrint.size(); i != 0; --i)
358 if (OpsToPrint[i-1].second == TheOp) {
359 O << "\n case " << OpsToPrint[i-1].first << ": ";
360 OpsToPrint.erase(OpsToPrint.begin()+i-1);
363 // Finally, emit the code.
364 O << TheOp.getCode();
369 /// EmitInstructions - Emit the last instruction in the vector and any other
370 /// instructions that are suitably similar to it.
371 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
373 AsmWriterInst FirstInst = Insts.back();
376 std::vector<AsmWriterInst> SimilarInsts;
377 unsigned DifferingOperand = ~0;
378 for (unsigned i = Insts.size(); i != 0; --i) {
379 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
381 if (DifferingOperand == ~0U) // First match!
382 DifferingOperand = DiffOp;
384 // If this differs in the same operand as the rest of the instructions in
385 // this class, move it to the SimilarInsts list.
386 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
387 SimilarInsts.push_back(Insts[i-1]);
388 Insts.erase(Insts.begin()+i-1);
393 O << " case " << FirstInst.CGI->Namespace << "::"
394 << FirstInst.CGI->TheDef->getName() << ":\n";
395 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
396 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
397 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
398 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
399 if (i != DifferingOperand) {
400 // If the operand is the same for all instructions, just print it.
401 O << " " << FirstInst.Operands[i].getCode();
403 // If this is the operand that varies between all of the instructions,
404 // emit a switch for just this operand now.
405 O << " switch (MI->getOpcode()) {\n";
406 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
407 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
408 FirstInst.CGI->TheDef->getName(),
409 FirstInst.Operands[i]));
411 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
412 AsmWriterInst &AWI = SimilarInsts[si];
413 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
414 AWI.CGI->TheDef->getName(),
417 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
418 while (!OpsToPrint.empty())
419 PrintCases(OpsToPrint, O);
427 void AsmWriterEmitter::
428 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
429 std::vector<unsigned> &InstIdxs,
430 std::vector<unsigned> &InstOpsUsed) const {
431 InstIdxs.assign(NumberedInstructions.size(), ~0U);
433 // This vector parallels UniqueOperandCommands, keeping track of which
434 // instructions each case are used for. It is a comma separated string of
436 std::vector<std::string> InstrsForCase;
437 InstrsForCase.resize(UniqueOperandCommands.size());
438 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
440 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
441 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
442 if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc.
445 if (Inst->Operands.empty())
446 continue; // Instruction already done.
448 Command = " " + Inst->Operands[0].getCode() + "\n";
450 // Check to see if we already have 'Command' in UniqueOperandCommands.
452 bool FoundIt = false;
453 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
454 if (UniqueOperandCommands[idx] == Command) {
456 InstrsForCase[idx] += ", ";
457 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
462 InstIdxs[i] = UniqueOperandCommands.size();
463 UniqueOperandCommands.push_back(Command);
464 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
466 // This command matches one operand so far.
467 InstOpsUsed.push_back(1);
471 // For each entry of UniqueOperandCommands, there is a set of instructions
472 // that uses it. If the next command of all instructions in the set are
473 // identical, fold it into the command.
474 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
475 CommandIdx != e; ++CommandIdx) {
477 for (unsigned Op = 1; ; ++Op) {
478 // Scan for the first instruction in the set.
479 std::vector<unsigned>::iterator NIT =
480 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
481 if (NIT == InstIdxs.end()) break; // No commonality.
483 // If this instruction has no more operands, we isn't anything to merge
484 // into this command.
485 const AsmWriterInst *FirstInst =
486 getAsmWriterInstByID(NIT-InstIdxs.begin());
487 if (!FirstInst || FirstInst->Operands.size() == Op)
490 // Otherwise, scan to see if all of the other instructions in this command
491 // set share the operand.
493 // Keep track of the maximum, number of operands or any
494 // instruction we see in the group.
495 size_t MaxSize = FirstInst->Operands.size();
497 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
498 NIT != InstIdxs.end();
499 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
500 // Okay, found another instruction in this command set. If the operand
501 // matches, we're ok, otherwise bail out.
502 const AsmWriterInst *OtherInst =
503 getAsmWriterInstByID(NIT-InstIdxs.begin());
506 OtherInst->Operands.size() > FirstInst->Operands.size())
507 MaxSize = std::max(MaxSize, OtherInst->Operands.size());
509 if (!OtherInst || OtherInst->Operands.size() == Op ||
510 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
517 // Okay, everything in this command set has the same next operand. Add it
518 // to UniqueOperandCommands and remember that it was consumed.
519 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
521 UniqueOperandCommands[CommandIdx] += Command;
522 InstOpsUsed[CommandIdx]++;
526 // Prepend some of the instructions each case is used for onto the case val.
527 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
528 std::string Instrs = InstrsForCase[i];
529 if (Instrs.size() > 70) {
530 Instrs.erase(Instrs.begin()+70, Instrs.end());
535 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
536 UniqueOperandCommands[i];
541 /// EmitPrintInstruction - Generate the code for the "printInstruction" method
543 void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
544 CodeGenTarget Target;
545 Record *AsmWriter = Target.getAsmWriter();
546 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
549 "/// printInstruction - This method is automatically generated by tablegen\n"
550 "/// from the instruction set description.\n"
551 "void " << Target.getName() << ClassName
552 << "::printInstruction(const MachineInstr *MI) {\n";
554 std::vector<AsmWriterInst> Instructions;
556 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
557 E = Target.inst_end(); I != E; ++I)
558 if (!I->second.AsmString.empty() &&
559 I->second.TheDef->getName() != "PHI")
560 Instructions.push_back(AsmWriterInst(I->second, AsmWriter));
562 // Get the instruction numbering.
563 Target.getInstructionsByEnumValue(NumberedInstructions);
565 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
566 // all machine instructions are necessarily being printed, so there may be
567 // target instructions not in this map.
568 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
569 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
571 // Build an aggregate string, and build a table of offsets into it.
572 std::map<std::string, unsigned> StringOffset;
573 std::string AggregateString;
574 AggregateString.push_back(0); // "\0"
575 AggregateString.push_back(0); // "\0"
577 /// OpcodeInfo - This encodes the index of the string to use for the first
578 /// chunk of the output as well as indices used for operand printing.
579 std::vector<unsigned> OpcodeInfo;
581 unsigned MaxStringIdx = 0;
582 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
583 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
586 // Something not handled by the asmwriter printer.
588 } else if (AWI->Operands[0].OperandType !=
589 AsmWriterOperand::isLiteralTextOperand ||
590 AWI->Operands[0].Str.empty()) {
591 // Something handled by the asmwriter printer, but with no leading string.
594 unsigned &Entry = StringOffset[AWI->Operands[0].Str];
596 // Add the string to the aggregate if this is the first time found.
597 MaxStringIdx = Entry = AggregateString.size();
598 std::string Str = AWI->Operands[0].Str;
600 AggregateString += Str;
601 AggregateString += '\0';
605 // Nuke the string from the operand list. It is now handled!
606 AWI->Operands.erase(AWI->Operands.begin());
608 OpcodeInfo.push_back(Idx);
611 // Figure out how many bits we used for the string index.
612 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+1);
614 // To reduce code size, we compactify common instructions into a few bits
615 // in the opcode-indexed table.
616 unsigned BitsLeft = 32-AsmStrBits;
618 std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
621 std::vector<std::string> UniqueOperandCommands;
622 std::vector<unsigned> InstIdxs;
623 std::vector<unsigned> NumInstOpsHandled;
624 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
627 // If we ran out of operands to print, we're done.
628 if (UniqueOperandCommands.empty()) break;
630 // Compute the number of bits we need to represent these cases, this is
631 // ceil(log2(numentries)).
632 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
634 // If we don't have enough bits for this operand, don't include it.
635 if (NumBits > BitsLeft) {
636 DEBUG(errs() << "Not enough bits to densely encode " << NumBits
641 // Otherwise, we can include this in the initial lookup table. Add it in.
643 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
644 if (InstIdxs[i] != ~0U)
645 OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
647 // Remove the info about this operand.
648 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
649 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
650 if (!Inst->Operands.empty()) {
651 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
652 assert(NumOps <= Inst->Operands.size() &&
653 "Can't remove this many ops!");
654 Inst->Operands.erase(Inst->Operands.begin(),
655 Inst->Operands.begin()+NumOps);
659 // Remember the handlers for this set of operands.
660 TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
665 O<<" static const unsigned OpInfo[] = {\n";
666 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
667 O << " " << OpcodeInfo[i] << "U,\t// "
668 << NumberedInstructions[i]->TheDef->getName() << "\n";
670 // Add a dummy entry so the array init doesn't end with a comma.
674 // Emit the string itself.
675 O << " const char *AsmStrs = \n \"";
676 unsigned CharsPrinted = 0;
677 EscapeString(AggregateString);
678 for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) {
679 if (CharsPrinted > 70) {
683 O << AggregateString[i];
686 // Print escape sequences all together.
687 if (AggregateString[i] == '\\') {
688 assert(i+1 < AggregateString.size() && "Incomplete escape sequence!");
689 if (isdigit(AggregateString[i+1])) {
690 assert(isdigit(AggregateString[i+2]) && isdigit(AggregateString[i+3]) &&
691 "Expected 3 digit octal escape!");
692 O << AggregateString[++i];
693 O << AggregateString[++i];
694 O << AggregateString[++i];
697 O << AggregateString[++i];
704 O << "\n#ifndef NO_ASM_WRITER_BOILERPLATE\n";
706 O << " if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {\n"
707 << " O << \"\\t\";\n"
708 << " printInlineAsm(MI);\n"
710 << " } else if (MI->isLabel()) {\n"
711 << " printLabel(MI);\n"
713 << " } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {\n"
714 << " printImplicitDef(MI);\n"
720 O << " O << \"\\t\";\n\n";
722 O << " // Emit the opcode for the instruction.\n"
723 << " unsigned Bits = OpInfo[MI->getOpcode()];\n"
724 << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
725 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ");\n\n";
727 // Output the table driven operand information.
728 BitsLeft = 32-AsmStrBits;
729 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
730 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
732 // Compute the number of bits we need to represent these cases, this is
733 // ceil(log2(numentries)).
734 unsigned NumBits = Log2_32_Ceil(Commands.size());
735 assert(NumBits <= BitsLeft && "consistency error");
737 // Emit code to extract this field from Bits.
740 O << "\n // Fragment " << i << " encoded into " << NumBits
741 << " bits for " << Commands.size() << " unique commands.\n";
743 if (Commands.size() == 2) {
744 // Emit two possibilitys with if/else.
745 O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
746 << ((1 << NumBits)-1) << ") {\n"
752 O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
753 << ((1 << NumBits)-1) << ") {\n"
754 << " default: // unreachable.\n";
756 // Print out all the cases.
757 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
758 O << " case " << i << ":\n";
766 // Okay, delete instructions with no operand info left.
767 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
768 // Entire instruction has been emitted?
769 AsmWriterInst &Inst = Instructions[i];
770 if (Inst.Operands.empty()) {
771 Instructions.erase(Instructions.begin()+i);
777 // Because this is a vector, we want to emit from the end. Reverse all of the
778 // elements in the vector.
779 std::reverse(Instructions.begin(), Instructions.end());
781 if (!Instructions.empty()) {
782 // Find the opcode # of inline asm.
783 O << " switch (MI->getOpcode()) {\n";
784 while (!Instructions.empty())
785 EmitInstructions(Instructions, O);
796 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
797 CodeGenTarget Target;
798 Record *AsmWriter = Target.getAsmWriter();
799 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
800 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
803 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
804 "/// from the register set description. This returns the assembler name\n"
805 "/// for the specified register.\n"
806 "const char *" << Target.getName() << ClassName
807 << "::getRegisterName(unsigned RegNo) {\n"
808 << " assert(RegNo && RegNo < " << (Registers.size()+1)
809 << " && \"Invalid register number!\");\n"
811 << " static const char *const RegAsmNames[] = {\n";
812 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
813 const CodeGenRegister &Reg = Registers[i];
815 std::string AsmName = Reg.TheDef->getValueAsString("AsmName");
817 AsmName = Reg.getName();
818 O << " \"" << AsmName << "\",\n";
823 << " return RegAsmNames[RegNo-1];\n"
828 void AsmWriterEmitter::run(raw_ostream &O) {
829 EmitSourceFileHeader("Assembly Writer Source Fragment", O);
831 EmitPrintInstruction(O);
832 EmitGetRegisterName(O);