1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific valeus in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "AsmMatcherEmitter.h"
100 #include "CodeGenTarget.h"
101 #include "StringToOffsetTable.h"
102 #include "llvm/ADT/OwningPtr.h"
103 #include "llvm/ADT/PointerUnion.h"
104 #include "llvm/ADT/SmallPtrSet.h"
105 #include "llvm/ADT/SmallVector.h"
106 #include "llvm/ADT/STLExtras.h"
107 #include "llvm/ADT/StringExtras.h"
108 #include "llvm/Support/CommandLine.h"
109 #include "llvm/Support/Debug.h"
110 #include "llvm/Support/ErrorHandling.h"
111 #include "llvm/TableGen/Error.h"
112 #include "llvm/TableGen/Record.h"
113 #include "llvm/TableGen/StringMatcher.h"
116 using namespace llvm;
118 static cl::opt<std::string>
119 MatchPrefix("match-prefix", cl::init(""),
120 cl::desc("Only match instructions with the given prefix"));
123 class AsmMatcherInfo;
124 struct SubtargetFeatureInfo;
126 /// ClassInfo - Helper class for storing the information about a particular
127 /// class of operands which can be matched.
130 /// Invalid kind, for use as a sentinel value.
133 /// The class for a particular token.
136 /// The (first) register class, subsequent register classes are
137 /// RegisterClass0+1, and so on.
140 /// The (first) user defined class, subsequent user defined classes are
141 /// UserClass0+1, and so on.
145 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
146 /// N) for the Nth user defined class.
149 /// SuperClasses - The super classes of this class. Note that for simplicities
150 /// sake user operands only record their immediate super class, while register
151 /// operands include all superclasses.
152 std::vector<ClassInfo*> SuperClasses;
154 /// Name - The full class name, suitable for use in an enum.
157 /// ClassName - The unadorned generic name for this class (e.g., Token).
158 std::string ClassName;
160 /// ValueName - The name of the value this class represents; for a token this
161 /// is the literal token string, for an operand it is the TableGen class (or
162 /// empty if this is a derived class).
163 std::string ValueName;
165 /// PredicateMethod - The name of the operand method to test whether the
166 /// operand matches this class; this is not valid for Token or register kinds.
167 std::string PredicateMethod;
169 /// RenderMethod - The name of the operand method to add this operand to an
170 /// MCInst; this is not valid for Token or register kinds.
171 std::string RenderMethod;
173 /// ParserMethod - The name of the operand method to do a target specific
174 /// parsing on the operand.
175 std::string ParserMethod;
177 /// For register classes, the records for all the registers in this class.
178 std::set<Record*> Registers;
181 /// isRegisterClass() - Check if this is a register class.
182 bool isRegisterClass() const {
183 return Kind >= RegisterClass0 && Kind < UserClass0;
186 /// isUserClass() - Check if this is a user defined class.
187 bool isUserClass() const {
188 return Kind >= UserClass0;
191 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
192 /// are related if they are in the same class hierarchy.
193 bool isRelatedTo(const ClassInfo &RHS) const {
194 // Tokens are only related to tokens.
195 if (Kind == Token || RHS.Kind == Token)
196 return Kind == Token && RHS.Kind == Token;
198 // Registers classes are only related to registers classes, and only if
199 // their intersection is non-empty.
200 if (isRegisterClass() || RHS.isRegisterClass()) {
201 if (!isRegisterClass() || !RHS.isRegisterClass())
204 std::set<Record*> Tmp;
205 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
206 std::set_intersection(Registers.begin(), Registers.end(),
207 RHS.Registers.begin(), RHS.Registers.end(),
213 // Otherwise we have two users operands; they are related if they are in the
214 // same class hierarchy.
216 // FIXME: This is an oversimplification, they should only be related if they
217 // intersect, however we don't have that information.
218 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
219 const ClassInfo *Root = this;
220 while (!Root->SuperClasses.empty())
221 Root = Root->SuperClasses.front();
223 const ClassInfo *RHSRoot = &RHS;
224 while (!RHSRoot->SuperClasses.empty())
225 RHSRoot = RHSRoot->SuperClasses.front();
227 return Root == RHSRoot;
230 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
231 bool isSubsetOf(const ClassInfo &RHS) const {
232 // This is a subset of RHS if it is the same class...
236 // ... or if any of its super classes are a subset of RHS.
237 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
238 ie = SuperClasses.end(); it != ie; ++it)
239 if ((*it)->isSubsetOf(RHS))
245 /// operator< - Compare two classes.
246 bool operator<(const ClassInfo &RHS) const {
250 // Unrelated classes can be ordered by kind.
251 if (!isRelatedTo(RHS))
252 return Kind < RHS.Kind;
256 llvm_unreachable("Invalid kind!");
259 // This class precedes the RHS if it is a proper subset of the RHS.
262 if (RHS.isSubsetOf(*this))
265 // Otherwise, order by name to ensure we have a total ordering.
266 return ValueName < RHS.ValueName;
271 /// MatchableInfo - Helper class for storing the necessary information for an
272 /// instruction or alias which is capable of being matched.
273 struct MatchableInfo {
275 /// Token - This is the token that the operand came from.
278 /// The unique class instance this operand should match.
281 /// The operand name this is, if anything.
284 /// The suboperand index within SrcOpName, or -1 for the entire operand.
287 /// Register record if this token is singleton register.
288 Record *SingletonReg;
290 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1),
294 /// ResOperand - This represents a single operand in the result instruction
295 /// generated by the match. In cases (like addressing modes) where a single
296 /// assembler operand expands to multiple MCOperands, this represents the
297 /// single assembler operand, not the MCOperand.
300 /// RenderAsmOperand - This represents an operand result that is
301 /// generated by calling the render method on the assembly operand. The
302 /// corresponding AsmOperand is specified by AsmOperandNum.
305 /// TiedOperand - This represents a result operand that is a duplicate of
306 /// a previous result operand.
309 /// ImmOperand - This represents an immediate value that is dumped into
313 /// RegOperand - This represents a fixed register that is dumped in.
318 /// This is the operand # in the AsmOperands list that this should be
320 unsigned AsmOperandNum;
322 /// TiedOperandNum - This is the (earlier) result operand that should be
324 unsigned TiedOperandNum;
326 /// ImmVal - This is the immediate value added to the instruction.
329 /// Register - This is the register record.
333 /// MINumOperands - The number of MCInst operands populated by this
335 unsigned MINumOperands;
337 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
339 X.Kind = RenderAsmOperand;
340 X.AsmOperandNum = AsmOpNum;
341 X.MINumOperands = NumOperands;
345 static ResOperand getTiedOp(unsigned TiedOperandNum) {
347 X.Kind = TiedOperand;
348 X.TiedOperandNum = TiedOperandNum;
353 static ResOperand getImmOp(int64_t Val) {
361 static ResOperand getRegOp(Record *Reg) {
370 /// AsmVariantID - Target's assembly syntax variant no.
373 /// TheDef - This is the definition of the instruction or InstAlias that this
374 /// matchable came from.
375 Record *const TheDef;
377 /// DefRec - This is the definition that it came from.
378 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
380 const CodeGenInstruction *getResultInst() const {
381 if (DefRec.is<const CodeGenInstruction*>())
382 return DefRec.get<const CodeGenInstruction*>();
383 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
386 /// ResOperands - This is the operand list that should be built for the result
388 SmallVector<ResOperand, 8> ResOperands;
390 /// AsmString - The assembly string for this instruction (with variants
391 /// removed), e.g. "movsx $src, $dst".
392 std::string AsmString;
394 /// Mnemonic - This is the first token of the matched instruction, its
398 /// AsmOperands - The textual operands that this instruction matches,
399 /// annotated with a class and where in the OperandList they were defined.
400 /// This directly corresponds to the tokenized AsmString after the mnemonic is
402 SmallVector<AsmOperand, 8> AsmOperands;
404 /// Predicates - The required subtarget features to match this instruction.
405 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
407 /// ConversionFnKind - The enum value which is passed to the generated
408 /// ConvertToMCInst to convert parsed operands into an MCInst for this
410 std::string ConversionFnKind;
412 MatchableInfo(const CodeGenInstruction &CGI)
413 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
414 AsmString(CGI.AsmString) {
417 MatchableInfo(const CodeGenInstAlias *Alias)
418 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
419 AsmString(Alias->AsmString) {
422 // Two-operand aliases clone from the main matchable, but mark the second
423 // operand as a tied operand of the first for purposes of the assembler.
424 void formTwoOperandAlias(StringRef Constraint);
426 void initialize(const AsmMatcherInfo &Info,
427 SmallPtrSet<Record*, 16> &SingletonRegisters,
428 int AsmVariantNo, std::string &RegisterPrefix);
430 /// validate - Return true if this matchable is a valid thing to match against
431 /// and perform a bunch of validity checking.
432 bool validate(StringRef CommentDelimiter, bool Hack) const;
434 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
435 /// if present, from specified token.
437 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
438 std::string &RegisterPrefix);
440 /// findAsmOperand - Find the AsmOperand with the specified name and
441 /// suboperand index.
442 int findAsmOperand(StringRef N, int SubOpIdx) const {
443 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
444 if (N == AsmOperands[i].SrcOpName &&
445 SubOpIdx == AsmOperands[i].SubOpIdx)
450 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
451 /// This does not check the suboperand index.
452 int findAsmOperandNamed(StringRef N) const {
453 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
454 if (N == AsmOperands[i].SrcOpName)
459 void buildInstructionResultOperands();
460 void buildAliasResultOperands();
462 /// operator< - Compare two matchables.
463 bool operator<(const MatchableInfo &RHS) const {
464 // The primary comparator is the instruction mnemonic.
465 if (Mnemonic != RHS.Mnemonic)
466 return Mnemonic < RHS.Mnemonic;
468 if (AsmOperands.size() != RHS.AsmOperands.size())
469 return AsmOperands.size() < RHS.AsmOperands.size();
471 // Compare lexicographically by operand. The matcher validates that other
472 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
473 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
474 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
476 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
483 /// couldMatchAmbiguouslyWith - Check whether this matchable could
484 /// ambiguously match the same set of operands as \arg RHS (without being a
485 /// strictly superior match).
486 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
487 // The primary comparator is the instruction mnemonic.
488 if (Mnemonic != RHS.Mnemonic)
491 // The number of operands is unambiguous.
492 if (AsmOperands.size() != RHS.AsmOperands.size())
495 // Otherwise, make sure the ordering of the two instructions is unambiguous
496 // by checking that either (a) a token or operand kind discriminates them,
497 // or (b) the ordering among equivalent kinds is consistent.
499 // Tokens and operand kinds are unambiguous (assuming a correct target
501 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
502 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
503 AsmOperands[i].Class->Kind == ClassInfo::Token)
504 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
505 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
508 // Otherwise, this operand could commute if all operands are equivalent, or
509 // there is a pair of operands that compare less than and a pair that
510 // compare greater than.
511 bool HasLT = false, HasGT = false;
512 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
513 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
515 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
519 return !(HasLT ^ HasGT);
525 void tokenizeAsmString(const AsmMatcherInfo &Info);
528 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
529 /// feature which participates in instruction matching.
530 struct SubtargetFeatureInfo {
531 /// \brief The predicate record for this feature.
534 /// \brief An unique index assigned to represent this feature.
537 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
539 /// \brief The name of the enumerated constant identifying this feature.
540 std::string getEnumName() const {
541 return "Feature_" + TheDef->getName();
545 struct OperandMatchEntry {
546 unsigned OperandMask;
550 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci,
553 X.OperandMask = opMask;
561 class AsmMatcherInfo {
564 RecordKeeper &Records;
566 /// The tablegen AsmParser record.
569 /// Target - The target information.
570 CodeGenTarget &Target;
572 /// The classes which are needed for matching.
573 std::vector<ClassInfo*> Classes;
575 /// The information on the matchables to match.
576 std::vector<MatchableInfo*> Matchables;
578 /// Info for custom matching operands by user defined methods.
579 std::vector<OperandMatchEntry> OperandMatchInfo;
581 /// Map of Register records to their class information.
582 std::map<Record*, ClassInfo*> RegisterClasses;
584 /// Map of Predicate records to their subtarget information.
585 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
588 /// Map of token to class information which has already been constructed.
589 std::map<std::string, ClassInfo*> TokenClasses;
591 /// Map of RegisterClass records to their class information.
592 std::map<Record*, ClassInfo*> RegisterClassClasses;
594 /// Map of AsmOperandClass records to their class information.
595 std::map<Record*, ClassInfo*> AsmOperandClasses;
598 /// getTokenClass - Lookup or create the class for the given token.
599 ClassInfo *getTokenClass(StringRef Token);
601 /// getOperandClass - Lookup or create the class for the given operand.
602 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
604 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
606 /// buildRegisterClasses - Build the ClassInfo* instances for register
608 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
610 /// buildOperandClasses - Build the ClassInfo* instances for user defined
612 void buildOperandClasses();
614 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
616 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
617 MatchableInfo::AsmOperand &Op);
620 AsmMatcherInfo(Record *AsmParser,
621 CodeGenTarget &Target,
622 RecordKeeper &Records);
624 /// buildInfo - Construct the various tables used during matching.
627 /// buildOperandMatchInfo - Build the necessary information to handle user
628 /// defined operand parsing methods.
629 void buildOperandMatchInfo();
631 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
633 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
634 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
635 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
636 SubtargetFeatures.find(Def);
637 return I == SubtargetFeatures.end() ? 0 : I->second;
640 RecordKeeper &getRecords() const {
647 void MatchableInfo::dump() {
648 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
650 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
651 AsmOperand &Op = AsmOperands[i];
652 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
653 errs() << '\"' << Op.Token << "\"\n";
657 static std::pair<StringRef, StringRef>
658 parseTwoOperandConstraint(StringRef S, SMLoc Loc) {
659 // Split via the '='.
660 std::pair<StringRef, StringRef> Ops = S.split('=');
661 if (Ops.second == "")
662 throw TGError(Loc, "missing '=' in two-operand alias constraint");
663 // Trim whitespace and the leading '$' on the operand names.
664 size_t start = Ops.first.find_first_of('$');
665 if (start == std::string::npos)
666 throw TGError(Loc, "expected '$' prefix on asm operand name");
667 Ops.first = Ops.first.slice(start + 1, std::string::npos);
668 size_t end = Ops.first.find_last_of(" \t");
669 Ops.first = Ops.first.slice(0, end);
670 // Now the second operand.
671 start = Ops.second.find_first_of('$');
672 if (start == std::string::npos)
673 throw TGError(Loc, "expected '$' prefix on asm operand name");
674 Ops.second = Ops.second.slice(start + 1, std::string::npos);
675 end = Ops.second.find_last_of(" \t");
676 Ops.first = Ops.first.slice(0, end);
680 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
681 // Figure out which operands are aliased and mark them as tied.
682 std::pair<StringRef, StringRef> Ops =
683 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
685 // Find the AsmOperands that refer to the operands we're aliasing.
686 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
687 int DstAsmOperand = findAsmOperandNamed(Ops.second);
688 if (SrcAsmOperand == -1)
689 throw TGError(TheDef->getLoc(),
690 "unknown source two-operand alias operand '" +
691 Ops.first.str() + "'.");
692 if (DstAsmOperand == -1)
693 throw TGError(TheDef->getLoc(),
694 "unknown destination two-operand alias operand '" +
695 Ops.second.str() + "'.");
697 // Find the ResOperand that refers to the operand we're aliasing away
698 // and update it to refer to the combined operand instead.
699 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
700 ResOperand &Op = ResOperands[i];
701 if (Op.Kind == ResOperand::RenderAsmOperand &&
702 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
703 Op.AsmOperandNum = DstAsmOperand;
707 // Remove the AsmOperand for the alias operand.
708 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
709 // Adjust the ResOperand references to any AsmOperands that followed
710 // the one we just deleted.
711 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
712 ResOperand &Op = ResOperands[i];
715 // Nothing to do for operands that don't reference AsmOperands.
717 case ResOperand::RenderAsmOperand:
718 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
721 case ResOperand::TiedOperand:
722 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
729 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
730 SmallPtrSet<Record*, 16> &SingletonRegisters,
731 int AsmVariantNo, std::string &RegisterPrefix) {
732 AsmVariantID = AsmVariantNo;
734 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
736 tokenizeAsmString(Info);
738 // Compute the require features.
739 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
740 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
741 if (SubtargetFeatureInfo *Feature =
742 Info.getSubtargetFeature(Predicates[i]))
743 RequiredFeatures.push_back(Feature);
745 // Collect singleton registers, if used.
746 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
747 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
748 if (Record *Reg = AsmOperands[i].SingletonReg)
749 SingletonRegisters.insert(Reg);
753 /// tokenizeAsmString - Tokenize a simplified assembly string.
754 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
755 StringRef String = AsmString;
758 for (unsigned i = 0, e = String.size(); i != e; ++i) {
768 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
771 if (!isspace(String[i]) && String[i] != ',')
772 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
778 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
782 assert(i != String.size() && "Invalid quoted character");
783 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
789 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
793 // If this isn't "${", treat like a normal token.
794 if (i + 1 == String.size() || String[i + 1] != '{') {
799 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
800 assert(End != String.end() && "Missing brace in operand reference!");
801 size_t EndPos = End - String.begin();
802 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
810 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
819 if (InTok && Prev != String.size())
820 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
822 // The first token of the instruction is the mnemonic, which must be a
823 // simple string, not a $foo variable or a singleton register.
824 if (AsmOperands.empty())
825 throw TGError(TheDef->getLoc(),
826 "Instruction '" + TheDef->getName() + "' has no tokens");
827 Mnemonic = AsmOperands[0].Token;
828 // FIXME : Check and raise an error if it is a register.
829 if (Mnemonic[0] == '$')
830 throw TGError(TheDef->getLoc(),
831 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
833 // Remove the first operand, it is tracked in the mnemonic field.
834 AsmOperands.erase(AsmOperands.begin());
837 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
838 // Reject matchables with no .s string.
839 if (AsmString.empty())
840 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
842 // Reject any matchables with a newline in them, they should be marked
843 // isCodeGenOnly if they are pseudo instructions.
844 if (AsmString.find('\n') != std::string::npos)
845 throw TGError(TheDef->getLoc(),
846 "multiline instruction is not valid for the asmparser, "
847 "mark it isCodeGenOnly");
849 // Remove comments from the asm string. We know that the asmstring only
851 if (!CommentDelimiter.empty() &&
852 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
853 throw TGError(TheDef->getLoc(),
854 "asmstring for instruction has comment character in it, "
855 "mark it isCodeGenOnly");
857 // Reject matchables with operand modifiers, these aren't something we can
858 // handle, the target should be refactored to use operands instead of
861 // Also, check for instructions which reference the operand multiple times;
862 // this implies a constraint we would not honor.
863 std::set<std::string> OperandNames;
864 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
865 StringRef Tok = AsmOperands[i].Token;
866 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
867 throw TGError(TheDef->getLoc(),
868 "matchable with operand modifier '" + Tok.str() +
869 "' not supported by asm matcher. Mark isCodeGenOnly!");
871 // Verify that any operand is only mentioned once.
872 // We reject aliases and ignore instructions for now.
873 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
875 throw TGError(TheDef->getLoc(),
876 "ERROR: matchable with tied operand '" + Tok.str() +
877 "' can never be matched!");
878 // FIXME: Should reject these. The ARM backend hits this with $lane in a
879 // bunch of instructions. It is unclear what the right answer is.
881 errs() << "warning: '" << TheDef->getName() << "': "
882 << "ignoring instruction with tied operand '"
883 << Tok.str() << "'\n";
892 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
893 /// if present, from specified token.
895 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
896 const AsmMatcherInfo &Info,
897 std::string &RegisterPrefix) {
898 StringRef Tok = AsmOperands[OperandNo].Token;
899 if (RegisterPrefix.empty()) {
900 std::string LoweredTok = Tok.lower();
901 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
902 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
906 if (!Tok.startswith(RegisterPrefix))
909 StringRef RegName = Tok.substr(RegisterPrefix.size());
910 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
911 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
913 // If there is no register prefix (i.e. "%" in "%eax"), then this may
914 // be some random non-register token, just ignore it.
918 static std::string getEnumNameForToken(StringRef Str) {
921 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
923 case '*': Res += "_STAR_"; break;
924 case '%': Res += "_PCT_"; break;
925 case ':': Res += "_COLON_"; break;
926 case '!': Res += "_EXCLAIM_"; break;
927 case '.': Res += "_DOT_"; break;
932 Res += "_" + utostr((unsigned) *it) + "_";
939 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
940 ClassInfo *&Entry = TokenClasses[Token];
943 Entry = new ClassInfo();
944 Entry->Kind = ClassInfo::Token;
945 Entry->ClassName = "Token";
946 Entry->Name = "MCK_" + getEnumNameForToken(Token);
947 Entry->ValueName = Token;
948 Entry->PredicateMethod = "<invalid>";
949 Entry->RenderMethod = "<invalid>";
950 Entry->ParserMethod = "";
951 Classes.push_back(Entry);
958 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
960 Record *Rec = OI.Rec;
962 Rec = dynamic_cast<DefInit*>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
963 return getOperandClass(Rec, SubOpIdx);
967 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
968 if (Rec->isSubClassOf("RegisterOperand")) {
969 // RegisterOperand may have an associated ParserMatchClass. If it does,
970 // use it, else just fall back to the underlying register class.
971 const RecordVal *R = Rec->getValue("ParserMatchClass");
972 if (R == 0 || R->getValue() == 0)
973 throw "Record `" + Rec->getName() +
974 "' does not have a ParserMatchClass!\n";
976 if (DefInit *DI= dynamic_cast<DefInit*>(R->getValue())) {
977 Record *MatchClass = DI->getDef();
978 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
982 // No custom match class. Just use the register class.
983 Record *ClassRec = Rec->getValueAsDef("RegClass");
985 throw TGError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
986 "' has no associated register class!\n");
987 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
989 throw TGError(Rec->getLoc(), "register class has no class info!");
993 if (Rec->isSubClassOf("RegisterClass")) {
994 if (ClassInfo *CI = RegisterClassClasses[Rec])
996 throw TGError(Rec->getLoc(), "register class has no class info!");
999 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1000 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1001 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1004 throw TGError(Rec->getLoc(), "operand has no match class!");
1007 void AsmMatcherInfo::
1008 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
1009 const std::vector<CodeGenRegister*> &Registers =
1010 Target.getRegBank().getRegisters();
1011 ArrayRef<CodeGenRegisterClass*> RegClassList =
1012 Target.getRegBank().getRegClasses();
1014 // The register sets used for matching.
1015 std::set< std::set<Record*> > RegisterSets;
1017 // Gather the defined sets.
1018 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
1019 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
1020 RegisterSets.insert(std::set<Record*>(
1021 (*it)->getOrder().begin(), (*it)->getOrder().end()));
1023 // Add any required singleton sets.
1024 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1025 ie = SingletonRegisters.end(); it != ie; ++it) {
1027 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
1030 // Introduce derived sets where necessary (when a register does not determine
1031 // a unique register set class), and build the mapping of registers to the set
1032 // they should classify to.
1033 std::map<Record*, std::set<Record*> > RegisterMap;
1034 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
1035 ie = Registers.end(); it != ie; ++it) {
1036 const CodeGenRegister &CGR = **it;
1037 // Compute the intersection of all sets containing this register.
1038 std::set<Record*> ContainingSet;
1040 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1041 ie = RegisterSets.end(); it != ie; ++it) {
1042 if (!it->count(CGR.TheDef))
1045 if (ContainingSet.empty()) {
1046 ContainingSet = *it;
1050 std::set<Record*> Tmp;
1051 std::swap(Tmp, ContainingSet);
1052 std::insert_iterator< std::set<Record*> > II(ContainingSet,
1053 ContainingSet.begin());
1054 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
1057 if (!ContainingSet.empty()) {
1058 RegisterSets.insert(ContainingSet);
1059 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1063 // Construct the register classes.
1064 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
1066 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1067 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
1068 ClassInfo *CI = new ClassInfo();
1069 CI->Kind = ClassInfo::RegisterClass0 + Index;
1070 CI->ClassName = "Reg" + utostr(Index);
1071 CI->Name = "MCK_Reg" + utostr(Index);
1073 CI->PredicateMethod = ""; // unused
1074 CI->RenderMethod = "addRegOperands";
1075 CI->Registers = *it;
1076 Classes.push_back(CI);
1077 RegisterSetClasses.insert(std::make_pair(*it, CI));
1080 // Find the superclasses; we could compute only the subgroup lattice edges,
1081 // but there isn't really a point.
1082 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1083 ie = RegisterSets.end(); it != ie; ++it) {
1084 ClassInfo *CI = RegisterSetClasses[*it];
1085 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
1086 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
1088 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
1089 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
1092 // Name the register classes which correspond to a user defined RegisterClass.
1093 for (ArrayRef<CodeGenRegisterClass*>::const_iterator
1094 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
1095 const CodeGenRegisterClass &RC = **it;
1096 // Def will be NULL for non-user defined register classes.
1097 Record *Def = RC.getDef();
1100 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(),
1101 RC.getOrder().end())];
1102 if (CI->ValueName.empty()) {
1103 CI->ClassName = RC.getName();
1104 CI->Name = "MCK_" + RC.getName();
1105 CI->ValueName = RC.getName();
1107 CI->ValueName = CI->ValueName + "," + RC.getName();
1109 RegisterClassClasses.insert(std::make_pair(Def, CI));
1112 // Populate the map for individual registers.
1113 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
1114 ie = RegisterMap.end(); it != ie; ++it)
1115 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1117 // Name the register classes which correspond to singleton registers.
1118 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1119 ie = SingletonRegisters.end(); it != ie; ++it) {
1121 ClassInfo *CI = RegisterClasses[Rec];
1122 assert(CI && "Missing singleton register class info!");
1124 if (CI->ValueName.empty()) {
1125 CI->ClassName = Rec->getName();
1126 CI->Name = "MCK_" + Rec->getName();
1127 CI->ValueName = Rec->getName();
1129 CI->ValueName = CI->ValueName + "," + Rec->getName();
1133 void AsmMatcherInfo::buildOperandClasses() {
1134 std::vector<Record*> AsmOperands =
1135 Records.getAllDerivedDefinitions("AsmOperandClass");
1137 // Pre-populate AsmOperandClasses map.
1138 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1139 ie = AsmOperands.end(); it != ie; ++it)
1140 AsmOperandClasses[*it] = new ClassInfo();
1143 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1144 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
1145 ClassInfo *CI = AsmOperandClasses[*it];
1146 CI->Kind = ClassInfo::UserClass0 + Index;
1148 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
1149 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1150 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
1152 PrintError((*it)->getLoc(), "Invalid super class reference!");
1156 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1158 PrintError((*it)->getLoc(), "Invalid super class reference!");
1160 CI->SuperClasses.push_back(SC);
1162 CI->ClassName = (*it)->getValueAsString("Name");
1163 CI->Name = "MCK_" + CI->ClassName;
1164 CI->ValueName = (*it)->getName();
1166 // Get or construct the predicate method name.
1167 Init *PMName = (*it)->getValueInit("PredicateMethod");
1168 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
1169 CI->PredicateMethod = SI->getValue();
1171 assert(dynamic_cast<UnsetInit*>(PMName) &&
1172 "Unexpected PredicateMethod field!");
1173 CI->PredicateMethod = "is" + CI->ClassName;
1176 // Get or construct the render method name.
1177 Init *RMName = (*it)->getValueInit("RenderMethod");
1178 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
1179 CI->RenderMethod = SI->getValue();
1181 assert(dynamic_cast<UnsetInit*>(RMName) &&
1182 "Unexpected RenderMethod field!");
1183 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1186 // Get the parse method name or leave it as empty.
1187 Init *PRMName = (*it)->getValueInit("ParserMethod");
1188 if (StringInit *SI = dynamic_cast<StringInit*>(PRMName))
1189 CI->ParserMethod = SI->getValue();
1191 AsmOperandClasses[*it] = CI;
1192 Classes.push_back(CI);
1196 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1197 CodeGenTarget &target,
1198 RecordKeeper &records)
1199 : Records(records), AsmParser(asmParser), Target(target) {
1202 /// buildOperandMatchInfo - Build the necessary information to handle user
1203 /// defined operand parsing methods.
1204 void AsmMatcherInfo::buildOperandMatchInfo() {
1206 /// Map containing a mask with all operands indices that can be found for
1207 /// that class inside a instruction.
1208 std::map<ClassInfo*, unsigned> OpClassMask;
1210 for (std::vector<MatchableInfo*>::const_iterator it =
1211 Matchables.begin(), ie = Matchables.end();
1213 MatchableInfo &II = **it;
1214 OpClassMask.clear();
1216 // Keep track of all operands of this instructions which belong to the
1218 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1219 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1220 if (Op.Class->ParserMethod.empty())
1222 unsigned &OperandMask = OpClassMask[Op.Class];
1223 OperandMask |= (1 << i);
1226 // Generate operand match info for each mnemonic/operand class pair.
1227 for (std::map<ClassInfo*, unsigned>::iterator iit = OpClassMask.begin(),
1228 iie = OpClassMask.end(); iit != iie; ++iit) {
1229 unsigned OpMask = iit->second;
1230 ClassInfo *CI = iit->first;
1231 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask));
1236 void AsmMatcherInfo::buildInfo() {
1237 // Build information about all of the AssemblerPredicates.
1238 std::vector<Record*> AllPredicates =
1239 Records.getAllDerivedDefinitions("Predicate");
1240 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1241 Record *Pred = AllPredicates[i];
1242 // Ignore predicates that are not intended for the assembler.
1243 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1246 if (Pred->getName().empty())
1247 throw TGError(Pred->getLoc(), "Predicate has no name!");
1249 unsigned FeatureNo = SubtargetFeatures.size();
1250 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1251 assert(FeatureNo < 32 && "Too many subtarget features!");
1254 // Parse the instructions; we need to do this first so that we can gather the
1255 // singleton register classes.
1256 SmallPtrSet<Record*, 16> SingletonRegisters;
1257 unsigned VariantCount = Target.getAsmParserVariantCount();
1258 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1259 Record *AsmVariant = Target.getAsmParserVariant(VC);
1260 std::string CommentDelimiter =
1261 AsmVariant->getValueAsString("CommentDelimiter");
1262 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1263 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1265 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1266 E = Target.inst_end(); I != E; ++I) {
1267 const CodeGenInstruction &CGI = **I;
1269 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1270 // filter the set of instructions we consider.
1271 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1274 // Ignore "codegen only" instructions.
1275 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1278 // Validate the operand list to ensure we can handle this instruction.
1279 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1280 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1282 // Validate tied operands.
1283 if (OI.getTiedRegister() != -1) {
1284 // If we have a tied operand that consists of multiple MCOperands,
1285 // reject it. We reject aliases and ignore instructions for now.
1286 if (OI.MINumOperands != 1) {
1287 // FIXME: Should reject these. The ARM backend hits this with $lane
1288 // in a bunch of instructions. The right answer is unclear.
1290 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1291 << "ignoring instruction with multi-operand tied operand '"
1292 << OI.Name << "'\n";
1299 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1301 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1303 // Ignore instructions which shouldn't be matched and diagnose invalid
1304 // instruction definitions with an error.
1305 if (!II->validate(CommentDelimiter, true))
1308 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1310 // FIXME: This is a total hack.
1311 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1312 StringRef(II->TheDef->getName()).endswith("_Int"))
1315 Matchables.push_back(II.take());
1318 // Parse all of the InstAlias definitions and stick them in the list of
1320 std::vector<Record*> AllInstAliases =
1321 Records.getAllDerivedDefinitions("InstAlias");
1322 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1323 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1325 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1326 // filter the set of instruction aliases we consider, based on the target
1328 if (!StringRef(Alias->ResultInst->TheDef->getName())
1329 .startswith( MatchPrefix))
1332 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1334 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1336 // Validate the alias definitions.
1337 II->validate(CommentDelimiter, false);
1339 Matchables.push_back(II.take());
1343 // Build info for the register classes.
1344 buildRegisterClasses(SingletonRegisters);
1346 // Build info for the user defined assembly operand classes.
1347 buildOperandClasses();
1349 // Build the information about matchables, now that we have fully formed
1351 std::vector<MatchableInfo*> NewMatchables;
1352 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1353 ie = Matchables.end(); it != ie; ++it) {
1354 MatchableInfo *II = *it;
1356 // Parse the tokens after the mnemonic.
1357 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1358 // don't precompute the loop bound.
1359 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1360 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1361 StringRef Token = Op.Token;
1363 // Check for singleton registers.
1364 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1365 Op.Class = RegisterClasses[RegRecord];
1366 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1367 "Unexpected class for singleton register");
1371 // Check for simple tokens.
1372 if (Token[0] != '$') {
1373 Op.Class = getTokenClass(Token);
1377 if (Token.size() > 1 && isdigit(Token[1])) {
1378 Op.Class = getTokenClass(Token);
1382 // Otherwise this is an operand reference.
1383 StringRef OperandName;
1384 if (Token[1] == '{')
1385 OperandName = Token.substr(2, Token.size() - 3);
1387 OperandName = Token.substr(1);
1389 if (II->DefRec.is<const CodeGenInstruction*>())
1390 buildInstructionOperandReference(II, OperandName, i);
1392 buildAliasOperandReference(II, OperandName, Op);
1395 if (II->DefRec.is<const CodeGenInstruction*>()) {
1396 II->buildInstructionResultOperands();
1397 // If the instruction has a two-operand alias, build up the
1398 // matchable here. We'll add them in bulk at the end to avoid
1399 // confusing this loop.
1400 std::string Constraint =
1401 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1402 if (Constraint != "") {
1403 // Start by making a copy of the original matchable.
1404 OwningPtr<MatchableInfo> AliasII(new MatchableInfo(*II));
1406 // Adjust it to be a two-operand alias.
1407 AliasII->formTwoOperandAlias(Constraint);
1409 // Add the alias to the matchables list.
1410 NewMatchables.push_back(AliasII.take());
1413 II->buildAliasResultOperands();
1415 if (!NewMatchables.empty())
1416 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1417 NewMatchables.end());
1419 // Process token alias definitions and set up the associated superclass
1421 std::vector<Record*> AllTokenAliases =
1422 Records.getAllDerivedDefinitions("TokenAlias");
1423 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1424 Record *Rec = AllTokenAliases[i];
1425 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1426 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1427 if (FromClass == ToClass)
1428 throw TGError(Rec->getLoc(),
1429 "error: Destination value identical to source value.");
1430 FromClass->SuperClasses.push_back(ToClass);
1433 // Reorder classes so that classes precede super classes.
1434 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1437 /// buildInstructionOperandReference - The specified operand is a reference to a
1438 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1439 void AsmMatcherInfo::
1440 buildInstructionOperandReference(MatchableInfo *II,
1441 StringRef OperandName,
1442 unsigned AsmOpIdx) {
1443 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1444 const CGIOperandList &Operands = CGI.Operands;
1445 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1447 // Map this token to an operand.
1449 if (!Operands.hasOperandNamed(OperandName, Idx))
1450 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1451 OperandName.str() + "'");
1453 // If the instruction operand has multiple suboperands, but the parser
1454 // match class for the asm operand is still the default "ImmAsmOperand",
1455 // then handle each suboperand separately.
1456 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1457 Record *Rec = Operands[Idx].Rec;
1458 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1459 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1460 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1461 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1462 StringRef Token = Op->Token; // save this in case Op gets moved
1463 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1464 MatchableInfo::AsmOperand NewAsmOp(Token);
1465 NewAsmOp.SubOpIdx = SI;
1466 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1468 // Replace Op with first suboperand.
1469 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1474 // Set up the operand class.
1475 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1477 // If the named operand is tied, canonicalize it to the untied operand.
1478 // For example, something like:
1479 // (outs GPR:$dst), (ins GPR:$src)
1480 // with an asmstring of
1482 // we want to canonicalize to:
1484 // so that we know how to provide the $dst operand when filling in the result.
1485 int OITied = Operands[Idx].getTiedRegister();
1487 // The tied operand index is an MIOperand index, find the operand that
1489 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1490 OperandName = Operands[Idx.first].Name;
1491 Op->SubOpIdx = Idx.second;
1494 Op->SrcOpName = OperandName;
1497 /// buildAliasOperandReference - When parsing an operand reference out of the
1498 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1499 /// operand reference is by looking it up in the result pattern definition.
1500 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1501 StringRef OperandName,
1502 MatchableInfo::AsmOperand &Op) {
1503 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1505 // Set up the operand class.
1506 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1507 if (CGA.ResultOperands[i].isRecord() &&
1508 CGA.ResultOperands[i].getName() == OperandName) {
1509 // It's safe to go with the first one we find, because CodeGenInstAlias
1510 // validates that all operands with the same name have the same record.
1511 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1512 // Use the match class from the Alias definition, not the
1513 // destination instruction, as we may have an immediate that's
1514 // being munged by the match class.
1515 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1517 Op.SrcOpName = OperandName;
1521 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1522 OperandName.str() + "'");
1525 void MatchableInfo::buildInstructionResultOperands() {
1526 const CodeGenInstruction *ResultInst = getResultInst();
1528 // Loop over all operands of the result instruction, determining how to
1530 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1531 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1533 // If this is a tied operand, just copy from the previously handled operand.
1534 int TiedOp = OpInfo.getTiedRegister();
1536 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1540 // Find out what operand from the asmparser this MCInst operand comes from.
1541 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1542 if (OpInfo.Name.empty() || SrcOperand == -1)
1543 throw TGError(TheDef->getLoc(), "Instruction '" +
1544 TheDef->getName() + "' has operand '" + OpInfo.Name +
1545 "' that doesn't appear in asm string!");
1547 // Check if the one AsmOperand populates the entire operand.
1548 unsigned NumOperands = OpInfo.MINumOperands;
1549 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1550 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1554 // Add a separate ResOperand for each suboperand.
1555 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1556 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1557 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1558 "unexpected AsmOperands for suboperands");
1559 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1564 void MatchableInfo::buildAliasResultOperands() {
1565 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1566 const CodeGenInstruction *ResultInst = getResultInst();
1568 // Loop over all operands of the result instruction, determining how to
1570 unsigned AliasOpNo = 0;
1571 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1572 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1573 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1575 // If this is a tied operand, just copy from the previously handled operand.
1576 int TiedOp = OpInfo->getTiedRegister();
1578 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1582 // Handle all the suboperands for this operand.
1583 const std::string &OpName = OpInfo->Name;
1584 for ( ; AliasOpNo < LastOpNo &&
1585 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1586 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1588 // Find out what operand from the asmparser that this MCInst operand
1590 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1591 case CodeGenInstAlias::ResultOperand::K_Record: {
1592 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1593 int SrcOperand = findAsmOperand(Name, SubIdx);
1594 if (SrcOperand == -1)
1595 throw TGError(TheDef->getLoc(), "Instruction '" +
1596 TheDef->getName() + "' has operand '" + OpName +
1597 "' that doesn't appear in asm string!");
1598 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1599 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1603 case CodeGenInstAlias::ResultOperand::K_Imm: {
1604 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1605 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1608 case CodeGenInstAlias::ResultOperand::K_Reg: {
1609 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1610 ResOperands.push_back(ResOperand::getRegOp(Reg));
1618 static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName,
1619 std::vector<MatchableInfo*> &Infos,
1621 // Write the convert function to a separate stream, so we can drop it after
1623 std::string ConvertFnBody;
1624 raw_string_ostream CvtOS(ConvertFnBody);
1626 // Function we have already generated.
1627 std::set<std::string> GeneratedFns;
1629 // Start the unified conversion function.
1630 CvtOS << "bool " << Target.getName() << ClassName << "::\n";
1631 CvtOS << "ConvertToMCInst(unsigned Kind, MCInst &Inst, "
1632 << "unsigned Opcode,\n"
1633 << " const SmallVectorImpl<MCParsedAsmOperand*"
1634 << "> &Operands) {\n";
1635 CvtOS << " Inst.setOpcode(Opcode);\n";
1636 CvtOS << " switch (Kind) {\n";
1637 CvtOS << " default:\n";
1639 // Start the enum, which we will generate inline.
1641 OS << "// Unified function for converting operands to MCInst instances.\n\n";
1642 OS << "enum ConversionKind {\n";
1644 // TargetOperandClass - This is the target's operand class, like X86Operand.
1645 std::string TargetOperandClass = Target.getName() + "Operand";
1647 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1648 ie = Infos.end(); it != ie; ++it) {
1649 MatchableInfo &II = **it;
1651 // Check if we have a custom match function.
1652 std::string AsmMatchConverter =
1653 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1654 if (!AsmMatchConverter.empty()) {
1655 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1656 II.ConversionFnKind = Signature;
1658 // Check if we have already generated this signature.
1659 if (!GeneratedFns.insert(Signature).second)
1662 // If not, emit it now. Add to the enum list.
1663 OS << " " << Signature << ",\n";
1665 CvtOS << " case " << Signature << ":\n";
1666 CvtOS << " return " << AsmMatchConverter
1667 << "(Inst, Opcode, Operands);\n";
1671 // Build the conversion function signature.
1672 std::string Signature = "Convert";
1673 std::string CaseBody;
1674 raw_string_ostream CaseOS(CaseBody);
1676 // Compute the convert enum and the case body.
1677 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1678 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1680 // Generate code to populate each result operand.
1681 switch (OpInfo.Kind) {
1682 case MatchableInfo::ResOperand::RenderAsmOperand: {
1683 // This comes from something we parsed.
1684 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1686 // Registers are always converted the same, don't duplicate the
1687 // conversion function based on them.
1689 if (Op.Class->isRegisterClass())
1692 Signature += Op.Class->ClassName;
1693 Signature += utostr(OpInfo.MINumOperands);
1694 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1696 CaseOS << " ((" << TargetOperandClass << "*)Operands["
1697 << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod
1698 << "(Inst, " << OpInfo.MINumOperands << ");\n";
1702 case MatchableInfo::ResOperand::TiedOperand: {
1703 // If this operand is tied to a previous one, just copy the MCInst
1704 // operand from the earlier one.We can only tie single MCOperand values.
1705 //assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1706 unsigned TiedOp = OpInfo.TiedOperandNum;
1707 assert(i > TiedOp && "Tied operand precedes its target!");
1708 CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
1709 Signature += "__Tie" + utostr(TiedOp);
1712 case MatchableInfo::ResOperand::ImmOperand: {
1713 int64_t Val = OpInfo.ImmVal;
1714 CaseOS << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n";
1715 Signature += "__imm" + itostr(Val);
1718 case MatchableInfo::ResOperand::RegOperand: {
1719 if (OpInfo.Register == 0) {
1720 CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
1721 Signature += "__reg0";
1723 std::string N = getQualifiedName(OpInfo.Register);
1724 CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n";
1725 Signature += "__reg" + OpInfo.Register->getName();
1731 II.ConversionFnKind = Signature;
1733 // Check if we have already generated this signature.
1734 if (!GeneratedFns.insert(Signature).second)
1737 // If not, emit it now. Add to the enum list.
1738 OS << " " << Signature << ",\n";
1740 CvtOS << " case " << Signature << ":\n";
1741 CvtOS << CaseOS.str();
1742 CvtOS << " return true;\n";
1745 // Finish the convert function.
1748 CvtOS << " return false;\n";
1751 // Finish the enum, and drop the convert function after it.
1753 OS << " NumConversionVariants\n";
1759 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1760 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1761 std::vector<ClassInfo*> &Infos,
1763 OS << "namespace {\n\n";
1765 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1766 << "/// instruction matching.\n";
1767 OS << "enum MatchClassKind {\n";
1768 OS << " InvalidMatchClass = 0,\n";
1769 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1770 ie = Infos.end(); it != ie; ++it) {
1771 ClassInfo &CI = **it;
1772 OS << " " << CI.Name << ", // ";
1773 if (CI.Kind == ClassInfo::Token) {
1774 OS << "'" << CI.ValueName << "'\n";
1775 } else if (CI.isRegisterClass()) {
1776 if (!CI.ValueName.empty())
1777 OS << "register class '" << CI.ValueName << "'\n";
1779 OS << "derived register class\n";
1781 OS << "user defined class '" << CI.ValueName << "'\n";
1784 OS << " NumMatchClassKinds\n";
1790 /// emitValidateOperandClass - Emit the function to validate an operand class.
1791 static void emitValidateOperandClass(AsmMatcherInfo &Info,
1793 OS << "static bool validateOperandClass(MCParsedAsmOperand *GOp, "
1794 << "MatchClassKind Kind) {\n";
1795 OS << " " << Info.Target.getName() << "Operand &Operand = *("
1796 << Info.Target.getName() << "Operand*)GOp;\n";
1798 // The InvalidMatchClass is not to match any operand.
1799 OS << " if (Kind == InvalidMatchClass)\n";
1800 OS << " return false;\n\n";
1802 // Check for Token operands first.
1803 OS << " if (Operand.isToken())\n";
1804 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind);"
1807 // Check for register operands, including sub-classes.
1808 OS << " if (Operand.isReg()) {\n";
1809 OS << " MatchClassKind OpKind;\n";
1810 OS << " switch (Operand.getReg()) {\n";
1811 OS << " default: OpKind = InvalidMatchClass; break;\n";
1812 for (std::map<Record*, ClassInfo*>::iterator
1813 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1815 OS << " case " << Info.Target.getName() << "::"
1816 << it->first->getName() << ": OpKind = " << it->second->Name
1819 OS << " return isSubclass(OpKind, Kind);\n";
1822 // Check the user classes. We don't care what order since we're only
1823 // actually matching against one of them.
1824 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1825 ie = Info.Classes.end(); it != ie; ++it) {
1826 ClassInfo &CI = **it;
1828 if (!CI.isUserClass())
1831 OS << " // '" << CI.ClassName << "' class\n";
1832 OS << " if (Kind == " << CI.Name
1833 << " && Operand." << CI.PredicateMethod << "()) {\n";
1834 OS << " return true;\n";
1838 OS << " return false;\n";
1842 /// emitIsSubclass - Emit the subclass predicate function.
1843 static void emitIsSubclass(CodeGenTarget &Target,
1844 std::vector<ClassInfo*> &Infos,
1846 OS << "/// isSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1847 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
1848 OS << " if (A == B)\n";
1849 OS << " return true;\n\n";
1851 OS << " switch (A) {\n";
1852 OS << " default:\n";
1853 OS << " return false;\n";
1854 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1855 ie = Infos.end(); it != ie; ++it) {
1856 ClassInfo &A = **it;
1858 std::vector<StringRef> SuperClasses;
1859 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1860 ie = Infos.end(); it != ie; ++it) {
1861 ClassInfo &B = **it;
1863 if (&A != &B && A.isSubsetOf(B))
1864 SuperClasses.push_back(B.Name);
1867 if (SuperClasses.empty())
1870 OS << "\n case " << A.Name << ":\n";
1872 if (SuperClasses.size() == 1) {
1873 OS << " return B == " << SuperClasses.back() << ";\n";
1877 OS << " switch (B) {\n";
1878 OS << " default: return false;\n";
1879 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1880 OS << " case " << SuperClasses[i] << ": return true;\n";
1887 /// emitMatchTokenString - Emit the function to match a token string to the
1888 /// appropriate match class value.
1889 static void emitMatchTokenString(CodeGenTarget &Target,
1890 std::vector<ClassInfo*> &Infos,
1892 // Construct the match list.
1893 std::vector<StringMatcher::StringPair> Matches;
1894 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1895 ie = Infos.end(); it != ie; ++it) {
1896 ClassInfo &CI = **it;
1898 if (CI.Kind == ClassInfo::Token)
1899 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1900 "return " + CI.Name + ";"));
1903 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
1905 StringMatcher("Name", Matches, OS).Emit();
1907 OS << " return InvalidMatchClass;\n";
1911 /// emitMatchRegisterName - Emit the function to match a string to the target
1912 /// specific register enum.
1913 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1915 // Construct the match list.
1916 std::vector<StringMatcher::StringPair> Matches;
1917 const std::vector<CodeGenRegister*> &Regs =
1918 Target.getRegBank().getRegisters();
1919 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1920 const CodeGenRegister *Reg = Regs[i];
1921 if (Reg->TheDef->getValueAsString("AsmName").empty())
1924 Matches.push_back(StringMatcher::StringPair(
1925 Reg->TheDef->getValueAsString("AsmName"),
1926 "return " + utostr(Reg->EnumValue) + ";"));
1929 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1931 StringMatcher("Name", Matches, OS).Emit();
1933 OS << " return 0;\n";
1937 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1939 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1941 OS << "// Flags for subtarget features that participate in "
1942 << "instruction matching.\n";
1943 OS << "enum SubtargetFeatureFlag {\n";
1944 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1945 it = Info.SubtargetFeatures.begin(),
1946 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1947 SubtargetFeatureInfo &SFI = *it->second;
1948 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1950 OS << " Feature_None = 0\n";
1954 /// emitGetSubtargetFeatureName - Emit the helper function to get the
1955 /// user-level name for a subtarget feature.
1956 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
1957 OS << "// User-level names for subtarget features that participate in\n"
1958 << "// instruction matching.\n"
1959 << "static const char *getSubtargetFeatureName(unsigned Val) {\n"
1960 << " switch(Val) {\n";
1961 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1962 it = Info.SubtargetFeatures.begin(),
1963 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1964 SubtargetFeatureInfo &SFI = *it->second;
1965 // FIXME: Totally just a placeholder name to get the algorithm working.
1966 OS << " case " << SFI.getEnumName() << ": return \""
1967 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
1969 OS << " default: return \"(unknown)\";\n";
1973 /// emitComputeAvailableFeatures - Emit the function to compute the list of
1974 /// available features given a subtarget.
1975 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
1977 std::string ClassName =
1978 Info.AsmParser->getValueAsString("AsmParserClassName");
1980 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1981 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
1982 OS << " unsigned Features = 0;\n";
1983 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1984 it = Info.SubtargetFeatures.begin(),
1985 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1986 SubtargetFeatureInfo &SFI = *it->second;
1989 std::string CondStorage =
1990 SFI.TheDef->getValueAsString("AssemblerCondString");
1991 StringRef Conds = CondStorage;
1992 std::pair<StringRef,StringRef> Comma = Conds.split(',');
1999 StringRef Cond = Comma.first;
2000 if (Cond[0] == '!') {
2002 Cond = Cond.substr(1);
2005 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2012 if (Comma.second.empty())
2016 Comma = Comma.second.split(',');
2020 OS << " Features |= " << SFI.getEnumName() << ";\n";
2022 OS << " return Features;\n";
2026 static std::string GetAliasRequiredFeatures(Record *R,
2027 const AsmMatcherInfo &Info) {
2028 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2030 unsigned NumFeatures = 0;
2031 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2032 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2035 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2036 "' is not marked as an AssemblerPredicate!");
2041 Result += F->getEnumName();
2045 if (NumFeatures > 1)
2046 Result = '(' + Result + ')';
2050 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2051 /// emit a function for them and return true, otherwise return false.
2052 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
2053 // Ignore aliases when match-prefix is set.
2054 if (!MatchPrefix.empty())
2057 std::vector<Record*> Aliases =
2058 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2059 if (Aliases.empty()) return false;
2061 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2062 "unsigned Features) {\n";
2064 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2065 // iteration order of the map is stable.
2066 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2068 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2069 Record *R = Aliases[i];
2070 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2073 // Process each alias a "from" mnemonic at a time, building the code executed
2074 // by the string remapper.
2075 std::vector<StringMatcher::StringPair> Cases;
2076 for (std::map<std::string, std::vector<Record*> >::iterator
2077 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2079 const std::vector<Record*> &ToVec = I->second;
2081 // Loop through each alias and emit code that handles each case. If there
2082 // are two instructions without predicates, emit an error. If there is one,
2084 std::string MatchCode;
2085 int AliasWithNoPredicate = -1;
2087 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2088 Record *R = ToVec[i];
2089 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2091 // If this unconditionally matches, remember it for later and diagnose
2093 if (FeatureMask.empty()) {
2094 if (AliasWithNoPredicate != -1) {
2095 // We can't have two aliases from the same mnemonic with no predicate.
2096 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2097 "two MnemonicAliases with the same 'from' mnemonic!");
2098 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
2101 AliasWithNoPredicate = i;
2104 if (R->getValueAsString("ToMnemonic") == I->first)
2105 throw TGError(R->getLoc(), "MnemonicAlias to the same string");
2107 if (!MatchCode.empty())
2108 MatchCode += "else ";
2109 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2110 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2113 if (AliasWithNoPredicate != -1) {
2114 Record *R = ToVec[AliasWithNoPredicate];
2115 if (!MatchCode.empty())
2116 MatchCode += "else\n ";
2117 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2120 MatchCode += "return;";
2122 Cases.push_back(std::make_pair(I->first, MatchCode));
2125 StringMatcher("Mnemonic", Cases, OS).Emit();
2131 static const char *getMinimalTypeForRange(uint64_t Range) {
2132 assert(Range < 0xFFFFFFFFULL && "Enum too large");
2140 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2141 const AsmMatcherInfo &Info, StringRef ClassName) {
2142 // Emit the static custom operand parsing table;
2143 OS << "namespace {\n";
2144 OS << " struct OperandMatchEntry {\n";
2145 OS << " static const char *const MnemonicTable;\n";
2146 OS << " uint32_t OperandMask;\n";
2147 OS << " uint32_t Mnemonic;\n";
2148 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2149 << " RequiredFeatures;\n";
2150 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2152 OS << " StringRef getMnemonic() const {\n";
2153 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2154 OS << " MnemonicTable[Mnemonic]);\n";
2158 OS << " // Predicate for searching for an opcode.\n";
2159 OS << " struct LessOpcodeOperand {\n";
2160 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2161 OS << " return LHS.getMnemonic() < RHS;\n";
2163 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2164 OS << " return LHS < RHS.getMnemonic();\n";
2166 OS << " bool operator()(const OperandMatchEntry &LHS,";
2167 OS << " const OperandMatchEntry &RHS) {\n";
2168 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2172 OS << "} // end anonymous namespace.\n\n";
2174 StringToOffsetTable StringTable;
2176 OS << "static const OperandMatchEntry OperandMatchTable["
2177 << Info.OperandMatchInfo.size() << "] = {\n";
2179 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2180 for (std::vector<OperandMatchEntry>::const_iterator it =
2181 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2183 const OperandMatchEntry &OMI = *it;
2184 const MatchableInfo &II = *OMI.MI;
2186 OS << " { " << OMI.OperandMask;
2189 bool printComma = false;
2190 for (int i = 0, e = 31; i !=e; ++i)
2191 if (OMI.OperandMask & (1 << i)) {
2199 // Store a pascal-style length byte in the mnemonic.
2200 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2201 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2202 << " /* " << II.Mnemonic << " */, ";
2204 // Write the required features mask.
2205 if (!II.RequiredFeatures.empty()) {
2206 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2208 OS << II.RequiredFeatures[i]->getEnumName();
2213 OS << ", " << OMI.CI->Name;
2219 OS << "const char *const OperandMatchEntry::MnemonicTable =\n";
2220 StringTable.EmitString(OS);
2223 // Emit the operand class switch to call the correct custom parser for
2224 // the found operand class.
2225 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2226 << Target.getName() << ClassName << "::\n"
2227 << "tryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
2228 << " &Operands,\n unsigned MCK) {\n\n"
2229 << " switch(MCK) {\n";
2231 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
2232 ie = Info.Classes.end(); it != ie; ++it) {
2233 ClassInfo *CI = *it;
2234 if (CI->ParserMethod.empty())
2236 OS << " case " << CI->Name << ":\n"
2237 << " return " << CI->ParserMethod << "(Operands);\n";
2240 OS << " default:\n";
2241 OS << " return MatchOperand_NoMatch;\n";
2243 OS << " return MatchOperand_NoMatch;\n";
2246 // Emit the static custom operand parser. This code is very similar with
2247 // the other matcher. Also use MatchResultTy here just in case we go for
2248 // a better error handling.
2249 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2250 << Target.getName() << ClassName << "::\n"
2251 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
2252 << " &Operands,\n StringRef Mnemonic) {\n";
2254 // Emit code to get the available features.
2255 OS << " // Get the current feature set.\n";
2256 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2258 OS << " // Get the next operand index.\n";
2259 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2261 // Emit code to search the table.
2262 OS << " // Search the table.\n";
2263 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2264 OS << " MnemonicRange =\n";
2265 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2266 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2267 << " LessOpcodeOperand());\n\n";
2269 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2270 OS << " return MatchOperand_NoMatch;\n\n";
2272 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2273 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2275 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2276 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2278 // Emit check that the required features are available.
2279 OS << " // check if the available features match\n";
2280 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2281 << "!= it->RequiredFeatures) {\n";
2282 OS << " continue;\n";
2285 // Emit check to ensure the operand number matches.
2286 OS << " // check if the operand in question has a custom parser.\n";
2287 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2288 OS << " continue;\n\n";
2290 // Emit call to the custom parser method
2291 OS << " // call custom parse method to handle the operand\n";
2292 OS << " OperandMatchResultTy Result = ";
2293 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2294 OS << " if (Result != MatchOperand_NoMatch)\n";
2295 OS << " return Result;\n";
2298 OS << " // Okay, we had no match.\n";
2299 OS << " return MatchOperand_NoMatch;\n";
2303 void AsmMatcherEmitter::run(raw_ostream &OS) {
2304 CodeGenTarget Target(Records);
2305 Record *AsmParser = Target.getAsmParser();
2306 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2308 // Compute the information on the instructions to match.
2309 AsmMatcherInfo Info(AsmParser, Target, Records);
2312 // Sort the instruction table using the partial order on classes. We use
2313 // stable_sort to ensure that ambiguous instructions are still
2314 // deterministically ordered.
2315 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2316 less_ptr<MatchableInfo>());
2318 DEBUG_WITH_TYPE("instruction_info", {
2319 for (std::vector<MatchableInfo*>::iterator
2320 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2325 // Check for ambiguous matchables.
2326 DEBUG_WITH_TYPE("ambiguous_instrs", {
2327 unsigned NumAmbiguous = 0;
2328 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2329 for (unsigned j = i + 1; j != e; ++j) {
2330 MatchableInfo &A = *Info.Matchables[i];
2331 MatchableInfo &B = *Info.Matchables[j];
2333 if (A.couldMatchAmbiguouslyWith(B)) {
2334 errs() << "warning: ambiguous matchables:\n";
2336 errs() << "\nis incomparable with:\n";
2344 errs() << "warning: " << NumAmbiguous
2345 << " ambiguous matchables!\n";
2348 // Compute the information on the custom operand parsing.
2349 Info.buildOperandMatchInfo();
2351 // Write the output.
2353 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
2355 // Information for the class declaration.
2356 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2357 OS << "#undef GET_ASSEMBLER_HEADER\n";
2358 OS << " // This should be included into the middle of the declaration of\n";
2359 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2360 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2361 OS << " bool ConvertToMCInst(unsigned Kind, MCInst &Inst, "
2362 << "unsigned Opcode,\n"
2363 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2365 OS << " bool MnemonicIsValid(StringRef Mnemonic);\n";
2366 OS << " unsigned MatchInstructionImpl(\n";
2367 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2368 OS << " MCInst &Inst, unsigned &ErrorInfo, unsigned VariantID = 0);\n";
2370 if (Info.OperandMatchInfo.size()) {
2371 OS << "\n enum OperandMatchResultTy {\n";
2372 OS << " MatchOperand_Success, // operand matched successfully\n";
2373 OS << " MatchOperand_NoMatch, // operand did not match\n";
2374 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2376 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2377 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2378 OS << " StringRef Mnemonic);\n";
2380 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2381 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2382 OS << " unsigned MCK);\n\n";
2385 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2387 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2388 OS << "#undef GET_REGISTER_MATCHER\n\n";
2390 // Emit the subtarget feature enumeration.
2391 emitSubtargetFeatureFlagEnumeration(Info, OS);
2393 // Emit the function to match a register name to number.
2394 emitMatchRegisterName(Target, AsmParser, OS);
2396 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2398 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2399 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2401 // Generate the helper function to get the names for subtarget features.
2402 emitGetSubtargetFeatureName(Info, OS);
2404 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2406 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2407 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2409 // Generate the function that remaps for mnemonic aliases.
2410 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info);
2412 // Generate the unified function to convert operands into an MCInst.
2413 emitConvertToMCInst(Target, ClassName, Info.Matchables, OS);
2415 // Emit the enumeration for classes which participate in matching.
2416 emitMatchClassEnumeration(Target, Info.Classes, OS);
2418 // Emit the routine to match token strings to their match class.
2419 emitMatchTokenString(Target, Info.Classes, OS);
2421 // Emit the subclass predicate routine.
2422 emitIsSubclass(Target, Info.Classes, OS);
2424 // Emit the routine to validate an operand against a match class.
2425 emitValidateOperandClass(Info, OS);
2427 // Emit the available features compute function.
2428 emitComputeAvailableFeatures(Info, OS);
2431 size_t MaxNumOperands = 0;
2432 for (std::vector<MatchableInfo*>::const_iterator it =
2433 Info.Matchables.begin(), ie = Info.Matchables.end();
2435 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
2437 // Emit the static match table; unused classes get initalized to 0 which is
2438 // guaranteed to be InvalidMatchClass.
2440 // FIXME: We can reduce the size of this table very easily. First, we change
2441 // it so that store the kinds in separate bit-fields for each index, which
2442 // only needs to be the max width used for classes at that index (we also need
2443 // to reject based on this during classification). If we then make sure to
2444 // order the match kinds appropriately (putting mnemonics last), then we
2445 // should only end up using a few bits for each class, especially the ones
2446 // following the mnemonic.
2447 OS << "namespace {\n";
2448 OS << " struct MatchEntry {\n";
2449 OS << " static const char *const MnemonicTable;\n";
2450 OS << " uint32_t Mnemonic;\n";
2451 OS << " uint16_t Opcode;\n";
2452 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2454 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2455 << " RequiredFeatures;\n";
2456 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2457 << " Classes[" << MaxNumOperands << "];\n";
2458 OS << " uint8_t AsmVariantID;\n\n";
2459 OS << " StringRef getMnemonic() const {\n";
2460 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2461 OS << " MnemonicTable[Mnemonic]);\n";
2465 OS << " // Predicate for searching for an opcode.\n";
2466 OS << " struct LessOpcode {\n";
2467 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2468 OS << " return LHS.getMnemonic() < RHS;\n";
2470 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2471 OS << " return LHS < RHS.getMnemonic();\n";
2473 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2474 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2478 OS << "} // end anonymous namespace.\n\n";
2480 StringToOffsetTable StringTable;
2482 OS << "static const MatchEntry MatchTable["
2483 << Info.Matchables.size() << "] = {\n";
2485 for (std::vector<MatchableInfo*>::const_iterator it =
2486 Info.Matchables.begin(), ie = Info.Matchables.end();
2488 MatchableInfo &II = **it;
2490 // Store a pascal-style length byte in the mnemonic.
2491 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2492 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2493 << " /* " << II.Mnemonic << " */, "
2494 << Target.getName() << "::"
2495 << II.getResultInst()->TheDef->getName() << ", "
2496 << II.ConversionFnKind << ", ";
2498 // Write the required features mask.
2499 if (!II.RequiredFeatures.empty()) {
2500 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2502 OS << II.RequiredFeatures[i]->getEnumName();
2508 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2509 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2512 OS << Op.Class->Name;
2514 OS << " }, " << II.AsmVariantID;
2520 OS << "const char *const MatchEntry::MnemonicTable =\n";
2521 StringTable.EmitString(OS);
2524 // A method to determine if a mnemonic is in the list.
2525 OS << "bool " << Target.getName() << ClassName << "::\n"
2526 << "MnemonicIsValid(StringRef Mnemonic) {\n";
2527 OS << " // Search the table.\n";
2528 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2529 OS << " std::equal_range(MatchTable, MatchTable+"
2530 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n";
2531 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2534 // Finally, build the match function.
2536 << Target.getName() << ClassName << "::\n"
2537 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2539 OS << " MCInst &Inst, unsigned &ErrorInfo, ";
2540 OS << "unsigned VariantID) {\n";
2542 // Emit code to get the available features.
2543 OS << " // Get the current feature set.\n";
2544 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2546 OS << " // Get the instruction mnemonic, which is the first token.\n";
2547 OS << " StringRef Mnemonic = ((" << Target.getName()
2548 << "Operand*)Operands[0])->getToken();\n\n";
2550 if (HasMnemonicAliases) {
2551 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2552 OS << " // FIXME : Add an entry in AsmParserVariant to check this.\n";
2553 OS << " if (!VariantID)\n";
2554 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
2557 // Emit code to compute the class list for this operand vector.
2558 OS << " // Eliminate obvious mismatches.\n";
2559 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2560 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2561 OS << " return Match_InvalidOperand;\n";
2564 OS << " // Some state to try to produce better error messages.\n";
2565 OS << " bool HadMatchOtherThanFeatures = false;\n";
2566 OS << " bool HadMatchOtherThanPredicate = false;\n";
2567 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2568 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2569 OS << " // wrong for all instances of the instruction.\n";
2570 OS << " ErrorInfo = ~0U;\n";
2572 // Emit code to search the table.
2573 OS << " // Search the table.\n";
2574 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2575 OS << " std::equal_range(MatchTable, MatchTable+"
2576 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
2578 OS << " // Return a more specific error code if no mnemonics match.\n";
2579 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2580 OS << " return Match_MnemonicFail;\n\n";
2582 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2583 << "*ie = MnemonicRange.second;\n";
2584 OS << " it != ie; ++it) {\n";
2586 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2587 OS << " assert(Mnemonic == it->getMnemonic());\n";
2589 // Emit check that the subclasses match.
2590 OS << " if (VariantID != it->AsmVariantID) continue;\n";
2591 OS << " bool OperandsValid = true;\n";
2592 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2593 OS << " if (i + 1 >= Operands.size()) {\n";
2594 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2597 OS << " if (validateOperandClass(Operands[i+1], "
2598 "(MatchClassKind)it->Classes[i]))\n";
2599 OS << " continue;\n";
2600 OS << " // If this operand is broken for all of the instances of this\n";
2601 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2602 OS << " if (it == MnemonicRange.first || ErrorInfo <= i+1)\n";
2603 OS << " ErrorInfo = i+1;\n";
2604 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2605 OS << " OperandsValid = false;\n";
2609 OS << " if (!OperandsValid) continue;\n";
2611 // Emit check that the required features are available.
2612 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2613 << "!= it->RequiredFeatures) {\n";
2614 OS << " HadMatchOtherThanFeatures = true;\n";
2615 OS << " ErrorInfo = it->RequiredFeatures & ~AvailableFeatures;\n";
2616 OS << " continue;\n";
2619 OS << " // We have selected a definite instruction, convert the parsed\n"
2620 << " // operands into the appropriate MCInst.\n";
2621 OS << " if (!ConvertToMCInst(it->ConvertFn, Inst,\n"
2622 << " it->Opcode, Operands))\n";
2623 OS << " return Match_ConversionFail;\n";
2626 // Verify the instruction with the target-specific match predicate function.
2627 OS << " // We have a potential match. Check the target predicate to\n"
2628 << " // handle any context sensitive constraints.\n"
2629 << " unsigned MatchResult;\n"
2630 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
2631 << " Match_Success) {\n"
2632 << " Inst.clear();\n"
2633 << " RetCode = MatchResult;\n"
2634 << " HadMatchOtherThanPredicate = true;\n"
2638 // Call the post-processing function, if used.
2639 std::string InsnCleanupFn =
2640 AsmParser->getValueAsString("AsmParserInstCleanup");
2641 if (!InsnCleanupFn.empty())
2642 OS << " " << InsnCleanupFn << "(Inst);\n";
2644 OS << " return Match_Success;\n";
2647 OS << " // Okay, we had no match. Try to return a useful error code.\n";
2648 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)";
2649 OS << " return RetCode;\n";
2650 OS << " assert(ErrorInfo && \"missing feature(s) but what?!\");";
2651 OS << " return Match_MissingFeature;\n";
2654 if (Info.OperandMatchInfo.size())
2655 emitCustomOperandParsing(OS, Target, Info, ClassName);
2657 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";