1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures.
13 // The input to the target specific matcher is a list of literal tokens and
14 // operands. The target specific parser should generally eliminate any syntax
15 // which is not relevant for matching; for example, comma tokens should have
16 // already been consumed and eliminated by the parser. Most instructions will
17 // end up with a single literal token (the instruction name) and some number of
20 // Some example inputs, for X86:
21 // 'addl' (immediate ...) (register ...)
22 // 'add' (immediate ...) (memory ...)
25 // The assembly matcher is responsible for converting this input into a precise
26 // machine instruction (i.e., an instruction with a well defined encoding). This
27 // mapping has several properties which complicate matching:
29 // - It may be ambiguous; many architectures can legally encode particular
30 // variants of an instruction in different ways (for example, using a smaller
31 // encoding for small immediates). Such ambiguities should never be
32 // arbitrarily resolved by the assembler, the assembler is always responsible
33 // for choosing the "best" available instruction.
35 // - It may depend on the subtarget or the assembler context. Instructions
36 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
37 // an SSE instruction in a file being assembled for i486) should be accepted
38 // and rejected by the assembler front end. However, if the proper encoding
39 // for an instruction is dependent on the assembler context then the matcher
40 // is responsible for selecting the correct machine instruction for the
43 // The core matching algorithm attempts to exploit the regularity in most
44 // instruction sets to quickly determine the set of possibly matching
45 // instructions, and the simplify the generated code. Additionally, this helps
46 // to ensure that the ambiguities are intentionally resolved by the user.
48 // The matching is divided into two distinct phases:
50 // 1. Classification: Each operand is mapped to the unique set which (a)
51 // contains it, and (b) is the largest such subset for which a single
52 // instruction could match all members.
54 // For register classes, we can generate these subgroups automatically. For
55 // arbitrary operands, we expect the user to define the classes and their
56 // relations to one another (for example, 8-bit signed immediates as a
57 // subset of 32-bit immediates).
59 // By partitioning the operands in this way, we guarantee that for any
60 // tuple of classes, any single instruction must match either all or none
61 // of the sets of operands which could classify to that tuple.
63 // In addition, the subset relation amongst classes induces a partial order
64 // on such tuples, which we use to resolve ambiguities.
66 // 2. The input can now be treated as a tuple of classes (static tokens are
67 // simple singleton sets). Each such tuple should generally map to a single
68 // instruction (we currently ignore cases where this isn't true, whee!!!),
69 // which we can emit a simple matcher for.
71 //===----------------------------------------------------------------------===//
73 #include "AsmMatcherEmitter.h"
74 #include "CodeGenTarget.h"
76 #include "StringMatcher.h"
77 #include "llvm/ADT/OwningPtr.h"
78 #include "llvm/ADT/PointerUnion.h"
79 #include "llvm/ADT/SmallPtrSet.h"
80 #include "llvm/ADT/SmallVector.h"
81 #include "llvm/ADT/STLExtras.h"
82 #include "llvm/ADT/StringExtras.h"
83 #include "llvm/Support/CommandLine.h"
84 #include "llvm/Support/Debug.h"
89 static cl::opt<std::string>
90 MatchPrefix("match-prefix", cl::init(""),
91 cl::desc("Only match instructions with the given prefix"));
96 struct SubtargetFeatureInfo;
98 /// ClassInfo - Helper class for storing the information about a particular
99 /// class of operands which can be matched.
102 /// Invalid kind, for use as a sentinel value.
105 /// The class for a particular token.
108 /// The (first) register class, subsequent register classes are
109 /// RegisterClass0+1, and so on.
112 /// The (first) user defined class, subsequent user defined classes are
113 /// UserClass0+1, and so on.
117 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
118 /// N) for the Nth user defined class.
121 /// SuperClasses - The super classes of this class. Note that for simplicities
122 /// sake user operands only record their immediate super class, while register
123 /// operands include all superclasses.
124 std::vector<ClassInfo*> SuperClasses;
126 /// Name - The full class name, suitable for use in an enum.
129 /// ClassName - The unadorned generic name for this class (e.g., Token).
130 std::string ClassName;
132 /// ValueName - The name of the value this class represents; for a token this
133 /// is the literal token string, for an operand it is the TableGen class (or
134 /// empty if this is a derived class).
135 std::string ValueName;
137 /// PredicateMethod - The name of the operand method to test whether the
138 /// operand matches this class; this is not valid for Token or register kinds.
139 std::string PredicateMethod;
141 /// RenderMethod - The name of the operand method to add this operand to an
142 /// MCInst; this is not valid for Token or register kinds.
143 std::string RenderMethod;
145 /// For register classes, the records for all the registers in this class.
146 std::set<Record*> Registers;
149 /// isRegisterClass() - Check if this is a register class.
150 bool isRegisterClass() const {
151 return Kind >= RegisterClass0 && Kind < UserClass0;
154 /// isUserClass() - Check if this is a user defined class.
155 bool isUserClass() const {
156 return Kind >= UserClass0;
159 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
160 /// are related if they are in the same class hierarchy.
161 bool isRelatedTo(const ClassInfo &RHS) const {
162 // Tokens are only related to tokens.
163 if (Kind == Token || RHS.Kind == Token)
164 return Kind == Token && RHS.Kind == Token;
166 // Registers classes are only related to registers classes, and only if
167 // their intersection is non-empty.
168 if (isRegisterClass() || RHS.isRegisterClass()) {
169 if (!isRegisterClass() || !RHS.isRegisterClass())
172 std::set<Record*> Tmp;
173 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
174 std::set_intersection(Registers.begin(), Registers.end(),
175 RHS.Registers.begin(), RHS.Registers.end(),
181 // Otherwise we have two users operands; they are related if they are in the
182 // same class hierarchy.
184 // FIXME: This is an oversimplification, they should only be related if they
185 // intersect, however we don't have that information.
186 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
187 const ClassInfo *Root = this;
188 while (!Root->SuperClasses.empty())
189 Root = Root->SuperClasses.front();
191 const ClassInfo *RHSRoot = &RHS;
192 while (!RHSRoot->SuperClasses.empty())
193 RHSRoot = RHSRoot->SuperClasses.front();
195 return Root == RHSRoot;
198 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
199 bool isSubsetOf(const ClassInfo &RHS) const {
200 // This is a subset of RHS if it is the same class...
204 // ... or if any of its super classes are a subset of RHS.
205 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
206 ie = SuperClasses.end(); it != ie; ++it)
207 if ((*it)->isSubsetOf(RHS))
213 /// operator< - Compare two classes.
214 bool operator<(const ClassInfo &RHS) const {
218 // Unrelated classes can be ordered by kind.
219 if (!isRelatedTo(RHS))
220 return Kind < RHS.Kind;
224 assert(0 && "Invalid kind!");
226 // Tokens are comparable by value.
228 // FIXME: Compare by enum value.
229 return ValueName < RHS.ValueName;
232 // This class preceeds the RHS if it is a proper subset of the RHS.
235 if (RHS.isSubsetOf(*this))
238 // Otherwise, order by name to ensure we have a total ordering.
239 return ValueName < RHS.ValueName;
244 /// MatchableInfo - Helper class for storing the necessary information for an
245 /// instruction or alias which is capable of being matched.
246 struct MatchableInfo {
248 /// Token - This is the token that the operand came from.
251 /// The unique class instance this operand should match.
254 /// The operand name this is, if anything.
257 /// The suboperand index within SrcOpName, or -1 for the entire operand.
260 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1) {}
263 /// ResOperand - This represents a single operand in the result instruction
264 /// generated by the match. In cases (like addressing modes) where a single
265 /// assembler operand expands to multiple MCOperands, this represents the
266 /// single assembler operand, not the MCOperand.
269 /// RenderAsmOperand - This represents an operand result that is
270 /// generated by calling the render method on the assembly operand. The
271 /// corresponding AsmOperand is specified by AsmOperandNum.
274 /// TiedOperand - This represents a result operand that is a duplicate of
275 /// a previous result operand.
278 /// ImmOperand - This represents an immediate value that is dumped into
282 /// RegOperand - This represents a fixed register that is dumped in.
287 /// This is the operand # in the AsmOperands list that this should be
289 unsigned AsmOperandNum;
291 /// TiedOperandNum - This is the (earlier) result operand that should be
293 unsigned TiedOperandNum;
295 /// ImmVal - This is the immediate value added to the instruction.
298 /// Register - This is the register record.
302 /// MINumOperands - The number of MCInst operands populated by this
304 unsigned MINumOperands;
306 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
308 X.Kind = RenderAsmOperand;
309 X.AsmOperandNum = AsmOpNum;
310 X.MINumOperands = NumOperands;
314 static ResOperand getTiedOp(unsigned TiedOperandNum) {
316 X.Kind = TiedOperand;
317 X.TiedOperandNum = TiedOperandNum;
322 static ResOperand getImmOp(int64_t Val) {
330 static ResOperand getRegOp(Record *Reg) {
339 /// TheDef - This is the definition of the instruction or InstAlias that this
340 /// matchable came from.
341 Record *const TheDef;
343 /// DefRec - This is the definition that it came from.
344 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
346 const CodeGenInstruction *getResultInst() const {
347 if (DefRec.is<const CodeGenInstruction*>())
348 return DefRec.get<const CodeGenInstruction*>();
349 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
352 /// ResOperands - This is the operand list that should be built for the result
354 std::vector<ResOperand> ResOperands;
356 /// AsmString - The assembly string for this instruction (with variants
357 /// removed), e.g. "movsx $src, $dst".
358 std::string AsmString;
360 /// Mnemonic - This is the first token of the matched instruction, its
364 /// AsmOperands - The textual operands that this instruction matches,
365 /// annotated with a class and where in the OperandList they were defined.
366 /// This directly corresponds to the tokenized AsmString after the mnemonic is
368 SmallVector<AsmOperand, 4> AsmOperands;
370 /// Predicates - The required subtarget features to match this instruction.
371 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
373 /// ConversionFnKind - The enum value which is passed to the generated
374 /// ConvertToMCInst to convert parsed operands into an MCInst for this
376 std::string ConversionFnKind;
378 MatchableInfo(const CodeGenInstruction &CGI)
379 : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) {
382 MatchableInfo(const CodeGenInstAlias *Alias)
383 : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) {
386 void Initialize(const AsmMatcherInfo &Info,
387 SmallPtrSet<Record*, 16> &SingletonRegisters);
389 /// Validate - Return true if this matchable is a valid thing to match against
390 /// and perform a bunch of validity checking.
391 bool Validate(StringRef CommentDelimiter, bool Hack) const;
393 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
394 /// register, return the Record for it, otherwise return null.
395 Record *getSingletonRegisterForAsmOperand(unsigned i,
396 const AsmMatcherInfo &Info) const;
398 /// FindAsmOperand - Find the AsmOperand with the specified name and
399 /// suboperand index.
400 int FindAsmOperand(StringRef N, int SubOpIdx) const {
401 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
402 if (N == AsmOperands[i].SrcOpName &&
403 SubOpIdx == AsmOperands[i].SubOpIdx)
408 /// FindAsmOperandNamed - Find the first AsmOperand with the specified name.
409 /// This does not check the suboperand index.
410 int FindAsmOperandNamed(StringRef N) const {
411 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
412 if (N == AsmOperands[i].SrcOpName)
417 void BuildInstructionResultOperands();
418 void BuildAliasResultOperands();
420 /// operator< - Compare two matchables.
421 bool operator<(const MatchableInfo &RHS) const {
422 // The primary comparator is the instruction mnemonic.
423 if (Mnemonic != RHS.Mnemonic)
424 return Mnemonic < RHS.Mnemonic;
426 if (AsmOperands.size() != RHS.AsmOperands.size())
427 return AsmOperands.size() < RHS.AsmOperands.size();
429 // Compare lexicographically by operand. The matcher validates that other
430 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith().
431 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
432 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
434 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
441 /// CouldMatchAmiguouslyWith - Check whether this matchable could
442 /// ambiguously match the same set of operands as \arg RHS (without being a
443 /// strictly superior match).
444 bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) {
445 // The primary comparator is the instruction mnemonic.
446 if (Mnemonic != RHS.Mnemonic)
449 // The number of operands is unambiguous.
450 if (AsmOperands.size() != RHS.AsmOperands.size())
453 // Otherwise, make sure the ordering of the two instructions is unambiguous
454 // by checking that either (a) a token or operand kind discriminates them,
455 // or (b) the ordering among equivalent kinds is consistent.
457 // Tokens and operand kinds are unambiguous (assuming a correct target
459 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
460 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
461 AsmOperands[i].Class->Kind == ClassInfo::Token)
462 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
463 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
466 // Otherwise, this operand could commute if all operands are equivalent, or
467 // there is a pair of operands that compare less than and a pair that
468 // compare greater than.
469 bool HasLT = false, HasGT = false;
470 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
471 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
473 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
477 return !(HasLT ^ HasGT);
483 void TokenizeAsmString(const AsmMatcherInfo &Info);
486 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
487 /// feature which participates in instruction matching.
488 struct SubtargetFeatureInfo {
489 /// \brief The predicate record for this feature.
492 /// \brief An unique index assigned to represent this feature.
495 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
497 /// \brief The name of the enumerated constant identifying this feature.
498 std::string getEnumName() const {
499 return "Feature_" + TheDef->getName();
503 class AsmMatcherInfo {
506 RecordKeeper &Records;
508 /// The tablegen AsmParser record.
511 /// Target - The target information.
512 CodeGenTarget &Target;
514 /// The AsmParser "RegisterPrefix" value.
515 std::string RegisterPrefix;
517 /// The classes which are needed for matching.
518 std::vector<ClassInfo*> Classes;
520 /// The information on the matchables to match.
521 std::vector<MatchableInfo*> Matchables;
523 /// Map of Register records to their class information.
524 std::map<Record*, ClassInfo*> RegisterClasses;
526 /// Map of Predicate records to their subtarget information.
527 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
530 /// Map of token to class information which has already been constructed.
531 std::map<std::string, ClassInfo*> TokenClasses;
533 /// Map of RegisterClass records to their class information.
534 std::map<Record*, ClassInfo*> RegisterClassClasses;
536 /// Map of AsmOperandClass records to their class information.
537 std::map<Record*, ClassInfo*> AsmOperandClasses;
540 /// getTokenClass - Lookup or create the class for the given token.
541 ClassInfo *getTokenClass(StringRef Token);
543 /// getOperandClass - Lookup or create the class for the given operand.
544 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
547 /// BuildRegisterClasses - Build the ClassInfo* instances for register
549 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
551 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
553 void BuildOperandClasses();
555 void BuildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
557 void BuildAliasOperandReference(MatchableInfo *II, StringRef OpName,
558 MatchableInfo::AsmOperand &Op);
561 AsmMatcherInfo(Record *AsmParser,
562 CodeGenTarget &Target,
563 RecordKeeper &Records);
565 /// BuildInfo - Construct the various tables used during matching.
568 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
570 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
571 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
572 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
573 SubtargetFeatures.find(Def);
574 return I == SubtargetFeatures.end() ? 0 : I->second;
577 RecordKeeper &getRecords() const {
584 void MatchableInfo::dump() {
585 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
587 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
588 AsmOperand &Op = AsmOperands[i];
589 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
590 errs() << '\"' << Op.Token << "\"\n";
594 void MatchableInfo::Initialize(const AsmMatcherInfo &Info,
595 SmallPtrSet<Record*, 16> &SingletonRegisters) {
596 // TODO: Eventually support asmparser for Variant != 0.
597 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0);
599 TokenizeAsmString(Info);
601 // Compute the require features.
602 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
603 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
604 if (SubtargetFeatureInfo *Feature =
605 Info.getSubtargetFeature(Predicates[i]))
606 RequiredFeatures.push_back(Feature);
608 // Collect singleton registers, if used.
609 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
610 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
611 SingletonRegisters.insert(Reg);
615 /// TokenizeAsmString - Tokenize a simplified assembly string.
616 void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) {
617 StringRef String = AsmString;
620 for (unsigned i = 0, e = String.size(); i != e; ++i) {
630 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
633 if (!isspace(String[i]) && String[i] != ',')
634 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
640 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
644 assert(i != String.size() && "Invalid quoted character");
645 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
651 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
655 // If this isn't "${", treat like a normal token.
656 if (i + 1 == String.size() || String[i + 1] != '{') {
661 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
662 assert(End != String.end() && "Missing brace in operand reference!");
663 size_t EndPos = End - String.begin();
664 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
672 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
681 if (InTok && Prev != String.size())
682 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
684 // The first token of the instruction is the mnemonic, which must be a
685 // simple string, not a $foo variable or a singleton register.
686 assert(!AsmOperands.empty() && "Instruction has no tokens?");
687 Mnemonic = AsmOperands[0].Token;
688 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info))
689 throw TGError(TheDef->getLoc(),
690 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
692 // Remove the first operand, it is tracked in the mnemonic field.
693 AsmOperands.erase(AsmOperands.begin());
698 bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const {
699 // Reject matchables with no .s string.
700 if (AsmString.empty())
701 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
703 // Reject any matchables with a newline in them, they should be marked
704 // isCodeGenOnly if they are pseudo instructions.
705 if (AsmString.find('\n') != std::string::npos)
706 throw TGError(TheDef->getLoc(),
707 "multiline instruction is not valid for the asmparser, "
708 "mark it isCodeGenOnly");
710 // Remove comments from the asm string. We know that the asmstring only
712 if (!CommentDelimiter.empty() &&
713 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
714 throw TGError(TheDef->getLoc(),
715 "asmstring for instruction has comment character in it, "
716 "mark it isCodeGenOnly");
718 // Reject matchables with operand modifiers, these aren't something we can
719 // handle, the target should be refactored to use operands instead of
722 // Also, check for instructions which reference the operand multiple times;
723 // this implies a constraint we would not honor.
724 std::set<std::string> OperandNames;
725 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
726 StringRef Tok = AsmOperands[i].Token;
727 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
728 throw TGError(TheDef->getLoc(),
729 "matchable with operand modifier '" + Tok.str() +
730 "' not supported by asm matcher. Mark isCodeGenOnly!");
732 // Verify that any operand is only mentioned once.
733 // We reject aliases and ignore instructions for now.
734 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
736 throw TGError(TheDef->getLoc(),
737 "ERROR: matchable with tied operand '" + Tok.str() +
738 "' can never be matched!");
739 // FIXME: Should reject these. The ARM backend hits this with $lane in a
740 // bunch of instructions. It is unclear what the right answer is.
742 errs() << "warning: '" << TheDef->getName() << "': "
743 << "ignoring instruction with tied operand '"
744 << Tok.str() << "'\n";
754 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
755 /// register, return the register name, otherwise return a null StringRef.
756 Record *MatchableInfo::
757 getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{
758 StringRef Tok = AsmOperands[i].Token;
759 if (!Tok.startswith(Info.RegisterPrefix))
762 StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
763 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
766 // If there is no register prefix (i.e. "%" in "%eax"), then this may
767 // be some random non-register token, just ignore it.
768 if (Info.RegisterPrefix.empty())
771 // Otherwise, we have something invalid prefixed with the register prefix,
773 std::string Err = "unable to find register for '" + RegName.str() +
774 "' (which matches register prefix)";
775 throw TGError(TheDef->getLoc(), Err);
779 static std::string getEnumNameForToken(StringRef Str) {
782 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
784 case '*': Res += "_STAR_"; break;
785 case '%': Res += "_PCT_"; break;
786 case ':': Res += "_COLON_"; break;
787 case '!': Res += "_EXCLAIM_"; break;
788 case '.': Res += "_DOT_"; break;
793 Res += "_" + utostr((unsigned) *it) + "_";
800 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
801 ClassInfo *&Entry = TokenClasses[Token];
804 Entry = new ClassInfo();
805 Entry->Kind = ClassInfo::Token;
806 Entry->ClassName = "Token";
807 Entry->Name = "MCK_" + getEnumNameForToken(Token);
808 Entry->ValueName = Token;
809 Entry->PredicateMethod = "<invalid>";
810 Entry->RenderMethod = "<invalid>";
811 Classes.push_back(Entry);
818 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
820 Record *Rec = OI.Rec;
822 Rec = dynamic_cast<DefInit*>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
824 if (Rec->isSubClassOf("RegisterClass")) {
825 if (ClassInfo *CI = RegisterClassClasses[Rec])
827 throw TGError(Rec->getLoc(), "register class has no class info!");
830 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
831 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
832 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
835 throw TGError(Rec->getLoc(), "operand has no match class!");
838 void AsmMatcherInfo::
839 BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
840 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
841 const std::vector<CodeGenRegisterClass> &RegClassList =
842 Target.getRegisterClasses();
844 // The register sets used for matching.
845 std::set< std::set<Record*> > RegisterSets;
847 // Gather the defined sets.
848 for (std::vector<CodeGenRegisterClass>::const_iterator it =
849 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
850 RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
851 it->Elements.end()));
853 // Add any required singleton sets.
854 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
855 ie = SingletonRegisters.end(); it != ie; ++it) {
857 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
860 // Introduce derived sets where necessary (when a register does not determine
861 // a unique register set class), and build the mapping of registers to the set
862 // they should classify to.
863 std::map<Record*, std::set<Record*> > RegisterMap;
864 for (std::vector<CodeGenRegister>::const_iterator it = Registers.begin(),
865 ie = Registers.end(); it != ie; ++it) {
866 const CodeGenRegister &CGR = *it;
867 // Compute the intersection of all sets containing this register.
868 std::set<Record*> ContainingSet;
870 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
871 ie = RegisterSets.end(); it != ie; ++it) {
872 if (!it->count(CGR.TheDef))
875 if (ContainingSet.empty()) {
880 std::set<Record*> Tmp;
881 std::swap(Tmp, ContainingSet);
882 std::insert_iterator< std::set<Record*> > II(ContainingSet,
883 ContainingSet.begin());
884 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
887 if (!ContainingSet.empty()) {
888 RegisterSets.insert(ContainingSet);
889 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
893 // Construct the register classes.
894 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
896 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
897 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
898 ClassInfo *CI = new ClassInfo();
899 CI->Kind = ClassInfo::RegisterClass0 + Index;
900 CI->ClassName = "Reg" + utostr(Index);
901 CI->Name = "MCK_Reg" + utostr(Index);
903 CI->PredicateMethod = ""; // unused
904 CI->RenderMethod = "addRegOperands";
906 Classes.push_back(CI);
907 RegisterSetClasses.insert(std::make_pair(*it, CI));
910 // Find the superclasses; we could compute only the subgroup lattice edges,
911 // but there isn't really a point.
912 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
913 ie = RegisterSets.end(); it != ie; ++it) {
914 ClassInfo *CI = RegisterSetClasses[*it];
915 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
916 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
918 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
919 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
922 // Name the register classes which correspond to a user defined RegisterClass.
923 for (std::vector<CodeGenRegisterClass>::const_iterator
924 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
925 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
926 it->Elements.end())];
927 if (CI->ValueName.empty()) {
928 CI->ClassName = it->getName();
929 CI->Name = "MCK_" + it->getName();
930 CI->ValueName = it->getName();
932 CI->ValueName = CI->ValueName + "," + it->getName();
934 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
937 // Populate the map for individual registers.
938 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
939 ie = RegisterMap.end(); it != ie; ++it)
940 RegisterClasses[it->first] = RegisterSetClasses[it->second];
942 // Name the register classes which correspond to singleton registers.
943 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
944 ie = SingletonRegisters.end(); it != ie; ++it) {
946 ClassInfo *CI = RegisterClasses[Rec];
947 assert(CI && "Missing singleton register class info!");
949 if (CI->ValueName.empty()) {
950 CI->ClassName = Rec->getName();
951 CI->Name = "MCK_" + Rec->getName();
952 CI->ValueName = Rec->getName();
954 CI->ValueName = CI->ValueName + "," + Rec->getName();
958 void AsmMatcherInfo::BuildOperandClasses() {
959 std::vector<Record*> AsmOperands =
960 Records.getAllDerivedDefinitions("AsmOperandClass");
962 // Pre-populate AsmOperandClasses map.
963 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
964 ie = AsmOperands.end(); it != ie; ++it)
965 AsmOperandClasses[*it] = new ClassInfo();
968 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
969 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
970 ClassInfo *CI = AsmOperandClasses[*it];
971 CI->Kind = ClassInfo::UserClass0 + Index;
973 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
974 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
975 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
977 PrintError((*it)->getLoc(), "Invalid super class reference!");
981 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
983 PrintError((*it)->getLoc(), "Invalid super class reference!");
985 CI->SuperClasses.push_back(SC);
987 CI->ClassName = (*it)->getValueAsString("Name");
988 CI->Name = "MCK_" + CI->ClassName;
989 CI->ValueName = (*it)->getName();
991 // Get or construct the predicate method name.
992 Init *PMName = (*it)->getValueInit("PredicateMethod");
993 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
994 CI->PredicateMethod = SI->getValue();
996 assert(dynamic_cast<UnsetInit*>(PMName) &&
997 "Unexpected PredicateMethod field!");
998 CI->PredicateMethod = "is" + CI->ClassName;
1001 // Get or construct the render method name.
1002 Init *RMName = (*it)->getValueInit("RenderMethod");
1003 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
1004 CI->RenderMethod = SI->getValue();
1006 assert(dynamic_cast<UnsetInit*>(RMName) &&
1007 "Unexpected RenderMethod field!");
1008 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1011 AsmOperandClasses[*it] = CI;
1012 Classes.push_back(CI);
1016 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1017 CodeGenTarget &target,
1018 RecordKeeper &records)
1019 : Records(records), AsmParser(asmParser), Target(target),
1020 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
1024 void AsmMatcherInfo::BuildInfo() {
1025 // Build information about all of the AssemblerPredicates.
1026 std::vector<Record*> AllPredicates =
1027 Records.getAllDerivedDefinitions("Predicate");
1028 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1029 Record *Pred = AllPredicates[i];
1030 // Ignore predicates that are not intended for the assembler.
1031 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1034 if (Pred->getName().empty())
1035 throw TGError(Pred->getLoc(), "Predicate has no name!");
1037 unsigned FeatureNo = SubtargetFeatures.size();
1038 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1039 assert(FeatureNo < 32 && "Too many subtarget features!");
1042 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
1044 // Parse the instructions; we need to do this first so that we can gather the
1045 // singleton register classes.
1046 SmallPtrSet<Record*, 16> SingletonRegisters;
1047 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1048 E = Target.inst_end(); I != E; ++I) {
1049 const CodeGenInstruction &CGI = **I;
1051 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1052 // filter the set of instructions we consider.
1053 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1056 // Ignore "codegen only" instructions.
1057 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1060 // Validate the operand list to ensure we can handle this instruction.
1061 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1062 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1064 // Validate tied operands.
1065 if (OI.getTiedRegister() != -1) {
1066 // If we have a tied operand that consists of multiple MCOperands, reject
1067 // it. We reject aliases and ignore instructions for now.
1068 if (OI.MINumOperands != 1) {
1069 // FIXME: Should reject these. The ARM backend hits this with $lane
1070 // in a bunch of instructions. It is unclear what the right answer is.
1072 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1073 << "ignoring instruction with multi-operand tied operand '"
1074 << OI.Name << "'\n";
1081 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1083 II->Initialize(*this, SingletonRegisters);
1085 // Ignore instructions which shouldn't be matched and diagnose invalid
1086 // instruction definitions with an error.
1087 if (!II->Validate(CommentDelimiter, true))
1090 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1092 // FIXME: This is a total hack.
1093 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1094 StringRef(II->TheDef->getName()).endswith("_Int"))
1097 Matchables.push_back(II.take());
1100 // Parse all of the InstAlias definitions and stick them in the list of
1102 std::vector<Record*> AllInstAliases =
1103 Records.getAllDerivedDefinitions("InstAlias");
1104 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1105 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1107 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1108 // filter the set of instruction aliases we consider, based on the target
1110 if (!StringRef(Alias->ResultInst->TheDef->getName()).startswith(
1114 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1116 II->Initialize(*this, SingletonRegisters);
1118 // Validate the alias definitions.
1119 II->Validate(CommentDelimiter, false);
1121 Matchables.push_back(II.take());
1124 // Build info for the register classes.
1125 BuildRegisterClasses(SingletonRegisters);
1127 // Build info for the user defined assembly operand classes.
1128 BuildOperandClasses();
1130 // Build the information about matchables, now that we have fully formed
1132 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1133 ie = Matchables.end(); it != ie; ++it) {
1134 MatchableInfo *II = *it;
1136 // Parse the tokens after the mnemonic.
1137 // Note: BuildInstructionOperandReference may insert new AsmOperands, so
1138 // don't precompute the loop bound.
1139 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1140 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1141 StringRef Token = Op.Token;
1143 // Check for singleton registers.
1144 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) {
1145 Op.Class = RegisterClasses[RegRecord];
1146 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1147 "Unexpected class for singleton register");
1151 // Check for simple tokens.
1152 if (Token[0] != '$') {
1153 Op.Class = getTokenClass(Token);
1157 if (Token.size() > 1 && isdigit(Token[1])) {
1158 Op.Class = getTokenClass(Token);
1162 // Otherwise this is an operand reference.
1163 StringRef OperandName;
1164 if (Token[1] == '{')
1165 OperandName = Token.substr(2, Token.size() - 3);
1167 OperandName = Token.substr(1);
1169 if (II->DefRec.is<const CodeGenInstruction*>())
1170 BuildInstructionOperandReference(II, OperandName, i);
1172 BuildAliasOperandReference(II, OperandName, Op);
1175 if (II->DefRec.is<const CodeGenInstruction*>())
1176 II->BuildInstructionResultOperands();
1178 II->BuildAliasResultOperands();
1181 // Reorder classes so that classes preceed super classes.
1182 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1185 /// BuildInstructionOperandReference - The specified operand is a reference to a
1186 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1187 void AsmMatcherInfo::
1188 BuildInstructionOperandReference(MatchableInfo *II,
1189 StringRef OperandName,
1190 unsigned AsmOpIdx) {
1191 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1192 const CGIOperandList &Operands = CGI.Operands;
1193 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1195 // Map this token to an operand.
1197 if (!Operands.hasOperandNamed(OperandName, Idx))
1198 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1199 OperandName.str() + "'");
1201 // If the instruction operand has multiple suboperands, but the parser
1202 // match class for the asm operand is still the default "ImmAsmOperand",
1203 // then handle each suboperand separately.
1204 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1205 Record *Rec = Operands[Idx].Rec;
1206 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1207 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1208 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1209 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1210 StringRef Token = Op->Token; // save this in case Op gets moved
1211 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1212 MatchableInfo::AsmOperand NewAsmOp(Token);
1213 NewAsmOp.SubOpIdx = SI;
1214 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1216 // Replace Op with first suboperand.
1217 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1222 // Set up the operand class.
1223 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1225 // If the named operand is tied, canonicalize it to the untied operand.
1226 // For example, something like:
1227 // (outs GPR:$dst), (ins GPR:$src)
1228 // with an asmstring of
1230 // we want to canonicalize to:
1232 // so that we know how to provide the $dst operand when filling in the result.
1233 int OITied = Operands[Idx].getTiedRegister();
1235 // The tied operand index is an MIOperand index, find the operand that
1237 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1238 OperandName = Operands[Idx.first].Name;
1239 Op->SubOpIdx = Idx.second;
1242 Op->SrcOpName = OperandName;
1245 /// BuildAliasOperandReference - When parsing an operand reference out of the
1246 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1247 /// operand reference is by looking it up in the result pattern definition.
1248 void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II,
1249 StringRef OperandName,
1250 MatchableInfo::AsmOperand &Op) {
1251 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1253 // Set up the operand class.
1254 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1255 if (CGA.ResultOperands[i].isRecord() &&
1256 CGA.ResultOperands[i].getName() == OperandName) {
1257 // It's safe to go with the first one we find, because CodeGenInstAlias
1258 // validates that all operands with the same name have the same record.
1259 unsigned ResultIdx = CGA.ResultInstOperandIndex[i].first;
1260 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1261 Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx],
1263 Op.SrcOpName = OperandName;
1267 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1268 OperandName.str() + "'");
1271 void MatchableInfo::BuildInstructionResultOperands() {
1272 const CodeGenInstruction *ResultInst = getResultInst();
1274 // Loop over all operands of the result instruction, determining how to
1276 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1277 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1279 // If this is a tied operand, just copy from the previously handled operand.
1280 int TiedOp = OpInfo.getTiedRegister();
1282 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1286 // Find out what operand from the asmparser this MCInst operand comes from.
1287 int SrcOperand = FindAsmOperandNamed(OpInfo.Name);
1288 if (OpInfo.Name.empty() || SrcOperand == -1)
1289 throw TGError(TheDef->getLoc(), "Instruction '" +
1290 TheDef->getName() + "' has operand '" + OpInfo.Name +
1291 "' that doesn't appear in asm string!");
1293 // Check if the one AsmOperand populates the entire operand.
1294 unsigned NumOperands = OpInfo.MINumOperands;
1295 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1296 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1300 // Add a separate ResOperand for each suboperand.
1301 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1302 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1303 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1304 "unexpected AsmOperands for suboperands");
1305 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1310 void MatchableInfo::BuildAliasResultOperands() {
1311 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1312 const CodeGenInstruction *ResultInst = getResultInst();
1314 // Loop over all operands of the result instruction, determining how to
1316 unsigned AliasOpNo = 0;
1317 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1318 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1319 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1321 // If this is a tied operand, just copy from the previously handled operand.
1322 int TiedOp = OpInfo->getTiedRegister();
1324 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1328 // Handle all the suboperands for this operand.
1329 const std::string &OpName = OpInfo->Name;
1330 for ( ; AliasOpNo < LastOpNo &&
1331 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1332 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1334 // Find out what operand from the asmparser that this MCInst operand
1336 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1337 default: assert(0 && "unexpected InstAlias operand kind");
1338 case CodeGenInstAlias::ResultOperand::K_Record: {
1339 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1340 int SrcOperand = FindAsmOperand(Name, SubIdx);
1341 if (SrcOperand == -1)
1342 throw TGError(TheDef->getLoc(), "Instruction '" +
1343 TheDef->getName() + "' has operand '" + OpName +
1344 "' that doesn't appear in asm string!");
1345 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1346 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1350 case CodeGenInstAlias::ResultOperand::K_Imm: {
1351 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1352 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1355 case CodeGenInstAlias::ResultOperand::K_Reg: {
1356 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1357 ResOperands.push_back(ResOperand::getRegOp(Reg));
1365 static void EmitConvertToMCInst(CodeGenTarget &Target,
1366 std::vector<MatchableInfo*> &Infos,
1368 // Write the convert function to a separate stream, so we can drop it after
1370 std::string ConvertFnBody;
1371 raw_string_ostream CvtOS(ConvertFnBody);
1373 // Function we have already generated.
1374 std::set<std::string> GeneratedFns;
1376 // Start the unified conversion function.
1377 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
1378 << "unsigned Opcode,\n"
1379 << " const SmallVectorImpl<MCParsedAsmOperand*"
1380 << "> &Operands) {\n";
1381 CvtOS << " Inst.setOpcode(Opcode);\n";
1382 CvtOS << " switch (Kind) {\n";
1383 CvtOS << " default:\n";
1385 // Start the enum, which we will generate inline.
1387 OS << "// Unified function for converting operands to MCInst instances.\n\n";
1388 OS << "enum ConversionKind {\n";
1390 // TargetOperandClass - This is the target's operand class, like X86Operand.
1391 std::string TargetOperandClass = Target.getName() + "Operand";
1393 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1394 ie = Infos.end(); it != ie; ++it) {
1395 MatchableInfo &II = **it;
1397 // Build the conversion function signature.
1398 std::string Signature = "Convert";
1399 std::string CaseBody;
1400 raw_string_ostream CaseOS(CaseBody);
1402 // Compute the convert enum and the case body.
1403 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1404 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1406 // Generate code to populate each result operand.
1407 switch (OpInfo.Kind) {
1408 case MatchableInfo::ResOperand::RenderAsmOperand: {
1409 // This comes from something we parsed.
1410 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1412 // Registers are always converted the same, don't duplicate the
1413 // conversion function based on them.
1415 if (Op.Class->isRegisterClass())
1418 Signature += Op.Class->ClassName;
1419 Signature += utostr(OpInfo.MINumOperands);
1420 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1422 CaseOS << " ((" << TargetOperandClass << "*)Operands["
1423 << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod
1424 << "(Inst, " << OpInfo.MINumOperands << ");\n";
1428 case MatchableInfo::ResOperand::TiedOperand: {
1429 // If this operand is tied to a previous one, just copy the MCInst
1430 // operand from the earlier one.We can only tie single MCOperand values.
1431 //assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1432 unsigned TiedOp = OpInfo.TiedOperandNum;
1433 assert(i > TiedOp && "Tied operand preceeds its target!");
1434 CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
1435 Signature += "__Tie" + utostr(TiedOp);
1438 case MatchableInfo::ResOperand::ImmOperand: {
1439 int64_t Val = OpInfo.ImmVal;
1440 CaseOS << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n";
1441 Signature += "__imm" + itostr(Val);
1444 case MatchableInfo::ResOperand::RegOperand: {
1445 if (OpInfo.Register == 0) {
1446 CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
1447 Signature += "__reg0";
1449 std::string N = getQualifiedName(OpInfo.Register);
1450 CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n";
1451 Signature += "__reg" + OpInfo.Register->getName();
1457 II.ConversionFnKind = Signature;
1459 // Check if we have already generated this signature.
1460 if (!GeneratedFns.insert(Signature).second)
1463 // If not, emit it now. Add to the enum list.
1464 OS << " " << Signature << ",\n";
1466 CvtOS << " case " << Signature << ":\n";
1467 CvtOS << CaseOS.str();
1468 CvtOS << " return;\n";
1471 // Finish the convert function.
1476 // Finish the enum, and drop the convert function after it.
1478 OS << " NumConversionVariants\n";
1484 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1485 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1486 std::vector<ClassInfo*> &Infos,
1488 OS << "namespace {\n\n";
1490 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1491 << "/// instruction matching.\n";
1492 OS << "enum MatchClassKind {\n";
1493 OS << " InvalidMatchClass = 0,\n";
1494 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1495 ie = Infos.end(); it != ie; ++it) {
1496 ClassInfo &CI = **it;
1497 OS << " " << CI.Name << ", // ";
1498 if (CI.Kind == ClassInfo::Token) {
1499 OS << "'" << CI.ValueName << "'\n";
1500 } else if (CI.isRegisterClass()) {
1501 if (!CI.ValueName.empty())
1502 OS << "register class '" << CI.ValueName << "'\n";
1504 OS << "derived register class\n";
1506 OS << "user defined class '" << CI.ValueName << "'\n";
1509 OS << " NumMatchClassKinds\n";
1515 /// EmitClassifyOperand - Emit the function to classify an operand.
1516 static void EmitClassifyOperand(AsmMatcherInfo &Info,
1518 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
1519 << " " << Info.Target.getName() << "Operand &Operand = *("
1520 << Info.Target.getName() << "Operand*)GOp;\n";
1523 OS << " if (Operand.isToken())\n";
1524 OS << " return MatchTokenString(Operand.getToken());\n\n";
1526 // Classify registers.
1528 // FIXME: Don't hardcode isReg, getReg.
1529 OS << " if (Operand.isReg()) {\n";
1530 OS << " switch (Operand.getReg()) {\n";
1531 OS << " default: return InvalidMatchClass;\n";
1532 for (std::map<Record*, ClassInfo*>::iterator
1533 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1535 OS << " case " << Info.Target.getName() << "::"
1536 << it->first->getName() << ": return " << it->second->Name << ";\n";
1540 // Classify user defined operands. To do so, we need to perform a topological
1541 // sort of the superclass relationship graph so that we always match the
1542 // narrowest type first.
1544 // Collect the incoming edge counts for each class.
1545 std::map<ClassInfo*, unsigned> IncomingEdges;
1546 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1547 ie = Info.Classes.end(); it != ie; ++it) {
1548 ClassInfo &CI = **it;
1550 if (!CI.isUserClass())
1553 for (std::vector<ClassInfo*>::iterator SI = CI.SuperClasses.begin(),
1554 SE = CI.SuperClasses.end(); SI != SE; ++SI)
1555 ++IncomingEdges[*SI];
1558 // Initialize a worklist of classes with no incoming edges.
1559 std::vector<ClassInfo*> LeafClasses;
1560 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1561 ie = Info.Classes.end(); it != ie; ++it) {
1562 if (!IncomingEdges[*it])
1563 LeafClasses.push_back(*it);
1566 // Iteratively pop the list, process that class, and update the incoming
1567 // edge counts for its super classes. When a superclass reaches zero
1568 // incoming edges, push it onto the worklist for processing.
1569 while (!LeafClasses.empty()) {
1570 ClassInfo &CI = *LeafClasses.back();
1571 LeafClasses.pop_back();
1573 if (!CI.isUserClass())
1576 OS << " // '" << CI.ClassName << "' class";
1577 if (!CI.SuperClasses.empty()) {
1578 OS << ", subclass of ";
1579 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
1581 OS << "'" << CI.SuperClasses[i]->ClassName << "'";
1582 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
1584 --IncomingEdges[CI.SuperClasses[i]];
1585 if (!IncomingEdges[CI.SuperClasses[i]])
1586 LeafClasses.push_back(CI.SuperClasses[i]);
1591 OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
1593 // Validate subclass relationships.
1594 if (!CI.SuperClasses.empty()) {
1595 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
1596 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
1597 << "() && \"Invalid class relationship!\");\n";
1600 OS << " return " << CI.Name << ";\n";
1604 OS << " return InvalidMatchClass;\n";
1608 /// EmitIsSubclass - Emit the subclass predicate function.
1609 static void EmitIsSubclass(CodeGenTarget &Target,
1610 std::vector<ClassInfo*> &Infos,
1612 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1613 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1614 OS << " if (A == B)\n";
1615 OS << " return true;\n\n";
1617 OS << " switch (A) {\n";
1618 OS << " default:\n";
1619 OS << " return false;\n";
1620 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1621 ie = Infos.end(); it != ie; ++it) {
1622 ClassInfo &A = **it;
1624 if (A.Kind != ClassInfo::Token) {
1625 std::vector<StringRef> SuperClasses;
1626 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1627 ie = Infos.end(); it != ie; ++it) {
1628 ClassInfo &B = **it;
1630 if (&A != &B && A.isSubsetOf(B))
1631 SuperClasses.push_back(B.Name);
1634 if (SuperClasses.empty())
1637 OS << "\n case " << A.Name << ":\n";
1639 if (SuperClasses.size() == 1) {
1640 OS << " return B == " << SuperClasses.back() << ";\n";
1644 OS << " switch (B) {\n";
1645 OS << " default: return false;\n";
1646 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1647 OS << " case " << SuperClasses[i] << ": return true;\n";
1657 /// EmitMatchTokenString - Emit the function to match a token string to the
1658 /// appropriate match class value.
1659 static void EmitMatchTokenString(CodeGenTarget &Target,
1660 std::vector<ClassInfo*> &Infos,
1662 // Construct the match list.
1663 std::vector<StringMatcher::StringPair> Matches;
1664 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1665 ie = Infos.end(); it != ie; ++it) {
1666 ClassInfo &CI = **it;
1668 if (CI.Kind == ClassInfo::Token)
1669 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1670 "return " + CI.Name + ";"));
1673 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1675 StringMatcher("Name", Matches, OS).Emit();
1677 OS << " return InvalidMatchClass;\n";
1681 /// EmitMatchRegisterName - Emit the function to match a string to the target
1682 /// specific register enum.
1683 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1685 // Construct the match list.
1686 std::vector<StringMatcher::StringPair> Matches;
1687 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
1688 const CodeGenRegister &Reg = Target.getRegisters()[i];
1689 if (Reg.TheDef->getValueAsString("AsmName").empty())
1692 Matches.push_back(StringMatcher::StringPair(
1693 Reg.TheDef->getValueAsString("AsmName"),
1694 "return " + utostr(i + 1) + ";"));
1697 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1699 StringMatcher("Name", Matches, OS).Emit();
1701 OS << " return 0;\n";
1705 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1707 static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1709 OS << "// Flags for subtarget features that participate in "
1710 << "instruction matching.\n";
1711 OS << "enum SubtargetFeatureFlag {\n";
1712 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1713 it = Info.SubtargetFeatures.begin(),
1714 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1715 SubtargetFeatureInfo &SFI = *it->second;
1716 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1718 OS << " Feature_None = 0\n";
1722 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1723 /// available features given a subtarget.
1724 static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
1726 std::string ClassName =
1727 Info.AsmParser->getValueAsString("AsmParserClassName");
1729 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1730 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1731 << "Subtarget *Subtarget) const {\n";
1732 OS << " unsigned Features = 0;\n";
1733 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1734 it = Info.SubtargetFeatures.begin(),
1735 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1736 SubtargetFeatureInfo &SFI = *it->second;
1737 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1739 OS << " Features |= " << SFI.getEnumName() << ";\n";
1741 OS << " return Features;\n";
1745 static std::string GetAliasRequiredFeatures(Record *R,
1746 const AsmMatcherInfo &Info) {
1747 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
1749 unsigned NumFeatures = 0;
1750 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
1751 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
1754 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
1755 "' is not marked as an AssemblerPredicate!");
1760 Result += F->getEnumName();
1764 if (NumFeatures > 1)
1765 Result = '(' + Result + ')';
1769 /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
1770 /// emit a function for them and return true, otherwise return false.
1771 static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
1772 // Ignore aliases when match-prefix is set.
1773 if (!MatchPrefix.empty())
1776 std::vector<Record*> Aliases =
1777 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
1778 if (Aliases.empty()) return false;
1780 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
1781 "unsigned Features) {\n";
1783 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
1784 // iteration order of the map is stable.
1785 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
1787 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
1788 Record *R = Aliases[i];
1789 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
1792 // Process each alias a "from" mnemonic at a time, building the code executed
1793 // by the string remapper.
1794 std::vector<StringMatcher::StringPair> Cases;
1795 for (std::map<std::string, std::vector<Record*> >::iterator
1796 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
1798 const std::vector<Record*> &ToVec = I->second;
1800 // Loop through each alias and emit code that handles each case. If there
1801 // are two instructions without predicates, emit an error. If there is one,
1803 std::string MatchCode;
1804 int AliasWithNoPredicate = -1;
1806 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
1807 Record *R = ToVec[i];
1808 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
1810 // If this unconditionally matches, remember it for later and diagnose
1812 if (FeatureMask.empty()) {
1813 if (AliasWithNoPredicate != -1) {
1814 // We can't have two aliases from the same mnemonic with no predicate.
1815 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
1816 "two MnemonicAliases with the same 'from' mnemonic!");
1817 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
1820 AliasWithNoPredicate = i;
1824 if (!MatchCode.empty())
1825 MatchCode += "else ";
1826 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
1827 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
1830 if (AliasWithNoPredicate != -1) {
1831 Record *R = ToVec[AliasWithNoPredicate];
1832 if (!MatchCode.empty())
1833 MatchCode += "else\n ";
1834 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
1837 MatchCode += "return;";
1839 Cases.push_back(std::make_pair(I->first, MatchCode));
1843 StringMatcher("Mnemonic", Cases, OS).Emit();
1849 void AsmMatcherEmitter::run(raw_ostream &OS) {
1850 CodeGenTarget Target(Records);
1851 Record *AsmParser = Target.getAsmParser();
1852 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
1854 // Compute the information on the instructions to match.
1855 AsmMatcherInfo Info(AsmParser, Target, Records);
1858 // Sort the instruction table using the partial order on classes. We use
1859 // stable_sort to ensure that ambiguous instructions are still
1860 // deterministically ordered.
1861 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
1862 less_ptr<MatchableInfo>());
1864 DEBUG_WITH_TYPE("instruction_info", {
1865 for (std::vector<MatchableInfo*>::iterator
1866 it = Info.Matchables.begin(), ie = Info.Matchables.end();
1871 // Check for ambiguous matchables.
1872 DEBUG_WITH_TYPE("ambiguous_instrs", {
1873 unsigned NumAmbiguous = 0;
1874 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
1875 for (unsigned j = i + 1; j != e; ++j) {
1876 MatchableInfo &A = *Info.Matchables[i];
1877 MatchableInfo &B = *Info.Matchables[j];
1879 if (A.CouldMatchAmiguouslyWith(B)) {
1880 errs() << "warning: ambiguous matchables:\n";
1882 errs() << "\nis incomparable with:\n";
1890 errs() << "warning: " << NumAmbiguous
1891 << " ambiguous matchables!\n";
1894 // Write the output.
1896 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1898 // Information for the class declaration.
1899 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
1900 OS << "#undef GET_ASSEMBLER_HEADER\n";
1901 OS << " // This should be included into the middle of the declaration of \n";
1902 OS << " // your subclasses implementation of TargetAsmParser.\n";
1903 OS << " unsigned ComputeAvailableFeatures(const " <<
1904 Target.getName() << "Subtarget *Subtarget) const;\n";
1905 OS << " enum MatchResultTy {\n";
1906 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n";
1907 OS << " Match_MissingFeature\n";
1909 OS << " MatchResultTy MatchInstructionImpl(\n";
1910 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
1911 OS << " MCInst &Inst, unsigned &ErrorInfo);\n\n";
1912 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
1914 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
1915 OS << "#undef GET_REGISTER_MATCHER\n\n";
1917 // Emit the subtarget feature enumeration.
1918 EmitSubtargetFeatureFlagEnumeration(Info, OS);
1920 // Emit the function to match a register name to number.
1921 EmitMatchRegisterName(Target, AsmParser, OS);
1923 OS << "#endif // GET_REGISTER_MATCHER\n\n";
1926 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
1927 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
1929 // Generate the function that remaps for mnemonic aliases.
1930 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
1932 // Generate the unified function to convert operands into an MCInst.
1933 EmitConvertToMCInst(Target, Info.Matchables, OS);
1935 // Emit the enumeration for classes which participate in matching.
1936 EmitMatchClassEnumeration(Target, Info.Classes, OS);
1938 // Emit the routine to match token strings to their match class.
1939 EmitMatchTokenString(Target, Info.Classes, OS);
1941 // Emit the routine to classify an operand.
1942 EmitClassifyOperand(Info, OS);
1944 // Emit the subclass predicate routine.
1945 EmitIsSubclass(Target, Info.Classes, OS);
1947 // Emit the available features compute function.
1948 EmitComputeAvailableFeatures(Info, OS);
1951 size_t MaxNumOperands = 0;
1952 for (std::vector<MatchableInfo*>::const_iterator it =
1953 Info.Matchables.begin(), ie = Info.Matchables.end();
1955 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
1958 // Emit the static match table; unused classes get initalized to 0 which is
1959 // guaranteed to be InvalidMatchClass.
1961 // FIXME: We can reduce the size of this table very easily. First, we change
1962 // it so that store the kinds in separate bit-fields for each index, which
1963 // only needs to be the max width used for classes at that index (we also need
1964 // to reject based on this during classification). If we then make sure to
1965 // order the match kinds appropriately (putting mnemonics last), then we
1966 // should only end up using a few bits for each class, especially the ones
1967 // following the mnemonic.
1968 OS << "namespace {\n";
1969 OS << " struct MatchEntry {\n";
1970 OS << " unsigned Opcode;\n";
1971 OS << " const char *Mnemonic;\n";
1972 OS << " ConversionKind ConvertFn;\n";
1973 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1974 OS << " unsigned RequiredFeatures;\n";
1977 OS << "// Predicate for searching for an opcode.\n";
1978 OS << " struct LessOpcode {\n";
1979 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
1980 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
1982 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
1983 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
1985 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
1986 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
1990 OS << "} // end anonymous namespace.\n\n";
1992 OS << "static const MatchEntry MatchTable["
1993 << Info.Matchables.size() << "] = {\n";
1995 for (std::vector<MatchableInfo*>::const_iterator it =
1996 Info.Matchables.begin(), ie = Info.Matchables.end();
1998 MatchableInfo &II = **it;
2001 OS << " { " << Target.getName() << "::"
2002 << II.getResultInst()->TheDef->getName() << ", \"" << II.Mnemonic << "\""
2003 << ", " << II.ConversionFnKind << ", { ";
2004 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2005 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2008 OS << Op.Class->Name;
2012 // Write the required features mask.
2013 if (!II.RequiredFeatures.empty()) {
2014 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2016 OS << II.RequiredFeatures[i]->getEnumName();
2026 // Finally, build the match function.
2027 OS << Target.getName() << ClassName << "::MatchResultTy "
2028 << Target.getName() << ClassName << "::\n"
2029 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2031 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
2033 // Emit code to get the available features.
2034 OS << " // Get the current feature set.\n";
2035 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2037 OS << " // Get the instruction mnemonic, which is the first token.\n";
2038 OS << " StringRef Mnemonic = ((" << Target.getName()
2039 << "Operand*)Operands[0])->getToken();\n\n";
2041 if (HasMnemonicAliases) {
2042 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2043 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
2046 // Emit code to compute the class list for this operand vector.
2047 OS << " // Eliminate obvious mismatches.\n";
2048 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2049 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2050 OS << " return Match_InvalidOperand;\n";
2053 OS << " // Compute the class list for this operand vector.\n";
2054 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
2055 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n";
2056 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n";
2058 OS << " // Check for invalid operands before matching.\n";
2059 OS << " if (Classes[i-1] == InvalidMatchClass) {\n";
2060 OS << " ErrorInfo = i;\n";
2061 OS << " return Match_InvalidOperand;\n";
2065 OS << " // Mark unused classes.\n";
2066 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; "
2067 << "i != e; ++i)\n";
2068 OS << " Classes[i] = InvalidMatchClass;\n\n";
2070 OS << " // Some state to try to produce better error messages.\n";
2071 OS << " bool HadMatchOtherThanFeatures = false;\n\n";
2072 OS << " // Set ErrorInfo to the operand that mismatches if it is \n";
2073 OS << " // wrong for all instances of the instruction.\n";
2074 OS << " ErrorInfo = ~0U;\n";
2076 // Emit code to search the table.
2077 OS << " // Search the table.\n";
2078 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2079 OS << " std::equal_range(MatchTable, MatchTable+"
2080 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
2082 OS << " // Return a more specific error code if no mnemonics match.\n";
2083 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2084 OS << " return Match_MnemonicFail;\n\n";
2086 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2087 << "*ie = MnemonicRange.second;\n";
2088 OS << " it != ie; ++it) {\n";
2090 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2091 OS << " assert(Mnemonic == it->Mnemonic);\n";
2093 // Emit check that the subclasses match.
2094 OS << " bool OperandsValid = true;\n";
2095 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2096 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n";
2097 OS << " continue;\n";
2098 OS << " // If this operand is broken for all of the instances of this\n";
2099 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2100 OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n";
2101 OS << " ErrorInfo = i+1;\n";
2103 OS << " ErrorInfo = ~0U;";
2104 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2105 OS << " OperandsValid = false;\n";
2109 OS << " if (!OperandsValid) continue;\n";
2111 // Emit check that the required features are available.
2112 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2113 << "!= it->RequiredFeatures) {\n";
2114 OS << " HadMatchOtherThanFeatures = true;\n";
2115 OS << " continue;\n";
2119 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2121 // Call the post-processing function, if used.
2122 std::string InsnCleanupFn =
2123 AsmParser->getValueAsString("AsmParserInstCleanup");
2124 if (!InsnCleanupFn.empty())
2125 OS << " " << InsnCleanupFn << "(Inst);\n";
2127 OS << " return Match_Success;\n";
2130 OS << " // Okay, we had no match. Try to return a useful error code.\n";
2131 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
2132 OS << " return Match_InvalidOperand;\n";
2135 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";