1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures.
13 // The input to the target specific matcher is a list of literal tokens and
14 // operands. The target specific parser should generally eliminate any syntax
15 // which is not relevant for matching; for example, comma tokens should have
16 // already been consumed and eliminated by the parser. Most instructions will
17 // end up with a single literal token (the instruction name) and some number of
20 // Some example inputs, for X86:
21 // 'addl' (immediate ...) (register ...)
22 // 'add' (immediate ...) (memory ...)
25 // The assembly matcher is responsible for converting this input into a precise
26 // machine instruction (i.e., an instruction with a well defined encoding). This
27 // mapping has several properties which complicate matching:
29 // - It may be ambiguous; many architectures can legally encode particular
30 // variants of an instruction in different ways (for example, using a smaller
31 // encoding for small immediates). Such ambiguities should never be
32 // arbitrarily resolved by the assembler, the assembler is always responsible
33 // for choosing the "best" available instruction.
35 // - It may depend on the subtarget or the assembler context. Instructions
36 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
37 // an SSE instruction in a file being assembled for i486) should be accepted
38 // and rejected by the assembler front end. However, if the proper encoding
39 // for an instruction is dependent on the assembler context then the matcher
40 // is responsible for selecting the correct machine instruction for the
43 // The core matching algorithm attempts to exploit the regularity in most
44 // instruction sets to quickly determine the set of possibly matching
45 // instructions, and the simplify the generated code. Additionally, this helps
46 // to ensure that the ambiguities are intentionally resolved by the user.
48 // The matching is divided into two distinct phases:
50 // 1. Classification: Each operand is mapped to the unique set which (a)
51 // contains it, and (b) is the largest such subset for which a single
52 // instruction could match all members.
54 // For register classes, we can generate these subgroups automatically. For
55 // arbitrary operands, we expect the user to define the classes and their
56 // relations to one another (for example, 8-bit signed immediates as a
57 // subset of 32-bit immediates).
59 // By partitioning the operands in this way, we guarantee that for any
60 // tuple of classes, any single instruction must match either all or none
61 // of the sets of operands which could classify to that tuple.
63 // In addition, the subset relation amongst classes induces a partial order
64 // on such tuples, which we use to resolve ambiguities.
66 // 2. The input can now be treated as a tuple of classes (static tokens are
67 // simple singleton sets). Each such tuple should generally map to a single
68 // instruction (we currently ignore cases where this isn't true, whee!!!),
69 // which we can emit a simple matcher for.
71 //===----------------------------------------------------------------------===//
73 #include "AsmMatcherEmitter.h"
74 #include "CodeGenTarget.h"
76 #include "StringMatcher.h"
77 #include "llvm/ADT/OwningPtr.h"
78 #include "llvm/ADT/PointerUnion.h"
79 #include "llvm/ADT/SmallPtrSet.h"
80 #include "llvm/ADT/SmallVector.h"
81 #include "llvm/ADT/STLExtras.h"
82 #include "llvm/ADT/StringExtras.h"
83 #include "llvm/Support/CommandLine.h"
84 #include "llvm/Support/Debug.h"
89 static cl::opt<std::string>
90 MatchPrefix("match-prefix", cl::init(""),
91 cl::desc("Only match instructions with the given prefix"));
96 struct SubtargetFeatureInfo;
98 /// ClassInfo - Helper class for storing the information about a particular
99 /// class of operands which can be matched.
102 /// Invalid kind, for use as a sentinel value.
105 /// The class for a particular token.
108 /// The (first) register class, subsequent register classes are
109 /// RegisterClass0+1, and so on.
112 /// The (first) user defined class, subsequent user defined classes are
113 /// UserClass0+1, and so on.
117 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
118 /// N) for the Nth user defined class.
121 /// SuperClasses - The super classes of this class. Note that for simplicities
122 /// sake user operands only record their immediate super class, while register
123 /// operands include all superclasses.
124 std::vector<ClassInfo*> SuperClasses;
126 /// Name - The full class name, suitable for use in an enum.
129 /// ClassName - The unadorned generic name for this class (e.g., Token).
130 std::string ClassName;
132 /// ValueName - The name of the value this class represents; for a token this
133 /// is the literal token string, for an operand it is the TableGen class (or
134 /// empty if this is a derived class).
135 std::string ValueName;
137 /// PredicateMethod - The name of the operand method to test whether the
138 /// operand matches this class; this is not valid for Token or register kinds.
139 std::string PredicateMethod;
141 /// RenderMethod - The name of the operand method to add this operand to an
142 /// MCInst; this is not valid for Token or register kinds.
143 std::string RenderMethod;
145 /// For register classes, the records for all the registers in this class.
146 std::set<Record*> Registers;
149 /// isRegisterClass() - Check if this is a register class.
150 bool isRegisterClass() const {
151 return Kind >= RegisterClass0 && Kind < UserClass0;
154 /// isUserClass() - Check if this is a user defined class.
155 bool isUserClass() const {
156 return Kind >= UserClass0;
159 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
160 /// are related if they are in the same class hierarchy.
161 bool isRelatedTo(const ClassInfo &RHS) const {
162 // Tokens are only related to tokens.
163 if (Kind == Token || RHS.Kind == Token)
164 return Kind == Token && RHS.Kind == Token;
166 // Registers classes are only related to registers classes, and only if
167 // their intersection is non-empty.
168 if (isRegisterClass() || RHS.isRegisterClass()) {
169 if (!isRegisterClass() || !RHS.isRegisterClass())
172 std::set<Record*> Tmp;
173 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
174 std::set_intersection(Registers.begin(), Registers.end(),
175 RHS.Registers.begin(), RHS.Registers.end(),
181 // Otherwise we have two users operands; they are related if they are in the
182 // same class hierarchy.
184 // FIXME: This is an oversimplification, they should only be related if they
185 // intersect, however we don't have that information.
186 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
187 const ClassInfo *Root = this;
188 while (!Root->SuperClasses.empty())
189 Root = Root->SuperClasses.front();
191 const ClassInfo *RHSRoot = &RHS;
192 while (!RHSRoot->SuperClasses.empty())
193 RHSRoot = RHSRoot->SuperClasses.front();
195 return Root == RHSRoot;
198 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
199 bool isSubsetOf(const ClassInfo &RHS) const {
200 // This is a subset of RHS if it is the same class...
204 // ... or if any of its super classes are a subset of RHS.
205 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
206 ie = SuperClasses.end(); it != ie; ++it)
207 if ((*it)->isSubsetOf(RHS))
213 /// operator< - Compare two classes.
214 bool operator<(const ClassInfo &RHS) const {
218 // Unrelated classes can be ordered by kind.
219 if (!isRelatedTo(RHS))
220 return Kind < RHS.Kind;
224 assert(0 && "Invalid kind!");
226 // Tokens are comparable by value.
228 // FIXME: Compare by enum value.
229 return ValueName < RHS.ValueName;
232 // This class preceeds the RHS if it is a proper subset of the RHS.
235 if (RHS.isSubsetOf(*this))
238 // Otherwise, order by name to ensure we have a total ordering.
239 return ValueName < RHS.ValueName;
244 /// MatchableInfo - Helper class for storing the necessary information for an
245 /// instruction or alias which is capable of being matched.
246 struct MatchableInfo {
248 /// Token - This is the token that the operand came from.
251 /// The unique class instance this operand should match.
254 /// The operand name this is, if anything.
257 explicit AsmOperand(StringRef T) : Token(T), Class(0) {}
260 /// ResOperand - This represents a single operand in the result instruction
261 /// generated by the match. In cases (like addressing modes) where a single
262 /// assembler operand expands to multiple MCOperands, this represents the
263 /// single assembler operand, not the MCOperand.
266 /// RenderAsmOperand - This represents an operand result that is
267 /// generated by calling the render method on the assembly operand. The
268 /// corresponding AsmOperand is specified by AsmOperandNum.
271 /// TiedOperand - This represents a result operand that is a duplicate of
272 /// a previous result operand.
275 /// ImmOperand - This represents an immediate value that is dumped into
281 /// This is the operand # in the AsmOperands list that this should be
283 unsigned AsmOperandNum;
285 /// TiedOperandNum - This is the (earlier) result operand that should be
287 unsigned TiedOperandNum;
289 /// ImmVal - This is the immediate value added to the instruction.
293 /// OpInfo - This is the information about the instruction operand that is
295 const CGIOperandList::OperandInfo *OpInfo;
297 static ResOperand getRenderedOp(unsigned AsmOpNum,
298 const CGIOperandList::OperandInfo *Op) {
300 X.Kind = RenderAsmOperand;
301 X.AsmOperandNum = AsmOpNum;
306 static ResOperand getTiedOp(unsigned TiedOperandNum,
307 const CGIOperandList::OperandInfo *Op) {
309 X.Kind = TiedOperand;
310 X.TiedOperandNum = TiedOperandNum;
315 static ResOperand getImmOp(int64_t Val,
316 const CGIOperandList::OperandInfo *Op) {
325 /// TheDef - This is the definition of the instruction or InstAlias that this
326 /// matchable came from.
327 Record *const TheDef;
329 /// DefRec - This is the definition that it came from.
330 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
332 const CodeGenInstruction *getResultInst() const {
333 if (DefRec.is<const CodeGenInstruction*>())
334 return DefRec.get<const CodeGenInstruction*>();
335 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
338 /// ResOperands - This is the operand list that should be built for the result
340 std::vector<ResOperand> ResOperands;
342 /// AsmString - The assembly string for this instruction (with variants
343 /// removed), e.g. "movsx $src, $dst".
344 std::string AsmString;
346 /// Mnemonic - This is the first token of the matched instruction, its
350 /// AsmOperands - The textual operands that this instruction matches,
351 /// annotated with a class and where in the OperandList they were defined.
352 /// This directly corresponds to the tokenized AsmString after the mnemonic is
354 SmallVector<AsmOperand, 4> AsmOperands;
356 /// Predicates - The required subtarget features to match this instruction.
357 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
359 /// ConversionFnKind - The enum value which is passed to the generated
360 /// ConvertToMCInst to convert parsed operands into an MCInst for this
362 std::string ConversionFnKind;
364 MatchableInfo(const CodeGenInstruction &CGI)
365 : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) {
368 MatchableInfo(const CodeGenInstAlias *Alias)
369 : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) {
372 void Initialize(const AsmMatcherInfo &Info,
373 SmallPtrSet<Record*, 16> &SingletonRegisters);
375 /// Validate - Return true if this matchable is a valid thing to match against
376 /// and perform a bunch of validity checking.
377 bool Validate(StringRef CommentDelimiter, bool Hack) const;
379 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
380 /// register, return the Record for it, otherwise return null.
381 Record *getSingletonRegisterForAsmOperand(unsigned i,
382 const AsmMatcherInfo &Info) const;
384 int FindAsmOperandNamed(StringRef N) const {
385 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
386 if (N == AsmOperands[i].SrcOpName)
391 void BuildInstructionResultOperands();
392 void BuildAliasResultOperands();
394 /// operator< - Compare two matchables.
395 bool operator<(const MatchableInfo &RHS) const {
396 // The primary comparator is the instruction mnemonic.
397 if (Mnemonic != RHS.Mnemonic)
398 return Mnemonic < RHS.Mnemonic;
400 if (AsmOperands.size() != RHS.AsmOperands.size())
401 return AsmOperands.size() < RHS.AsmOperands.size();
403 // Compare lexicographically by operand. The matcher validates that other
404 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith().
405 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
406 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
408 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
415 /// CouldMatchAmiguouslyWith - Check whether this matchable could
416 /// ambiguously match the same set of operands as \arg RHS (without being a
417 /// strictly superior match).
418 bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) {
419 // The primary comparator is the instruction mnemonic.
420 if (Mnemonic != RHS.Mnemonic)
423 // The number of operands is unambiguous.
424 if (AsmOperands.size() != RHS.AsmOperands.size())
427 // Otherwise, make sure the ordering of the two instructions is unambiguous
428 // by checking that either (a) a token or operand kind discriminates them,
429 // or (b) the ordering among equivalent kinds is consistent.
431 // Tokens and operand kinds are unambiguous (assuming a correct target
433 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
434 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
435 AsmOperands[i].Class->Kind == ClassInfo::Token)
436 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
437 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
440 // Otherwise, this operand could commute if all operands are equivalent, or
441 // there is a pair of operands that compare less than and a pair that
442 // compare greater than.
443 bool HasLT = false, HasGT = false;
444 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
445 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
447 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
451 return !(HasLT ^ HasGT);
457 void TokenizeAsmString(const AsmMatcherInfo &Info);
460 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
461 /// feature which participates in instruction matching.
462 struct SubtargetFeatureInfo {
463 /// \brief The predicate record for this feature.
466 /// \brief An unique index assigned to represent this feature.
469 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
471 /// \brief The name of the enumerated constant identifying this feature.
472 std::string getEnumName() const {
473 return "Feature_" + TheDef->getName();
477 class AsmMatcherInfo {
479 /// The tablegen AsmParser record.
482 /// Target - The target information.
483 CodeGenTarget &Target;
485 /// The AsmParser "RegisterPrefix" value.
486 std::string RegisterPrefix;
488 /// The classes which are needed for matching.
489 std::vector<ClassInfo*> Classes;
491 /// The information on the matchables to match.
492 std::vector<MatchableInfo*> Matchables;
494 /// Map of Register records to their class information.
495 std::map<Record*, ClassInfo*> RegisterClasses;
497 /// Map of Predicate records to their subtarget information.
498 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
501 /// Map of token to class information which has already been constructed.
502 std::map<std::string, ClassInfo*> TokenClasses;
504 /// Map of RegisterClass records to their class information.
505 std::map<Record*, ClassInfo*> RegisterClassClasses;
507 /// Map of AsmOperandClass records to their class information.
508 std::map<Record*, ClassInfo*> AsmOperandClasses;
511 /// getTokenClass - Lookup or create the class for the given token.
512 ClassInfo *getTokenClass(StringRef Token);
514 /// getOperandClass - Lookup or create the class for the given operand.
515 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI);
517 /// BuildRegisterClasses - Build the ClassInfo* instances for register
519 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
521 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
523 void BuildOperandClasses();
525 void BuildInstructionOperandReference(MatchableInfo *II,
527 MatchableInfo::AsmOperand &Op);
528 void BuildAliasOperandReference(MatchableInfo *II,
530 MatchableInfo::AsmOperand &Op);
533 AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target);
535 /// BuildInfo - Construct the various tables used during matching.
538 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
540 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
541 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
542 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
543 SubtargetFeatures.find(Def);
544 return I == SubtargetFeatures.end() ? 0 : I->second;
550 void MatchableInfo::dump() {
551 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
553 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
554 AsmOperand &Op = AsmOperands[i];
555 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
556 errs() << '\"' << Op.Token << "\"\n";
560 void MatchableInfo::Initialize(const AsmMatcherInfo &Info,
561 SmallPtrSet<Record*, 16> &SingletonRegisters) {
562 // TODO: Eventually support asmparser for Variant != 0.
563 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0);
565 TokenizeAsmString(Info);
567 // Compute the require features.
568 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
569 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
570 if (SubtargetFeatureInfo *Feature =
571 Info.getSubtargetFeature(Predicates[i]))
572 RequiredFeatures.push_back(Feature);
574 // Collect singleton registers, if used.
575 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
576 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
577 SingletonRegisters.insert(Reg);
581 /// TokenizeAsmString - Tokenize a simplified assembly string.
582 void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) {
583 StringRef String = AsmString;
586 for (unsigned i = 0, e = String.size(); i != e; ++i) {
596 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
599 if (!isspace(String[i]) && String[i] != ',')
600 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
606 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
610 assert(i != String.size() && "Invalid quoted character");
611 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
616 // If this isn't "${", treat like a normal token.
617 if (i + 1 == String.size() || String[i + 1] != '{') {
619 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
627 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
631 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
632 assert(End != String.end() && "Missing brace in operand reference!");
633 size_t EndPos = End - String.begin();
634 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
642 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
651 if (InTok && Prev != String.size())
652 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
654 // The first token of the instruction is the mnemonic, which must be a
655 // simple string, not a $foo variable or a singleton register.
656 assert(!AsmOperands.empty() && "Instruction has no tokens?");
657 Mnemonic = AsmOperands[0].Token;
658 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info))
659 throw TGError(TheDef->getLoc(),
660 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
662 // Remove the first operand, it is tracked in the mnemonic field.
663 AsmOperands.erase(AsmOperands.begin());
668 bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const {
669 // Reject matchables with no .s string.
670 if (AsmString.empty())
671 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
673 // Reject any matchables with a newline in them, they should be marked
674 // isCodeGenOnly if they are pseudo instructions.
675 if (AsmString.find('\n') != std::string::npos)
676 throw TGError(TheDef->getLoc(),
677 "multiline instruction is not valid for the asmparser, "
678 "mark it isCodeGenOnly");
680 // Remove comments from the asm string. We know that the asmstring only
682 if (!CommentDelimiter.empty() &&
683 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
684 throw TGError(TheDef->getLoc(),
685 "asmstring for instruction has comment character in it, "
686 "mark it isCodeGenOnly");
688 // Reject matchables with operand modifiers, these aren't something we can
689 /// handle, the target should be refactored to use operands instead of
692 // Also, check for instructions which reference the operand multiple times;
693 // this implies a constraint we would not honor.
694 std::set<std::string> OperandNames;
695 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
696 StringRef Tok = AsmOperands[i].Token;
697 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
698 throw TGError(TheDef->getLoc(),
699 "matchable with operand modifier '" + Tok.str() +
700 "' not supported by asm matcher. Mark isCodeGenOnly!");
702 // Verify that any operand is only mentioned once.
703 // We reject aliases and ignore instructions for now.
704 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
706 throw TGError(TheDef->getLoc(),
707 "ERROR: matchable with tied operand '" + Tok.str() +
708 "' can never be matched!");
709 // FIXME: Should reject these. The ARM backend hits this with $lane in a
710 // bunch of instructions. It is unclear what the right answer is.
712 errs() << "warning: '" << TheDef->getName() << "': "
713 << "ignoring instruction with tied operand '"
714 << Tok.str() << "'\n";
724 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
725 /// register, return the register name, otherwise return a null StringRef.
726 Record *MatchableInfo::
727 getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{
728 StringRef Tok = AsmOperands[i].Token;
729 if (!Tok.startswith(Info.RegisterPrefix))
732 StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
733 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
736 // If there is no register prefix (i.e. "%" in "%eax"), then this may
737 // be some random non-register token, just ignore it.
738 if (Info.RegisterPrefix.empty())
741 // Otherwise, we have something invalid prefixed with the register prefix,
743 std::string Err = "unable to find register for '" + RegName.str() +
744 "' (which matches register prefix)";
745 throw TGError(TheDef->getLoc(), Err);
749 static std::string getEnumNameForToken(StringRef Str) {
752 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
754 case '*': Res += "_STAR_"; break;
755 case '%': Res += "_PCT_"; break;
756 case ':': Res += "_COLON_"; break;
761 Res += "_" + utostr((unsigned) *it) + "_";
768 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
769 ClassInfo *&Entry = TokenClasses[Token];
772 Entry = new ClassInfo();
773 Entry->Kind = ClassInfo::Token;
774 Entry->ClassName = "Token";
775 Entry->Name = "MCK_" + getEnumNameForToken(Token);
776 Entry->ValueName = Token;
777 Entry->PredicateMethod = "<invalid>";
778 Entry->RenderMethod = "<invalid>";
779 Classes.push_back(Entry);
786 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI) {
787 if (OI.Rec->isSubClassOf("RegisterClass")) {
788 if (ClassInfo *CI = RegisterClassClasses[OI.Rec])
790 throw TGError(OI.Rec->getLoc(), "register class has no class info!");
793 assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!");
794 Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
795 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
798 throw TGError(OI.Rec->getLoc(), "operand has no match class!");
801 void AsmMatcherInfo::
802 BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
803 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
804 const std::vector<CodeGenRegisterClass> &RegClassList =
805 Target.getRegisterClasses();
807 // The register sets used for matching.
808 std::set< std::set<Record*> > RegisterSets;
810 // Gather the defined sets.
811 for (std::vector<CodeGenRegisterClass>::const_iterator it =
812 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
813 RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
814 it->Elements.end()));
816 // Add any required singleton sets.
817 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
818 ie = SingletonRegisters.end(); it != ie; ++it) {
820 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
823 // Introduce derived sets where necessary (when a register does not determine
824 // a unique register set class), and build the mapping of registers to the set
825 // they should classify to.
826 std::map<Record*, std::set<Record*> > RegisterMap;
827 for (std::vector<CodeGenRegister>::const_iterator it = Registers.begin(),
828 ie = Registers.end(); it != ie; ++it) {
829 const CodeGenRegister &CGR = *it;
830 // Compute the intersection of all sets containing this register.
831 std::set<Record*> ContainingSet;
833 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
834 ie = RegisterSets.end(); it != ie; ++it) {
835 if (!it->count(CGR.TheDef))
838 if (ContainingSet.empty()) {
843 std::set<Record*> Tmp;
844 std::swap(Tmp, ContainingSet);
845 std::insert_iterator< std::set<Record*> > II(ContainingSet,
846 ContainingSet.begin());
847 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
850 if (!ContainingSet.empty()) {
851 RegisterSets.insert(ContainingSet);
852 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
856 // Construct the register classes.
857 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
859 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
860 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
861 ClassInfo *CI = new ClassInfo();
862 CI->Kind = ClassInfo::RegisterClass0 + Index;
863 CI->ClassName = "Reg" + utostr(Index);
864 CI->Name = "MCK_Reg" + utostr(Index);
866 CI->PredicateMethod = ""; // unused
867 CI->RenderMethod = "addRegOperands";
869 Classes.push_back(CI);
870 RegisterSetClasses.insert(std::make_pair(*it, CI));
873 // Find the superclasses; we could compute only the subgroup lattice edges,
874 // but there isn't really a point.
875 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
876 ie = RegisterSets.end(); it != ie; ++it) {
877 ClassInfo *CI = RegisterSetClasses[*it];
878 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
879 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
881 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
882 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
885 // Name the register classes which correspond to a user defined RegisterClass.
886 for (std::vector<CodeGenRegisterClass>::const_iterator
887 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
888 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
889 it->Elements.end())];
890 if (CI->ValueName.empty()) {
891 CI->ClassName = it->getName();
892 CI->Name = "MCK_" + it->getName();
893 CI->ValueName = it->getName();
895 CI->ValueName = CI->ValueName + "," + it->getName();
897 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
900 // Populate the map for individual registers.
901 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
902 ie = RegisterMap.end(); it != ie; ++it)
903 RegisterClasses[it->first] = RegisterSetClasses[it->second];
905 // Name the register classes which correspond to singleton registers.
906 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
907 ie = SingletonRegisters.end(); it != ie; ++it) {
909 ClassInfo *CI = RegisterClasses[Rec];
910 assert(CI && "Missing singleton register class info!");
912 if (CI->ValueName.empty()) {
913 CI->ClassName = Rec->getName();
914 CI->Name = "MCK_" + Rec->getName();
915 CI->ValueName = Rec->getName();
917 CI->ValueName = CI->ValueName + "," + Rec->getName();
921 void AsmMatcherInfo::BuildOperandClasses() {
922 std::vector<Record*> AsmOperands =
923 Records.getAllDerivedDefinitions("AsmOperandClass");
925 // Pre-populate AsmOperandClasses map.
926 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
927 ie = AsmOperands.end(); it != ie; ++it)
928 AsmOperandClasses[*it] = new ClassInfo();
931 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
932 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
933 ClassInfo *CI = AsmOperandClasses[*it];
934 CI->Kind = ClassInfo::UserClass0 + Index;
936 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
937 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
938 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
940 PrintError((*it)->getLoc(), "Invalid super class reference!");
944 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
946 PrintError((*it)->getLoc(), "Invalid super class reference!");
948 CI->SuperClasses.push_back(SC);
950 CI->ClassName = (*it)->getValueAsString("Name");
951 CI->Name = "MCK_" + CI->ClassName;
952 CI->ValueName = (*it)->getName();
954 // Get or construct the predicate method name.
955 Init *PMName = (*it)->getValueInit("PredicateMethod");
956 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
957 CI->PredicateMethod = SI->getValue();
959 assert(dynamic_cast<UnsetInit*>(PMName) &&
960 "Unexpected PredicateMethod field!");
961 CI->PredicateMethod = "is" + CI->ClassName;
964 // Get or construct the render method name.
965 Init *RMName = (*it)->getValueInit("RenderMethod");
966 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
967 CI->RenderMethod = SI->getValue();
969 assert(dynamic_cast<UnsetInit*>(RMName) &&
970 "Unexpected RenderMethod field!");
971 CI->RenderMethod = "add" + CI->ClassName + "Operands";
974 AsmOperandClasses[*it] = CI;
975 Classes.push_back(CI);
979 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target)
980 : AsmParser(asmParser), Target(target),
981 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
985 void AsmMatcherInfo::BuildInfo() {
986 // Build information about all of the AssemblerPredicates.
987 std::vector<Record*> AllPredicates =
988 Records.getAllDerivedDefinitions("Predicate");
989 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
990 Record *Pred = AllPredicates[i];
991 // Ignore predicates that are not intended for the assembler.
992 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
995 if (Pred->getName().empty())
996 throw TGError(Pred->getLoc(), "Predicate has no name!");
998 unsigned FeatureNo = SubtargetFeatures.size();
999 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1000 assert(FeatureNo < 32 && "Too many subtarget features!");
1003 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
1005 // Parse the instructions; we need to do this first so that we can gather the
1006 // singleton register classes.
1007 SmallPtrSet<Record*, 16> SingletonRegisters;
1008 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1009 E = Target.inst_end(); I != E; ++I) {
1010 const CodeGenInstruction &CGI = **I;
1012 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1013 // filter the set of instructions we consider.
1014 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1017 // Ignore "codegen only" instructions.
1018 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1021 // Validate the operand list to ensure we can handle this instruction.
1022 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1023 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1025 // Validate tied operands.
1026 if (OI.getTiedRegister() != -1) {
1027 // If we have a tied operand that consists of multiple MCOperands, reject
1028 // it. We reject aliases and ignore instructions for now.
1029 if (OI.MINumOperands != 1) {
1030 // FIXME: Should reject these. The ARM backend hits this with $lane
1031 // in a bunch of instructions. It is unclear what the right answer is.
1033 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1034 << "ignoring instruction with multi-operand tied operand '"
1035 << OI.Name << "'\n";
1042 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1044 II->Initialize(*this, SingletonRegisters);
1046 // Ignore instructions which shouldn't be matched and diagnose invalid
1047 // instruction definitions with an error.
1048 if (!II->Validate(CommentDelimiter, true))
1051 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1053 // FIXME: This is a total hack.
1054 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1055 StringRef(II->TheDef->getName()).endswith("_Int"))
1058 Matchables.push_back(II.take());
1061 // Parse all of the InstAlias definitions and stick them in the list of
1063 std::vector<Record*> AllInstAliases =
1064 Records.getAllDerivedDefinitions("InstAlias");
1065 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1066 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1068 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1070 II->Initialize(*this, SingletonRegisters);
1072 // Validate the alias definitions.
1073 II->Validate(CommentDelimiter, false);
1075 Matchables.push_back(II.take());
1078 // Build info for the register classes.
1079 BuildRegisterClasses(SingletonRegisters);
1081 // Build info for the user defined assembly operand classes.
1082 BuildOperandClasses();
1084 // Build the information about matchables, now that we have fully formed
1086 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1087 ie = Matchables.end(); it != ie; ++it) {
1088 MatchableInfo *II = *it;
1090 // Parse the tokens after the mnemonic.
1091 for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) {
1092 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1093 StringRef Token = Op.Token;
1095 // Check for singleton registers.
1096 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) {
1097 Op.Class = RegisterClasses[RegRecord];
1098 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1099 "Unexpected class for singleton register");
1103 // Check for simple tokens.
1104 if (Token[0] != '$') {
1105 Op.Class = getTokenClass(Token);
1109 // Otherwise this is an operand reference.
1110 StringRef OperandName;
1111 if (Token[1] == '{')
1112 OperandName = Token.substr(2, Token.size() - 3);
1114 OperandName = Token.substr(1);
1116 if (II->DefRec.is<const CodeGenInstruction*>())
1117 BuildInstructionOperandReference(II, OperandName, Op);
1119 BuildAliasOperandReference(II, OperandName, Op);
1122 if (II->DefRec.is<const CodeGenInstruction*>())
1123 II->BuildInstructionResultOperands();
1125 II->BuildAliasResultOperands();
1128 // Reorder classes so that classes preceed super classes.
1129 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1132 /// BuildInstructionOperandReference - The specified operand is a reference to a
1133 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1134 void AsmMatcherInfo::
1135 BuildInstructionOperandReference(MatchableInfo *II,
1136 StringRef OperandName,
1137 MatchableInfo::AsmOperand &Op) {
1138 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1139 const CGIOperandList &Operands = CGI.Operands;
1141 // Map this token to an operand.
1143 if (!Operands.hasOperandNamed(OperandName, Idx))
1144 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1145 OperandName.str() + "'");
1147 // Set up the operand class.
1148 Op.Class = getOperandClass(Operands[Idx]);
1150 // If the named operand is tied, canonicalize it to the untied operand.
1151 // For example, something like:
1152 // (outs GPR:$dst), (ins GPR:$src)
1153 // with an asmstring of
1155 // we want to canonicalize to:
1157 // so that we know how to provide the $dst operand when filling in the result.
1158 int OITied = Operands[Idx].getTiedRegister();
1160 // The tied operand index is an MIOperand index, find the operand that
1162 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
1163 if (Operands[i].MIOperandNo == unsigned(OITied)) {
1164 OperandName = Operands[i].Name;
1170 Op.SrcOpName = OperandName;
1173 /// BuildAliasOperandReference - When parsing an operand reference out of the
1174 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1175 /// operand reference is by looking it up in the result pattern definition.
1176 void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II,
1177 StringRef OperandName,
1178 MatchableInfo::AsmOperand &Op) {
1179 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1181 // Set up the operand class.
1182 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1183 if (CGA.ResultOperands[i].isRecord() &&
1184 CGA.ResultOperands[i].getName() == OperandName) {
1185 // It's safe to go with the first one we find, because CodeGenInstAlias
1186 // validates that all operands with the same name have the same record.
1187 unsigned ResultIdx =CGA.getResultInstOperandIndexForResultOperandIndex(i);
1188 Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx]);
1189 Op.SrcOpName = OperandName;
1193 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1194 OperandName.str() + "'");
1197 void MatchableInfo::BuildInstructionResultOperands() {
1198 const CodeGenInstruction *ResultInst = getResultInst();
1200 // Loop over all operands of the result instruction, determining how to
1202 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1203 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1205 // If this is a tied operand, just copy from the previously handled operand.
1206 int TiedOp = OpInfo.getTiedRegister();
1208 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo));
1212 // Find out what operand from the asmparser that this MCInst operand comes
1214 int SrcOperand = FindAsmOperandNamed(OpInfo.Name);
1216 if (!OpInfo.Name.empty() && SrcOperand != -1) {
1217 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo));
1221 throw TGError(TheDef->getLoc(), "Instruction '" +
1222 TheDef->getName() + "' has operand '" + OpInfo.Name +
1223 "' that doesn't appear in asm string!");
1227 void MatchableInfo::BuildAliasResultOperands() {
1228 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1229 const CodeGenInstruction *ResultInst = getResultInst();
1231 // Loop over all operands of the result instruction, determining how to
1233 unsigned AliasOpNo = 0;
1234 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1235 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1237 // If this is a tied operand, just copy from the previously handled operand.
1238 int TiedOp = OpInfo.getTiedRegister();
1240 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo));
1244 // Find out what operand from the asmparser that this MCInst operand comes
1246 if (CGA.ResultOperands[AliasOpNo].isRecord()) {
1247 StringRef Name = CGA.ResultOperands[AliasOpNo++].getName();
1248 int SrcOperand = FindAsmOperandNamed(Name);
1249 if (SrcOperand != -1) {
1250 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo));
1254 throw TGError(TheDef->getLoc(), "Instruction '" +
1255 TheDef->getName() + "' has operand '" + OpInfo.Name +
1256 "' that doesn't appear in asm string!");
1259 int64_t ImmVal = CGA.ResultOperands[AliasOpNo++].getImm();
1260 ResOperands.push_back(ResOperand::getImmOp(ImmVal, &OpInfo));
1265 static void EmitConvertToMCInst(CodeGenTarget &Target,
1266 std::vector<MatchableInfo*> &Infos,
1268 // Write the convert function to a separate stream, so we can drop it after
1270 std::string ConvertFnBody;
1271 raw_string_ostream CvtOS(ConvertFnBody);
1273 // Function we have already generated.
1274 std::set<std::string> GeneratedFns;
1276 // Start the unified conversion function.
1277 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
1278 << "unsigned Opcode,\n"
1279 << " const SmallVectorImpl<MCParsedAsmOperand*"
1280 << "> &Operands) {\n";
1281 CvtOS << " Inst.setOpcode(Opcode);\n";
1282 CvtOS << " switch (Kind) {\n";
1283 CvtOS << " default:\n";
1285 // Start the enum, which we will generate inline.
1287 OS << "// Unified function for converting operands to MCInst instances.\n\n";
1288 OS << "enum ConversionKind {\n";
1290 // TargetOperandClass - This is the target's operand class, like X86Operand.
1291 std::string TargetOperandClass = Target.getName() + "Operand";
1293 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1294 ie = Infos.end(); it != ie; ++it) {
1295 MatchableInfo &II = **it;
1297 // Build the conversion function signature.
1298 std::string Signature = "Convert";
1299 std::string CaseBody;
1300 raw_string_ostream CaseOS(CaseBody);
1302 // Compute the convert enum and the case body.
1303 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1304 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1306 // Generate code to populate each result operand.
1307 switch (OpInfo.Kind) {
1308 case MatchableInfo::ResOperand::RenderAsmOperand: {
1309 // This comes from something we parsed.
1310 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1312 // Registers are always converted the same, don't duplicate the
1313 // conversion function based on them.
1315 if (Op.Class->isRegisterClass())
1318 Signature += Op.Class->ClassName;
1319 Signature += utostr(OpInfo.OpInfo->MINumOperands);
1320 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1322 CaseOS << " ((" << TargetOperandClass << "*)Operands["
1323 << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod
1324 << "(Inst, " << OpInfo.OpInfo->MINumOperands << ");\n";
1328 case MatchableInfo::ResOperand::TiedOperand: {
1329 // If this operand is tied to a previous one, just copy the MCInst
1330 // operand from the earlier one.We can only tie single MCOperand values.
1331 //assert(OpInfo.OpInfo->MINumOperands == 1 && "Not a singular MCOperand");
1332 unsigned TiedOp = OpInfo.TiedOperandNum;
1333 assert(i > TiedOp && "Tied operand preceeds its target!");
1334 CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
1335 Signature += "__Tie" + utostr(TiedOp);
1338 case MatchableInfo::ResOperand::ImmOperand: {
1339 int64_t Val = OpInfo.ImmVal;
1340 CaseOS << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n";
1341 Signature += "__imm" + itostr(Val);
1347 II.ConversionFnKind = Signature;
1349 // Check if we have already generated this signature.
1350 if (!GeneratedFns.insert(Signature).second)
1353 // If not, emit it now. Add to the enum list.
1354 OS << " " << Signature << ",\n";
1356 CvtOS << " case " << Signature << ":\n";
1357 CvtOS << CaseOS.str();
1358 CvtOS << " return;\n";
1361 // Finish the convert function.
1366 // Finish the enum, and drop the convert function after it.
1368 OS << " NumConversionVariants\n";
1374 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1375 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1376 std::vector<ClassInfo*> &Infos,
1378 OS << "namespace {\n\n";
1380 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1381 << "/// instruction matching.\n";
1382 OS << "enum MatchClassKind {\n";
1383 OS << " InvalidMatchClass = 0,\n";
1384 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1385 ie = Infos.end(); it != ie; ++it) {
1386 ClassInfo &CI = **it;
1387 OS << " " << CI.Name << ", // ";
1388 if (CI.Kind == ClassInfo::Token) {
1389 OS << "'" << CI.ValueName << "'\n";
1390 } else if (CI.isRegisterClass()) {
1391 if (!CI.ValueName.empty())
1392 OS << "register class '" << CI.ValueName << "'\n";
1394 OS << "derived register class\n";
1396 OS << "user defined class '" << CI.ValueName << "'\n";
1399 OS << " NumMatchClassKinds\n";
1405 /// EmitClassifyOperand - Emit the function to classify an operand.
1406 static void EmitClassifyOperand(AsmMatcherInfo &Info,
1408 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
1409 << " " << Info.Target.getName() << "Operand &Operand = *("
1410 << Info.Target.getName() << "Operand*)GOp;\n";
1413 OS << " if (Operand.isToken())\n";
1414 OS << " return MatchTokenString(Operand.getToken());\n\n";
1416 // Classify registers.
1418 // FIXME: Don't hardcode isReg, getReg.
1419 OS << " if (Operand.isReg()) {\n";
1420 OS << " switch (Operand.getReg()) {\n";
1421 OS << " default: return InvalidMatchClass;\n";
1422 for (std::map<Record*, ClassInfo*>::iterator
1423 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1425 OS << " case " << Info.Target.getName() << "::"
1426 << it->first->getName() << ": return " << it->second->Name << ";\n";
1430 // Classify user defined operands.
1431 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1432 ie = Info.Classes.end(); it != ie; ++it) {
1433 ClassInfo &CI = **it;
1435 if (!CI.isUserClass())
1438 OS << " // '" << CI.ClassName << "' class";
1439 if (!CI.SuperClasses.empty()) {
1440 OS << ", subclass of ";
1441 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
1443 OS << "'" << CI.SuperClasses[i]->ClassName << "'";
1444 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
1449 OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
1451 // Validate subclass relationships.
1452 if (!CI.SuperClasses.empty()) {
1453 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
1454 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
1455 << "() && \"Invalid class relationship!\");\n";
1458 OS << " return " << CI.Name << ";\n";
1461 OS << " return InvalidMatchClass;\n";
1465 /// EmitIsSubclass - Emit the subclass predicate function.
1466 static void EmitIsSubclass(CodeGenTarget &Target,
1467 std::vector<ClassInfo*> &Infos,
1469 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1470 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1471 OS << " if (A == B)\n";
1472 OS << " return true;\n\n";
1474 OS << " switch (A) {\n";
1475 OS << " default:\n";
1476 OS << " return false;\n";
1477 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1478 ie = Infos.end(); it != ie; ++it) {
1479 ClassInfo &A = **it;
1481 if (A.Kind != ClassInfo::Token) {
1482 std::vector<StringRef> SuperClasses;
1483 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1484 ie = Infos.end(); it != ie; ++it) {
1485 ClassInfo &B = **it;
1487 if (&A != &B && A.isSubsetOf(B))
1488 SuperClasses.push_back(B.Name);
1491 if (SuperClasses.empty())
1494 OS << "\n case " << A.Name << ":\n";
1496 if (SuperClasses.size() == 1) {
1497 OS << " return B == " << SuperClasses.back() << ";\n";
1501 OS << " switch (B) {\n";
1502 OS << " default: return false;\n";
1503 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1504 OS << " case " << SuperClasses[i] << ": return true;\n";
1514 /// EmitMatchTokenString - Emit the function to match a token string to the
1515 /// appropriate match class value.
1516 static void EmitMatchTokenString(CodeGenTarget &Target,
1517 std::vector<ClassInfo*> &Infos,
1519 // Construct the match list.
1520 std::vector<StringMatcher::StringPair> Matches;
1521 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1522 ie = Infos.end(); it != ie; ++it) {
1523 ClassInfo &CI = **it;
1525 if (CI.Kind == ClassInfo::Token)
1526 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1527 "return " + CI.Name + ";"));
1530 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1532 StringMatcher("Name", Matches, OS).Emit();
1534 OS << " return InvalidMatchClass;\n";
1538 /// EmitMatchRegisterName - Emit the function to match a string to the target
1539 /// specific register enum.
1540 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1542 // Construct the match list.
1543 std::vector<StringMatcher::StringPair> Matches;
1544 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
1545 const CodeGenRegister &Reg = Target.getRegisters()[i];
1546 if (Reg.TheDef->getValueAsString("AsmName").empty())
1549 Matches.push_back(StringMatcher::StringPair(
1550 Reg.TheDef->getValueAsString("AsmName"),
1551 "return " + utostr(i + 1) + ";"));
1554 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1556 StringMatcher("Name", Matches, OS).Emit();
1558 OS << " return 0;\n";
1562 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1564 static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1566 OS << "// Flags for subtarget features that participate in "
1567 << "instruction matching.\n";
1568 OS << "enum SubtargetFeatureFlag {\n";
1569 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1570 it = Info.SubtargetFeatures.begin(),
1571 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1572 SubtargetFeatureInfo &SFI = *it->second;
1573 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1575 OS << " Feature_None = 0\n";
1579 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1580 /// available features given a subtarget.
1581 static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
1583 std::string ClassName =
1584 Info.AsmParser->getValueAsString("AsmParserClassName");
1586 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1587 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1588 << "Subtarget *Subtarget) const {\n";
1589 OS << " unsigned Features = 0;\n";
1590 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1591 it = Info.SubtargetFeatures.begin(),
1592 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1593 SubtargetFeatureInfo &SFI = *it->second;
1594 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1596 OS << " Features |= " << SFI.getEnumName() << ";\n";
1598 OS << " return Features;\n";
1602 static std::string GetAliasRequiredFeatures(Record *R,
1603 const AsmMatcherInfo &Info) {
1604 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
1606 unsigned NumFeatures = 0;
1607 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
1608 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
1611 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
1612 "' is not marked as an AssemblerPredicate!");
1617 Result += F->getEnumName();
1621 if (NumFeatures > 1)
1622 Result = '(' + Result + ')';
1626 /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
1627 /// emit a function for them and return true, otherwise return false.
1628 static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
1629 std::vector<Record*> Aliases =
1630 Records.getAllDerivedDefinitions("MnemonicAlias");
1631 if (Aliases.empty()) return false;
1633 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
1634 "unsigned Features) {\n";
1636 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
1637 // iteration order of the map is stable.
1638 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
1640 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
1641 Record *R = Aliases[i];
1642 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
1645 // Process each alias a "from" mnemonic at a time, building the code executed
1646 // by the string remapper.
1647 std::vector<StringMatcher::StringPair> Cases;
1648 for (std::map<std::string, std::vector<Record*> >::iterator
1649 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
1651 const std::vector<Record*> &ToVec = I->second;
1653 // Loop through each alias and emit code that handles each case. If there
1654 // are two instructions without predicates, emit an error. If there is one,
1656 std::string MatchCode;
1657 int AliasWithNoPredicate = -1;
1659 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
1660 Record *R = ToVec[i];
1661 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
1663 // If this unconditionally matches, remember it for later and diagnose
1665 if (FeatureMask.empty()) {
1666 if (AliasWithNoPredicate != -1) {
1667 // We can't have two aliases from the same mnemonic with no predicate.
1668 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
1669 "two MnemonicAliases with the same 'from' mnemonic!");
1670 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
1673 AliasWithNoPredicate = i;
1677 if (!MatchCode.empty())
1678 MatchCode += "else ";
1679 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
1680 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
1683 if (AliasWithNoPredicate != -1) {
1684 Record *R = ToVec[AliasWithNoPredicate];
1685 if (!MatchCode.empty())
1686 MatchCode += "else\n ";
1687 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
1690 MatchCode += "return;";
1692 Cases.push_back(std::make_pair(I->first, MatchCode));
1696 StringMatcher("Mnemonic", Cases, OS).Emit();
1702 void AsmMatcherEmitter::run(raw_ostream &OS) {
1703 CodeGenTarget Target;
1704 Record *AsmParser = Target.getAsmParser();
1705 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
1707 // Compute the information on the instructions to match.
1708 AsmMatcherInfo Info(AsmParser, Target);
1711 // Sort the instruction table using the partial order on classes. We use
1712 // stable_sort to ensure that ambiguous instructions are still
1713 // deterministically ordered.
1714 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
1715 less_ptr<MatchableInfo>());
1717 DEBUG_WITH_TYPE("instruction_info", {
1718 for (std::vector<MatchableInfo*>::iterator
1719 it = Info.Matchables.begin(), ie = Info.Matchables.end();
1724 // Check for ambiguous matchables.
1725 DEBUG_WITH_TYPE("ambiguous_instrs", {
1726 unsigned NumAmbiguous = 0;
1727 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
1728 for (unsigned j = i + 1; j != e; ++j) {
1729 MatchableInfo &A = *Info.Matchables[i];
1730 MatchableInfo &B = *Info.Matchables[j];
1732 if (A.CouldMatchAmiguouslyWith(B)) {
1733 errs() << "warning: ambiguous matchables:\n";
1735 errs() << "\nis incomparable with:\n";
1743 errs() << "warning: " << NumAmbiguous
1744 << " ambiguous matchables!\n";
1747 // Write the output.
1749 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1751 // Information for the class declaration.
1752 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
1753 OS << "#undef GET_ASSEMBLER_HEADER\n";
1754 OS << " // This should be included into the middle of the declaration of \n";
1755 OS << " // your subclasses implementation of TargetAsmParser.\n";
1756 OS << " unsigned ComputeAvailableFeatures(const " <<
1757 Target.getName() << "Subtarget *Subtarget) const;\n";
1758 OS << " enum MatchResultTy {\n";
1759 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n";
1760 OS << " Match_MissingFeature\n";
1762 OS << " MatchResultTy MatchInstructionImpl(const "
1763 << "SmallVectorImpl<MCParsedAsmOperand*>"
1764 << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n";
1765 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
1770 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
1771 OS << "#undef GET_REGISTER_MATCHER\n\n";
1773 // Emit the subtarget feature enumeration.
1774 EmitSubtargetFeatureFlagEnumeration(Info, OS);
1776 // Emit the function to match a register name to number.
1777 EmitMatchRegisterName(Target, AsmParser, OS);
1779 OS << "#endif // GET_REGISTER_MATCHER\n\n";
1782 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
1783 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
1785 // Generate the function that remaps for mnemonic aliases.
1786 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
1788 // Generate the unified function to convert operands into an MCInst.
1789 EmitConvertToMCInst(Target, Info.Matchables, OS);
1791 // Emit the enumeration for classes which participate in matching.
1792 EmitMatchClassEnumeration(Target, Info.Classes, OS);
1794 // Emit the routine to match token strings to their match class.
1795 EmitMatchTokenString(Target, Info.Classes, OS);
1797 // Emit the routine to classify an operand.
1798 EmitClassifyOperand(Info, OS);
1800 // Emit the subclass predicate routine.
1801 EmitIsSubclass(Target, Info.Classes, OS);
1803 // Emit the available features compute function.
1804 EmitComputeAvailableFeatures(Info, OS);
1807 size_t MaxNumOperands = 0;
1808 for (std::vector<MatchableInfo*>::const_iterator it =
1809 Info.Matchables.begin(), ie = Info.Matchables.end();
1811 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
1814 // Emit the static match table; unused classes get initalized to 0 which is
1815 // guaranteed to be InvalidMatchClass.
1817 // FIXME: We can reduce the size of this table very easily. First, we change
1818 // it so that store the kinds in separate bit-fields for each index, which
1819 // only needs to be the max width used for classes at that index (we also need
1820 // to reject based on this during classification). If we then make sure to
1821 // order the match kinds appropriately (putting mnemonics last), then we
1822 // should only end up using a few bits for each class, especially the ones
1823 // following the mnemonic.
1824 OS << "namespace {\n";
1825 OS << " struct MatchEntry {\n";
1826 OS << " unsigned Opcode;\n";
1827 OS << " const char *Mnemonic;\n";
1828 OS << " ConversionKind ConvertFn;\n";
1829 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1830 OS << " unsigned RequiredFeatures;\n";
1833 OS << "// Predicate for searching for an opcode.\n";
1834 OS << " struct LessOpcode {\n";
1835 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
1836 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
1838 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
1839 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
1841 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
1842 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
1846 OS << "} // end anonymous namespace.\n\n";
1848 OS << "static const MatchEntry MatchTable["
1849 << Info.Matchables.size() << "] = {\n";
1851 for (std::vector<MatchableInfo*>::const_iterator it =
1852 Info.Matchables.begin(), ie = Info.Matchables.end();
1854 MatchableInfo &II = **it;
1857 OS << " { " << Target.getName() << "::"
1858 << II.getResultInst()->TheDef->getName() << ", \"" << II.Mnemonic << "\""
1859 << ", " << II.ConversionFnKind << ", { ";
1860 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1861 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1864 OS << Op.Class->Name;
1868 // Write the required features mask.
1869 if (!II.RequiredFeatures.empty()) {
1870 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
1872 OS << II.RequiredFeatures[i]->getEnumName();
1882 // Finally, build the match function.
1883 OS << Target.getName() << ClassName << "::MatchResultTy "
1884 << Target.getName() << ClassName << "::\n"
1885 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
1887 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
1889 // Emit code to get the available features.
1890 OS << " // Get the current feature set.\n";
1891 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
1893 OS << " // Get the instruction mnemonic, which is the first token.\n";
1894 OS << " StringRef Mnemonic = ((" << Target.getName()
1895 << "Operand*)Operands[0])->getToken();\n\n";
1897 if (HasMnemonicAliases) {
1898 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
1899 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
1902 // Emit code to compute the class list for this operand vector.
1903 OS << " // Eliminate obvious mismatches.\n";
1904 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
1905 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
1906 OS << " return Match_InvalidOperand;\n";
1909 OS << " // Compute the class list for this operand vector.\n";
1910 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1911 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n";
1912 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n";
1914 OS << " // Check for invalid operands before matching.\n";
1915 OS << " if (Classes[i-1] == InvalidMatchClass) {\n";
1916 OS << " ErrorInfo = i;\n";
1917 OS << " return Match_InvalidOperand;\n";
1921 OS << " // Mark unused classes.\n";
1922 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; "
1923 << "i != e; ++i)\n";
1924 OS << " Classes[i] = InvalidMatchClass;\n\n";
1926 OS << " // Some state to try to produce better error messages.\n";
1927 OS << " bool HadMatchOtherThanFeatures = false;\n\n";
1928 OS << " // Set ErrorInfo to the operand that mismatches if it is \n";
1929 OS << " // wrong for all instances of the instruction.\n";
1930 OS << " ErrorInfo = ~0U;\n";
1932 // Emit code to search the table.
1933 OS << " // Search the table.\n";
1934 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
1935 OS << " std::equal_range(MatchTable, MatchTable+"
1936 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
1938 OS << " // Return a more specific error code if no mnemonics match.\n";
1939 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
1940 OS << " return Match_MnemonicFail;\n\n";
1942 OS << " for (const MatchEntry *it = MnemonicRange.first, "
1943 << "*ie = MnemonicRange.second;\n";
1944 OS << " it != ie; ++it) {\n";
1946 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
1947 OS << " assert(Mnemonic == it->Mnemonic);\n";
1949 // Emit check that the subclasses match.
1950 OS << " bool OperandsValid = true;\n";
1951 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
1952 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n";
1953 OS << " continue;\n";
1954 OS << " // If this operand is broken for all of the instances of this\n";
1955 OS << " // mnemonic, keep track of it so we can report loc info.\n";
1956 OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n";
1957 OS << " ErrorInfo = i+1;\n";
1959 OS << " ErrorInfo = ~0U;";
1960 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
1961 OS << " OperandsValid = false;\n";
1965 OS << " if (!OperandsValid) continue;\n";
1967 // Emit check that the required features are available.
1968 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
1969 << "!= it->RequiredFeatures) {\n";
1970 OS << " HadMatchOtherThanFeatures = true;\n";
1971 OS << " continue;\n";
1975 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
1977 // Call the post-processing function, if used.
1978 std::string InsnCleanupFn =
1979 AsmParser->getValueAsString("AsmParserInstCleanup");
1980 if (!InsnCleanupFn.empty())
1981 OS << " " << InsnCleanupFn << "(Inst);\n";
1983 OS << " return Match_Success;\n";
1986 OS << " // Okay, we had no match. Try to return a useful error code.\n";
1987 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
1988 OS << " return Match_InvalidOperand;\n";
1991 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";