1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures.
13 // The input to the target specific matcher is a list of literal tokens and
14 // operands. The target specific parser should generally eliminate any syntax
15 // which is not relevant for matching; for example, comma tokens should have
16 // already been consumed and eliminated by the parser. Most instructions will
17 // end up with a single literal token (the instruction name) and some number of
20 // Some example inputs, for X86:
21 // 'addl' (immediate ...) (register ...)
22 // 'add' (immediate ...) (memory ...)
25 // The assembly matcher is responsible for converting this input into a precise
26 // machine instruction (i.e., an instruction with a well defined encoding). This
27 // mapping has several properties which complicate matching:
29 // - It may be ambiguous; many architectures can legally encode particular
30 // variants of an instruction in different ways (for example, using a smaller
31 // encoding for small immediates). Such ambiguities should never be
32 // arbitrarily resolved by the assembler, the assembler is always responsible
33 // for choosing the "best" available instruction.
35 // - It may depend on the subtarget or the assembler context. Instructions
36 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
37 // an SSE instruction in a file being assembled for i486) should be accepted
38 // and rejected by the assembler front end. However, if the proper encoding
39 // for an instruction is dependent on the assembler context then the matcher
40 // is responsible for selecting the correct machine instruction for the
43 // The core matching algorithm attempts to exploit the regularity in most
44 // instruction sets to quickly determine the set of possibly matching
45 // instructions, and the simplify the generated code. Additionally, this helps
46 // to ensure that the ambiguities are intentionally resolved by the user.
48 // The matching is divided into two distinct phases:
50 // 1. Classification: Each operand is mapped to the unique set which (a)
51 // contains it, and (b) is the largest such subset for which a single
52 // instruction could match all members.
54 // For register classes, we can generate these subgroups automatically. For
55 // arbitrary operands, we expect the user to define the classes and their
56 // relations to one another (for example, 8-bit signed immediates as a
57 // subset of 32-bit immediates).
59 // By partitioning the operands in this way, we guarantee that for any
60 // tuple of classes, any single instruction must match either all or none
61 // of the sets of operands which could classify to that tuple.
63 // In addition, the subset relation amongst classes induces a partial order
64 // on such tuples, which we use to resolve ambiguities.
66 // 2. The input can now be treated as a tuple of classes (static tokens are
67 // simple singleton sets). Each such tuple should generally map to a single
68 // instruction (we currently ignore cases where this isn't true, whee!!!),
69 // which we can emit a simple matcher for.
71 //===----------------------------------------------------------------------===//
73 #include "AsmMatcherEmitter.h"
74 #include "CodeGenTarget.h"
76 #include "StringMatcher.h"
77 #include "llvm/ADT/OwningPtr.h"
78 #include "llvm/ADT/PointerUnion.h"
79 #include "llvm/ADT/SmallPtrSet.h"
80 #include "llvm/ADT/SmallVector.h"
81 #include "llvm/ADT/STLExtras.h"
82 #include "llvm/ADT/StringExtras.h"
83 #include "llvm/Support/CommandLine.h"
84 #include "llvm/Support/Debug.h"
89 static cl::opt<std::string>
90 MatchPrefix("match-prefix", cl::init(""),
91 cl::desc("Only match instructions with the given prefix"));
96 struct SubtargetFeatureInfo;
98 /// ClassInfo - Helper class for storing the information about a particular
99 /// class of operands which can be matched.
102 /// Invalid kind, for use as a sentinel value.
105 /// The class for a particular token.
108 /// The (first) register class, subsequent register classes are
109 /// RegisterClass0+1, and so on.
112 /// The (first) user defined class, subsequent user defined classes are
113 /// UserClass0+1, and so on.
117 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
118 /// N) for the Nth user defined class.
121 /// SuperClasses - The super classes of this class. Note that for simplicities
122 /// sake user operands only record their immediate super class, while register
123 /// operands include all superclasses.
124 std::vector<ClassInfo*> SuperClasses;
126 /// Name - The full class name, suitable for use in an enum.
129 /// ClassName - The unadorned generic name for this class (e.g., Token).
130 std::string ClassName;
132 /// ValueName - The name of the value this class represents; for a token this
133 /// is the literal token string, for an operand it is the TableGen class (or
134 /// empty if this is a derived class).
135 std::string ValueName;
137 /// PredicateMethod - The name of the operand method to test whether the
138 /// operand matches this class; this is not valid for Token or register kinds.
139 std::string PredicateMethod;
141 /// RenderMethod - The name of the operand method to add this operand to an
142 /// MCInst; this is not valid for Token or register kinds.
143 std::string RenderMethod;
145 /// For register classes, the records for all the registers in this class.
146 std::set<Record*> Registers;
149 /// isRegisterClass() - Check if this is a register class.
150 bool isRegisterClass() const {
151 return Kind >= RegisterClass0 && Kind < UserClass0;
154 /// isUserClass() - Check if this is a user defined class.
155 bool isUserClass() const {
156 return Kind >= UserClass0;
159 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
160 /// are related if they are in the same class hierarchy.
161 bool isRelatedTo(const ClassInfo &RHS) const {
162 // Tokens are only related to tokens.
163 if (Kind == Token || RHS.Kind == Token)
164 return Kind == Token && RHS.Kind == Token;
166 // Registers classes are only related to registers classes, and only if
167 // their intersection is non-empty.
168 if (isRegisterClass() || RHS.isRegisterClass()) {
169 if (!isRegisterClass() || !RHS.isRegisterClass())
172 std::set<Record*> Tmp;
173 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
174 std::set_intersection(Registers.begin(), Registers.end(),
175 RHS.Registers.begin(), RHS.Registers.end(),
181 // Otherwise we have two users operands; they are related if they are in the
182 // same class hierarchy.
184 // FIXME: This is an oversimplification, they should only be related if they
185 // intersect, however we don't have that information.
186 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
187 const ClassInfo *Root = this;
188 while (!Root->SuperClasses.empty())
189 Root = Root->SuperClasses.front();
191 const ClassInfo *RHSRoot = &RHS;
192 while (!RHSRoot->SuperClasses.empty())
193 RHSRoot = RHSRoot->SuperClasses.front();
195 return Root == RHSRoot;
198 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
199 bool isSubsetOf(const ClassInfo &RHS) const {
200 // This is a subset of RHS if it is the same class...
204 // ... or if any of its super classes are a subset of RHS.
205 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
206 ie = SuperClasses.end(); it != ie; ++it)
207 if ((*it)->isSubsetOf(RHS))
213 /// operator< - Compare two classes.
214 bool operator<(const ClassInfo &RHS) const {
218 // Unrelated classes can be ordered by kind.
219 if (!isRelatedTo(RHS))
220 return Kind < RHS.Kind;
224 assert(0 && "Invalid kind!");
226 // Tokens are comparable by value.
228 // FIXME: Compare by enum value.
229 return ValueName < RHS.ValueName;
232 // This class preceeds the RHS if it is a proper subset of the RHS.
235 if (RHS.isSubsetOf(*this))
238 // Otherwise, order by name to ensure we have a total ordering.
239 return ValueName < RHS.ValueName;
244 /// MatchableInfo - Helper class for storing the necessary information for an
245 /// instruction or alias which is capable of being matched.
246 struct MatchableInfo {
248 /// Token - This is the token that the operand came from.
251 /// The unique class instance this operand should match.
254 /// The operand name this is, if anything.
257 explicit AsmOperand(StringRef T) : Token(T), Class(0) {}
260 /// ResOperand - This represents a single operand in the result instruction
261 /// generated by the match. In cases (like addressing modes) where a single
262 /// assembler operand expands to multiple MCOperands, this represents the
263 /// single assembler operand, not the MCOperand.
266 /// RenderAsmOperand - This represents an operand result that is
267 /// generated by calling the render method on the assembly operand. The
268 /// corresponding AsmOperand is specified by AsmOperandNum.
271 /// TiedOperand - This represents a result operand that is a duplicate of
272 /// a previous result operand.
275 /// ImmOperand - This represents an immediate value that is dumped into
279 /// RegOperand - This represents a fixed register that is dumped in.
284 /// This is the operand # in the AsmOperands list that this should be
286 unsigned AsmOperandNum;
288 /// TiedOperandNum - This is the (earlier) result operand that should be
290 unsigned TiedOperandNum;
292 /// ImmVal - This is the immediate value added to the instruction.
295 /// Register - This is the register record.
299 /// OpInfo - This is the information about the instruction operand that is
301 const CGIOperandList::OperandInfo *OpInfo;
303 static ResOperand getRenderedOp(unsigned AsmOpNum,
304 const CGIOperandList::OperandInfo *Op) {
306 X.Kind = RenderAsmOperand;
307 X.AsmOperandNum = AsmOpNum;
312 static ResOperand getTiedOp(unsigned TiedOperandNum,
313 const CGIOperandList::OperandInfo *Op) {
315 X.Kind = TiedOperand;
316 X.TiedOperandNum = TiedOperandNum;
321 static ResOperand getImmOp(int64_t Val,
322 const CGIOperandList::OperandInfo *Op) {
330 static ResOperand getRegOp(Record *Reg,
331 const CGIOperandList::OperandInfo *Op) {
341 /// TheDef - This is the definition of the instruction or InstAlias that this
342 /// matchable came from.
343 Record *const TheDef;
345 /// DefRec - This is the definition that it came from.
346 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
348 const CodeGenInstruction *getResultInst() const {
349 if (DefRec.is<const CodeGenInstruction*>())
350 return DefRec.get<const CodeGenInstruction*>();
351 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
354 /// ResOperands - This is the operand list that should be built for the result
356 std::vector<ResOperand> ResOperands;
358 /// AsmString - The assembly string for this instruction (with variants
359 /// removed), e.g. "movsx $src, $dst".
360 std::string AsmString;
362 /// Mnemonic - This is the first token of the matched instruction, its
366 /// AsmOperands - The textual operands that this instruction matches,
367 /// annotated with a class and where in the OperandList they were defined.
368 /// This directly corresponds to the tokenized AsmString after the mnemonic is
370 SmallVector<AsmOperand, 4> AsmOperands;
372 /// Predicates - The required subtarget features to match this instruction.
373 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
375 /// ConversionFnKind - The enum value which is passed to the generated
376 /// ConvertToMCInst to convert parsed operands into an MCInst for this
378 std::string ConversionFnKind;
380 MatchableInfo(const CodeGenInstruction &CGI)
381 : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) {
384 MatchableInfo(const CodeGenInstAlias *Alias)
385 : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) {
388 void Initialize(const AsmMatcherInfo &Info,
389 SmallPtrSet<Record*, 16> &SingletonRegisters);
391 /// Validate - Return true if this matchable is a valid thing to match against
392 /// and perform a bunch of validity checking.
393 bool Validate(StringRef CommentDelimiter, bool Hack) const;
395 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
396 /// register, return the Record for it, otherwise return null.
397 Record *getSingletonRegisterForAsmOperand(unsigned i,
398 const AsmMatcherInfo &Info) const;
400 int FindAsmOperandNamed(StringRef N) const {
401 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
402 if (N == AsmOperands[i].SrcOpName)
407 void BuildInstructionResultOperands();
408 void BuildAliasResultOperands();
410 /// operator< - Compare two matchables.
411 bool operator<(const MatchableInfo &RHS) const {
412 // The primary comparator is the instruction mnemonic.
413 if (Mnemonic != RHS.Mnemonic)
414 return Mnemonic < RHS.Mnemonic;
416 if (AsmOperands.size() != RHS.AsmOperands.size())
417 return AsmOperands.size() < RHS.AsmOperands.size();
419 // Compare lexicographically by operand. The matcher validates that other
420 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith().
421 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
422 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
424 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
431 /// CouldMatchAmiguouslyWith - Check whether this matchable could
432 /// ambiguously match the same set of operands as \arg RHS (without being a
433 /// strictly superior match).
434 bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) {
435 // The primary comparator is the instruction mnemonic.
436 if (Mnemonic != RHS.Mnemonic)
439 // The number of operands is unambiguous.
440 if (AsmOperands.size() != RHS.AsmOperands.size())
443 // Otherwise, make sure the ordering of the two instructions is unambiguous
444 // by checking that either (a) a token or operand kind discriminates them,
445 // or (b) the ordering among equivalent kinds is consistent.
447 // Tokens and operand kinds are unambiguous (assuming a correct target
449 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
450 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
451 AsmOperands[i].Class->Kind == ClassInfo::Token)
452 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
453 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
456 // Otherwise, this operand could commute if all operands are equivalent, or
457 // there is a pair of operands that compare less than and a pair that
458 // compare greater than.
459 bool HasLT = false, HasGT = false;
460 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
461 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
463 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
467 return !(HasLT ^ HasGT);
473 void TokenizeAsmString(const AsmMatcherInfo &Info);
476 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
477 /// feature which participates in instruction matching.
478 struct SubtargetFeatureInfo {
479 /// \brief The predicate record for this feature.
482 /// \brief An unique index assigned to represent this feature.
485 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
487 /// \brief The name of the enumerated constant identifying this feature.
488 std::string getEnumName() const {
489 return "Feature_" + TheDef->getName();
493 class AsmMatcherInfo {
495 /// The tablegen AsmParser record.
498 /// Target - The target information.
499 CodeGenTarget &Target;
501 /// The AsmParser "RegisterPrefix" value.
502 std::string RegisterPrefix;
504 /// The classes which are needed for matching.
505 std::vector<ClassInfo*> Classes;
507 /// The information on the matchables to match.
508 std::vector<MatchableInfo*> Matchables;
510 /// Map of Register records to their class information.
511 std::map<Record*, ClassInfo*> RegisterClasses;
513 /// Map of Predicate records to their subtarget information.
514 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
517 /// Map of token to class information which has already been constructed.
518 std::map<std::string, ClassInfo*> TokenClasses;
520 /// Map of RegisterClass records to their class information.
521 std::map<Record*, ClassInfo*> RegisterClassClasses;
523 /// Map of AsmOperandClass records to their class information.
524 std::map<Record*, ClassInfo*> AsmOperandClasses;
527 /// getTokenClass - Lookup or create the class for the given token.
528 ClassInfo *getTokenClass(StringRef Token);
530 /// getOperandClass - Lookup or create the class for the given operand.
531 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI);
533 /// BuildRegisterClasses - Build the ClassInfo* instances for register
535 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
537 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
539 void BuildOperandClasses();
541 void BuildInstructionOperandReference(MatchableInfo *II,
543 MatchableInfo::AsmOperand &Op);
544 void BuildAliasOperandReference(MatchableInfo *II,
546 MatchableInfo::AsmOperand &Op);
549 AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target);
551 /// BuildInfo - Construct the various tables used during matching.
554 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
556 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
557 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
558 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
559 SubtargetFeatures.find(Def);
560 return I == SubtargetFeatures.end() ? 0 : I->second;
566 void MatchableInfo::dump() {
567 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
569 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
570 AsmOperand &Op = AsmOperands[i];
571 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
572 errs() << '\"' << Op.Token << "\"\n";
576 void MatchableInfo::Initialize(const AsmMatcherInfo &Info,
577 SmallPtrSet<Record*, 16> &SingletonRegisters) {
578 // TODO: Eventually support asmparser for Variant != 0.
579 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0);
581 TokenizeAsmString(Info);
583 // Compute the require features.
584 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
585 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
586 if (SubtargetFeatureInfo *Feature =
587 Info.getSubtargetFeature(Predicates[i]))
588 RequiredFeatures.push_back(Feature);
590 // Collect singleton registers, if used.
591 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
592 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
593 SingletonRegisters.insert(Reg);
597 /// TokenizeAsmString - Tokenize a simplified assembly string.
598 void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) {
599 StringRef String = AsmString;
602 for (unsigned i = 0, e = String.size(); i != e; ++i) {
612 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
615 if (!isspace(String[i]) && String[i] != ',')
616 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
622 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
626 assert(i != String.size() && "Invalid quoted character");
627 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
633 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
637 // If this isn't "${", treat like a normal token.
638 if (i + 1 == String.size() || String[i + 1] != '{') {
643 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
644 assert(End != String.end() && "Missing brace in operand reference!");
645 size_t EndPos = End - String.begin();
646 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
654 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
663 if (InTok && Prev != String.size())
664 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
666 // The first token of the instruction is the mnemonic, which must be a
667 // simple string, not a $foo variable or a singleton register.
668 assert(!AsmOperands.empty() && "Instruction has no tokens?");
669 Mnemonic = AsmOperands[0].Token;
670 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info))
671 throw TGError(TheDef->getLoc(),
672 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
674 // Remove the first operand, it is tracked in the mnemonic field.
675 AsmOperands.erase(AsmOperands.begin());
680 bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const {
681 // Reject matchables with no .s string.
682 if (AsmString.empty())
683 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
685 // Reject any matchables with a newline in them, they should be marked
686 // isCodeGenOnly if they are pseudo instructions.
687 if (AsmString.find('\n') != std::string::npos)
688 throw TGError(TheDef->getLoc(),
689 "multiline instruction is not valid for the asmparser, "
690 "mark it isCodeGenOnly");
692 // Remove comments from the asm string. We know that the asmstring only
694 if (!CommentDelimiter.empty() &&
695 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
696 throw TGError(TheDef->getLoc(),
697 "asmstring for instruction has comment character in it, "
698 "mark it isCodeGenOnly");
700 // Reject matchables with operand modifiers, these aren't something we can
701 /// handle, the target should be refactored to use operands instead of
704 // Also, check for instructions which reference the operand multiple times;
705 // this implies a constraint we would not honor.
706 std::set<std::string> OperandNames;
707 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
708 StringRef Tok = AsmOperands[i].Token;
709 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
710 throw TGError(TheDef->getLoc(),
711 "matchable with operand modifier '" + Tok.str() +
712 "' not supported by asm matcher. Mark isCodeGenOnly!");
714 // Verify that any operand is only mentioned once.
715 // We reject aliases and ignore instructions for now.
716 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
718 throw TGError(TheDef->getLoc(),
719 "ERROR: matchable with tied operand '" + Tok.str() +
720 "' can never be matched!");
721 // FIXME: Should reject these. The ARM backend hits this with $lane in a
722 // bunch of instructions. It is unclear what the right answer is.
724 errs() << "warning: '" << TheDef->getName() << "': "
725 << "ignoring instruction with tied operand '"
726 << Tok.str() << "'\n";
736 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
737 /// register, return the register name, otherwise return a null StringRef.
738 Record *MatchableInfo::
739 getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{
740 StringRef Tok = AsmOperands[i].Token;
741 if (!Tok.startswith(Info.RegisterPrefix))
744 StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
745 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
748 // If there is no register prefix (i.e. "%" in "%eax"), then this may
749 // be some random non-register token, just ignore it.
750 if (Info.RegisterPrefix.empty())
753 // Otherwise, we have something invalid prefixed with the register prefix,
755 std::string Err = "unable to find register for '" + RegName.str() +
756 "' (which matches register prefix)";
757 throw TGError(TheDef->getLoc(), Err);
761 static std::string getEnumNameForToken(StringRef Str) {
764 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
766 case '*': Res += "_STAR_"; break;
767 case '%': Res += "_PCT_"; break;
768 case ':': Res += "_COLON_"; break;
773 Res += "_" + utostr((unsigned) *it) + "_";
780 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
781 ClassInfo *&Entry = TokenClasses[Token];
784 Entry = new ClassInfo();
785 Entry->Kind = ClassInfo::Token;
786 Entry->ClassName = "Token";
787 Entry->Name = "MCK_" + getEnumNameForToken(Token);
788 Entry->ValueName = Token;
789 Entry->PredicateMethod = "<invalid>";
790 Entry->RenderMethod = "<invalid>";
791 Classes.push_back(Entry);
798 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI) {
799 if (OI.Rec->isSubClassOf("RegisterClass")) {
800 if (ClassInfo *CI = RegisterClassClasses[OI.Rec])
802 throw TGError(OI.Rec->getLoc(), "register class has no class info!");
805 assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!");
806 Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
807 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
810 throw TGError(OI.Rec->getLoc(), "operand has no match class!");
813 void AsmMatcherInfo::
814 BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
815 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
816 const std::vector<CodeGenRegisterClass> &RegClassList =
817 Target.getRegisterClasses();
819 // The register sets used for matching.
820 std::set< std::set<Record*> > RegisterSets;
822 // Gather the defined sets.
823 for (std::vector<CodeGenRegisterClass>::const_iterator it =
824 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
825 RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
826 it->Elements.end()));
828 // Add any required singleton sets.
829 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
830 ie = SingletonRegisters.end(); it != ie; ++it) {
832 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
835 // Introduce derived sets where necessary (when a register does not determine
836 // a unique register set class), and build the mapping of registers to the set
837 // they should classify to.
838 std::map<Record*, std::set<Record*> > RegisterMap;
839 for (std::vector<CodeGenRegister>::const_iterator it = Registers.begin(),
840 ie = Registers.end(); it != ie; ++it) {
841 const CodeGenRegister &CGR = *it;
842 // Compute the intersection of all sets containing this register.
843 std::set<Record*> ContainingSet;
845 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
846 ie = RegisterSets.end(); it != ie; ++it) {
847 if (!it->count(CGR.TheDef))
850 if (ContainingSet.empty()) {
855 std::set<Record*> Tmp;
856 std::swap(Tmp, ContainingSet);
857 std::insert_iterator< std::set<Record*> > II(ContainingSet,
858 ContainingSet.begin());
859 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
862 if (!ContainingSet.empty()) {
863 RegisterSets.insert(ContainingSet);
864 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
868 // Construct the register classes.
869 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
871 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
872 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
873 ClassInfo *CI = new ClassInfo();
874 CI->Kind = ClassInfo::RegisterClass0 + Index;
875 CI->ClassName = "Reg" + utostr(Index);
876 CI->Name = "MCK_Reg" + utostr(Index);
878 CI->PredicateMethod = ""; // unused
879 CI->RenderMethod = "addRegOperands";
881 Classes.push_back(CI);
882 RegisterSetClasses.insert(std::make_pair(*it, CI));
885 // Find the superclasses; we could compute only the subgroup lattice edges,
886 // but there isn't really a point.
887 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
888 ie = RegisterSets.end(); it != ie; ++it) {
889 ClassInfo *CI = RegisterSetClasses[*it];
890 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
891 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
893 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
894 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
897 // Name the register classes which correspond to a user defined RegisterClass.
898 for (std::vector<CodeGenRegisterClass>::const_iterator
899 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
900 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
901 it->Elements.end())];
902 if (CI->ValueName.empty()) {
903 CI->ClassName = it->getName();
904 CI->Name = "MCK_" + it->getName();
905 CI->ValueName = it->getName();
907 CI->ValueName = CI->ValueName + "," + it->getName();
909 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
912 // Populate the map for individual registers.
913 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
914 ie = RegisterMap.end(); it != ie; ++it)
915 RegisterClasses[it->first] = RegisterSetClasses[it->second];
917 // Name the register classes which correspond to singleton registers.
918 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
919 ie = SingletonRegisters.end(); it != ie; ++it) {
921 ClassInfo *CI = RegisterClasses[Rec];
922 assert(CI && "Missing singleton register class info!");
924 if (CI->ValueName.empty()) {
925 CI->ClassName = Rec->getName();
926 CI->Name = "MCK_" + Rec->getName();
927 CI->ValueName = Rec->getName();
929 CI->ValueName = CI->ValueName + "," + Rec->getName();
933 void AsmMatcherInfo::BuildOperandClasses() {
934 std::vector<Record*> AsmOperands =
935 Records.getAllDerivedDefinitions("AsmOperandClass");
937 // Pre-populate AsmOperandClasses map.
938 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
939 ie = AsmOperands.end(); it != ie; ++it)
940 AsmOperandClasses[*it] = new ClassInfo();
943 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
944 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
945 ClassInfo *CI = AsmOperandClasses[*it];
946 CI->Kind = ClassInfo::UserClass0 + Index;
948 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
949 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
950 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
952 PrintError((*it)->getLoc(), "Invalid super class reference!");
956 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
958 PrintError((*it)->getLoc(), "Invalid super class reference!");
960 CI->SuperClasses.push_back(SC);
962 CI->ClassName = (*it)->getValueAsString("Name");
963 CI->Name = "MCK_" + CI->ClassName;
964 CI->ValueName = (*it)->getName();
966 // Get or construct the predicate method name.
967 Init *PMName = (*it)->getValueInit("PredicateMethod");
968 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
969 CI->PredicateMethod = SI->getValue();
971 assert(dynamic_cast<UnsetInit*>(PMName) &&
972 "Unexpected PredicateMethod field!");
973 CI->PredicateMethod = "is" + CI->ClassName;
976 // Get or construct the render method name.
977 Init *RMName = (*it)->getValueInit("RenderMethod");
978 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
979 CI->RenderMethod = SI->getValue();
981 assert(dynamic_cast<UnsetInit*>(RMName) &&
982 "Unexpected RenderMethod field!");
983 CI->RenderMethod = "add" + CI->ClassName + "Operands";
986 AsmOperandClasses[*it] = CI;
987 Classes.push_back(CI);
991 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target)
992 : AsmParser(asmParser), Target(target),
993 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
997 void AsmMatcherInfo::BuildInfo() {
998 // Build information about all of the AssemblerPredicates.
999 std::vector<Record*> AllPredicates =
1000 Records.getAllDerivedDefinitions("Predicate");
1001 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1002 Record *Pred = AllPredicates[i];
1003 // Ignore predicates that are not intended for the assembler.
1004 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1007 if (Pred->getName().empty())
1008 throw TGError(Pred->getLoc(), "Predicate has no name!");
1010 unsigned FeatureNo = SubtargetFeatures.size();
1011 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1012 assert(FeatureNo < 32 && "Too many subtarget features!");
1015 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
1017 // Parse the instructions; we need to do this first so that we can gather the
1018 // singleton register classes.
1019 SmallPtrSet<Record*, 16> SingletonRegisters;
1020 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1021 E = Target.inst_end(); I != E; ++I) {
1022 const CodeGenInstruction &CGI = **I;
1024 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1025 // filter the set of instructions we consider.
1026 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1029 // Ignore "codegen only" instructions.
1030 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1033 // Validate the operand list to ensure we can handle this instruction.
1034 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1035 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1037 // Validate tied operands.
1038 if (OI.getTiedRegister() != -1) {
1039 // If we have a tied operand that consists of multiple MCOperands, reject
1040 // it. We reject aliases and ignore instructions for now.
1041 if (OI.MINumOperands != 1) {
1042 // FIXME: Should reject these. The ARM backend hits this with $lane
1043 // in a bunch of instructions. It is unclear what the right answer is.
1045 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1046 << "ignoring instruction with multi-operand tied operand '"
1047 << OI.Name << "'\n";
1054 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1056 II->Initialize(*this, SingletonRegisters);
1058 // Ignore instructions which shouldn't be matched and diagnose invalid
1059 // instruction definitions with an error.
1060 if (!II->Validate(CommentDelimiter, true))
1063 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1065 // FIXME: This is a total hack.
1066 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1067 StringRef(II->TheDef->getName()).endswith("_Int"))
1070 Matchables.push_back(II.take());
1073 // Parse all of the InstAlias definitions and stick them in the list of
1075 std::vector<Record*> AllInstAliases =
1076 Records.getAllDerivedDefinitions("InstAlias");
1077 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1078 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1080 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1082 II->Initialize(*this, SingletonRegisters);
1084 // Validate the alias definitions.
1085 II->Validate(CommentDelimiter, false);
1087 Matchables.push_back(II.take());
1090 // Build info for the register classes.
1091 BuildRegisterClasses(SingletonRegisters);
1093 // Build info for the user defined assembly operand classes.
1094 BuildOperandClasses();
1096 // Build the information about matchables, now that we have fully formed
1098 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1099 ie = Matchables.end(); it != ie; ++it) {
1100 MatchableInfo *II = *it;
1102 // Parse the tokens after the mnemonic.
1103 for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) {
1104 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1105 StringRef Token = Op.Token;
1107 // Check for singleton registers.
1108 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) {
1109 Op.Class = RegisterClasses[RegRecord];
1110 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1111 "Unexpected class for singleton register");
1115 // Check for simple tokens.
1116 if (Token[0] != '$') {
1117 Op.Class = getTokenClass(Token);
1121 if (Token.size() > 1 && isdigit(Token[1])) {
1122 Op.Class = getTokenClass(Token);
1126 // Otherwise this is an operand reference.
1127 StringRef OperandName;
1128 if (Token[1] == '{')
1129 OperandName = Token.substr(2, Token.size() - 3);
1131 OperandName = Token.substr(1);
1133 if (II->DefRec.is<const CodeGenInstruction*>())
1134 BuildInstructionOperandReference(II, OperandName, Op);
1136 BuildAliasOperandReference(II, OperandName, Op);
1139 if (II->DefRec.is<const CodeGenInstruction*>())
1140 II->BuildInstructionResultOperands();
1142 II->BuildAliasResultOperands();
1145 // Reorder classes so that classes preceed super classes.
1146 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1149 /// BuildInstructionOperandReference - The specified operand is a reference to a
1150 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1151 void AsmMatcherInfo::
1152 BuildInstructionOperandReference(MatchableInfo *II,
1153 StringRef OperandName,
1154 MatchableInfo::AsmOperand &Op) {
1155 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1156 const CGIOperandList &Operands = CGI.Operands;
1158 // Map this token to an operand.
1160 if (!Operands.hasOperandNamed(OperandName, Idx))
1161 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1162 OperandName.str() + "'");
1164 // Set up the operand class.
1165 Op.Class = getOperandClass(Operands[Idx]);
1167 // If the named operand is tied, canonicalize it to the untied operand.
1168 // For example, something like:
1169 // (outs GPR:$dst), (ins GPR:$src)
1170 // with an asmstring of
1172 // we want to canonicalize to:
1174 // so that we know how to provide the $dst operand when filling in the result.
1175 int OITied = Operands[Idx].getTiedRegister();
1177 // The tied operand index is an MIOperand index, find the operand that
1179 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
1180 if (Operands[i].MIOperandNo == unsigned(OITied)) {
1181 OperandName = Operands[i].Name;
1187 Op.SrcOpName = OperandName;
1190 /// BuildAliasOperandReference - When parsing an operand reference out of the
1191 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1192 /// operand reference is by looking it up in the result pattern definition.
1193 void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II,
1194 StringRef OperandName,
1195 MatchableInfo::AsmOperand &Op) {
1196 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1198 // Set up the operand class.
1199 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1200 if (CGA.ResultOperands[i].isRecord() &&
1201 CGA.ResultOperands[i].getName() == OperandName) {
1202 // It's safe to go with the first one we find, because CodeGenInstAlias
1203 // validates that all operands with the same name have the same record.
1204 unsigned ResultIdx =CGA.getResultInstOperandIndexForResultOperandIndex(i);
1205 Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx]);
1206 Op.SrcOpName = OperandName;
1210 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1211 OperandName.str() + "'");
1214 void MatchableInfo::BuildInstructionResultOperands() {
1215 const CodeGenInstruction *ResultInst = getResultInst();
1217 // Loop over all operands of the result instruction, determining how to
1219 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1220 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1222 // If this is a tied operand, just copy from the previously handled operand.
1223 int TiedOp = OpInfo.getTiedRegister();
1225 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo));
1229 // Find out what operand from the asmparser that this MCInst operand comes
1231 int SrcOperand = FindAsmOperandNamed(OpInfo.Name);
1233 if (!OpInfo.Name.empty() && SrcOperand != -1) {
1234 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo));
1238 throw TGError(TheDef->getLoc(), "Instruction '" +
1239 TheDef->getName() + "' has operand '" + OpInfo.Name +
1240 "' that doesn't appear in asm string!");
1244 void MatchableInfo::BuildAliasResultOperands() {
1245 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1246 const CodeGenInstruction *ResultInst = getResultInst();
1248 // Loop over all operands of the result instruction, determining how to
1250 unsigned AliasOpNo = 0;
1251 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1252 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1254 // If this is a tied operand, just copy from the previously handled operand.
1255 int TiedOp = OpInfo.getTiedRegister();
1257 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo));
1261 // Find out what operand from the asmparser that this MCInst operand comes
1263 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1264 case CodeGenInstAlias::ResultOperand::K_Record: {
1265 StringRef Name = CGA.ResultOperands[AliasOpNo++].getName();
1266 int SrcOperand = FindAsmOperandNamed(Name);
1267 if (SrcOperand != -1) {
1268 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo));
1272 throw TGError(TheDef->getLoc(), "Instruction '" +
1273 TheDef->getName() + "' has operand '" + OpInfo.Name +
1274 "' that doesn't appear in asm string!");
1276 case CodeGenInstAlias::ResultOperand::K_Imm: {
1277 int64_t ImmVal = CGA.ResultOperands[AliasOpNo++].getImm();
1278 ResOperands.push_back(ResOperand::getImmOp(ImmVal, &OpInfo));
1282 case CodeGenInstAlias::ResultOperand::K_Reg: {
1283 Record *Reg = CGA.ResultOperands[AliasOpNo++].getRegister();
1284 ResOperands.push_back(ResOperand::getRegOp(Reg, &OpInfo));
1291 static void EmitConvertToMCInst(CodeGenTarget &Target,
1292 std::vector<MatchableInfo*> &Infos,
1294 // Write the convert function to a separate stream, so we can drop it after
1296 std::string ConvertFnBody;
1297 raw_string_ostream CvtOS(ConvertFnBody);
1299 // Function we have already generated.
1300 std::set<std::string> GeneratedFns;
1302 // Start the unified conversion function.
1303 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
1304 << "unsigned Opcode,\n"
1305 << " const SmallVectorImpl<MCParsedAsmOperand*"
1306 << "> &Operands) {\n";
1307 CvtOS << " Inst.setOpcode(Opcode);\n";
1308 CvtOS << " switch (Kind) {\n";
1309 CvtOS << " default:\n";
1311 // Start the enum, which we will generate inline.
1313 OS << "// Unified function for converting operands to MCInst instances.\n\n";
1314 OS << "enum ConversionKind {\n";
1316 // TargetOperandClass - This is the target's operand class, like X86Operand.
1317 std::string TargetOperandClass = Target.getName() + "Operand";
1319 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1320 ie = Infos.end(); it != ie; ++it) {
1321 MatchableInfo &II = **it;
1323 // Build the conversion function signature.
1324 std::string Signature = "Convert";
1325 std::string CaseBody;
1326 raw_string_ostream CaseOS(CaseBody);
1328 // Compute the convert enum and the case body.
1329 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1330 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1332 // Generate code to populate each result operand.
1333 switch (OpInfo.Kind) {
1334 case MatchableInfo::ResOperand::RenderAsmOperand: {
1335 // This comes from something we parsed.
1336 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1338 // Registers are always converted the same, don't duplicate the
1339 // conversion function based on them.
1341 if (Op.Class->isRegisterClass())
1344 Signature += Op.Class->ClassName;
1345 Signature += utostr(OpInfo.OpInfo->MINumOperands);
1346 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1348 CaseOS << " ((" << TargetOperandClass << "*)Operands["
1349 << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod
1350 << "(Inst, " << OpInfo.OpInfo->MINumOperands << ");\n";
1354 case MatchableInfo::ResOperand::TiedOperand: {
1355 // If this operand is tied to a previous one, just copy the MCInst
1356 // operand from the earlier one.We can only tie single MCOperand values.
1357 //assert(OpInfo.OpInfo->MINumOperands == 1 && "Not a singular MCOperand");
1358 unsigned TiedOp = OpInfo.TiedOperandNum;
1359 assert(i > TiedOp && "Tied operand preceeds its target!");
1360 CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
1361 Signature += "__Tie" + utostr(TiedOp);
1364 case MatchableInfo::ResOperand::ImmOperand: {
1365 int64_t Val = OpInfo.ImmVal;
1366 CaseOS << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n";
1367 Signature += "__imm" + itostr(Val);
1370 case MatchableInfo::ResOperand::RegOperand: {
1371 std::string N = getQualifiedName(OpInfo.Register);
1372 CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n";
1373 Signature += "__reg" + OpInfo.Register->getName();
1378 II.ConversionFnKind = Signature;
1380 // Check if we have already generated this signature.
1381 if (!GeneratedFns.insert(Signature).second)
1384 // If not, emit it now. Add to the enum list.
1385 OS << " " << Signature << ",\n";
1387 CvtOS << " case " << Signature << ":\n";
1388 CvtOS << CaseOS.str();
1389 CvtOS << " return;\n";
1392 // Finish the convert function.
1397 // Finish the enum, and drop the convert function after it.
1399 OS << " NumConversionVariants\n";
1405 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1406 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1407 std::vector<ClassInfo*> &Infos,
1409 OS << "namespace {\n\n";
1411 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1412 << "/// instruction matching.\n";
1413 OS << "enum MatchClassKind {\n";
1414 OS << " InvalidMatchClass = 0,\n";
1415 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1416 ie = Infos.end(); it != ie; ++it) {
1417 ClassInfo &CI = **it;
1418 OS << " " << CI.Name << ", // ";
1419 if (CI.Kind == ClassInfo::Token) {
1420 OS << "'" << CI.ValueName << "'\n";
1421 } else if (CI.isRegisterClass()) {
1422 if (!CI.ValueName.empty())
1423 OS << "register class '" << CI.ValueName << "'\n";
1425 OS << "derived register class\n";
1427 OS << "user defined class '" << CI.ValueName << "'\n";
1430 OS << " NumMatchClassKinds\n";
1436 /// EmitClassifyOperand - Emit the function to classify an operand.
1437 static void EmitClassifyOperand(AsmMatcherInfo &Info,
1439 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
1440 << " " << Info.Target.getName() << "Operand &Operand = *("
1441 << Info.Target.getName() << "Operand*)GOp;\n";
1444 OS << " if (Operand.isToken())\n";
1445 OS << " return MatchTokenString(Operand.getToken());\n\n";
1447 // Classify registers.
1449 // FIXME: Don't hardcode isReg, getReg.
1450 OS << " if (Operand.isReg()) {\n";
1451 OS << " switch (Operand.getReg()) {\n";
1452 OS << " default: return InvalidMatchClass;\n";
1453 for (std::map<Record*, ClassInfo*>::iterator
1454 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1456 OS << " case " << Info.Target.getName() << "::"
1457 << it->first->getName() << ": return " << it->second->Name << ";\n";
1461 // Classify user defined operands.
1462 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1463 ie = Info.Classes.end(); it != ie; ++it) {
1464 ClassInfo &CI = **it;
1466 if (!CI.isUserClass())
1469 OS << " // '" << CI.ClassName << "' class";
1470 if (!CI.SuperClasses.empty()) {
1471 OS << ", subclass of ";
1472 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
1474 OS << "'" << CI.SuperClasses[i]->ClassName << "'";
1475 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
1480 OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
1482 // Validate subclass relationships.
1483 if (!CI.SuperClasses.empty()) {
1484 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
1485 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
1486 << "() && \"Invalid class relationship!\");\n";
1489 OS << " return " << CI.Name << ";\n";
1492 OS << " return InvalidMatchClass;\n";
1496 /// EmitIsSubclass - Emit the subclass predicate function.
1497 static void EmitIsSubclass(CodeGenTarget &Target,
1498 std::vector<ClassInfo*> &Infos,
1500 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1501 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1502 OS << " if (A == B)\n";
1503 OS << " return true;\n\n";
1505 OS << " switch (A) {\n";
1506 OS << " default:\n";
1507 OS << " return false;\n";
1508 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1509 ie = Infos.end(); it != ie; ++it) {
1510 ClassInfo &A = **it;
1512 if (A.Kind != ClassInfo::Token) {
1513 std::vector<StringRef> SuperClasses;
1514 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1515 ie = Infos.end(); it != ie; ++it) {
1516 ClassInfo &B = **it;
1518 if (&A != &B && A.isSubsetOf(B))
1519 SuperClasses.push_back(B.Name);
1522 if (SuperClasses.empty())
1525 OS << "\n case " << A.Name << ":\n";
1527 if (SuperClasses.size() == 1) {
1528 OS << " return B == " << SuperClasses.back() << ";\n";
1532 OS << " switch (B) {\n";
1533 OS << " default: return false;\n";
1534 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1535 OS << " case " << SuperClasses[i] << ": return true;\n";
1545 /// EmitMatchTokenString - Emit the function to match a token string to the
1546 /// appropriate match class value.
1547 static void EmitMatchTokenString(CodeGenTarget &Target,
1548 std::vector<ClassInfo*> &Infos,
1550 // Construct the match list.
1551 std::vector<StringMatcher::StringPair> Matches;
1552 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1553 ie = Infos.end(); it != ie; ++it) {
1554 ClassInfo &CI = **it;
1556 if (CI.Kind == ClassInfo::Token)
1557 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1558 "return " + CI.Name + ";"));
1561 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1563 StringMatcher("Name", Matches, OS).Emit();
1565 OS << " return InvalidMatchClass;\n";
1569 /// EmitMatchRegisterName - Emit the function to match a string to the target
1570 /// specific register enum.
1571 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1573 // Construct the match list.
1574 std::vector<StringMatcher::StringPair> Matches;
1575 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
1576 const CodeGenRegister &Reg = Target.getRegisters()[i];
1577 if (Reg.TheDef->getValueAsString("AsmName").empty())
1580 Matches.push_back(StringMatcher::StringPair(
1581 Reg.TheDef->getValueAsString("AsmName"),
1582 "return " + utostr(i + 1) + ";"));
1585 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1587 StringMatcher("Name", Matches, OS).Emit();
1589 OS << " return 0;\n";
1593 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1595 static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1597 OS << "// Flags for subtarget features that participate in "
1598 << "instruction matching.\n";
1599 OS << "enum SubtargetFeatureFlag {\n";
1600 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1601 it = Info.SubtargetFeatures.begin(),
1602 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1603 SubtargetFeatureInfo &SFI = *it->second;
1604 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1606 OS << " Feature_None = 0\n";
1610 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1611 /// available features given a subtarget.
1612 static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
1614 std::string ClassName =
1615 Info.AsmParser->getValueAsString("AsmParserClassName");
1617 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1618 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1619 << "Subtarget *Subtarget) const {\n";
1620 OS << " unsigned Features = 0;\n";
1621 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1622 it = Info.SubtargetFeatures.begin(),
1623 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1624 SubtargetFeatureInfo &SFI = *it->second;
1625 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1627 OS << " Features |= " << SFI.getEnumName() << ";\n";
1629 OS << " return Features;\n";
1633 static std::string GetAliasRequiredFeatures(Record *R,
1634 const AsmMatcherInfo &Info) {
1635 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
1637 unsigned NumFeatures = 0;
1638 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
1639 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
1642 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
1643 "' is not marked as an AssemblerPredicate!");
1648 Result += F->getEnumName();
1652 if (NumFeatures > 1)
1653 Result = '(' + Result + ')';
1657 /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
1658 /// emit a function for them and return true, otherwise return false.
1659 static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
1660 std::vector<Record*> Aliases =
1661 Records.getAllDerivedDefinitions("MnemonicAlias");
1662 if (Aliases.empty()) return false;
1664 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
1665 "unsigned Features) {\n";
1667 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
1668 // iteration order of the map is stable.
1669 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
1671 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
1672 Record *R = Aliases[i];
1673 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
1676 // Process each alias a "from" mnemonic at a time, building the code executed
1677 // by the string remapper.
1678 std::vector<StringMatcher::StringPair> Cases;
1679 for (std::map<std::string, std::vector<Record*> >::iterator
1680 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
1682 const std::vector<Record*> &ToVec = I->second;
1684 // Loop through each alias and emit code that handles each case. If there
1685 // are two instructions without predicates, emit an error. If there is one,
1687 std::string MatchCode;
1688 int AliasWithNoPredicate = -1;
1690 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
1691 Record *R = ToVec[i];
1692 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
1694 // If this unconditionally matches, remember it for later and diagnose
1696 if (FeatureMask.empty()) {
1697 if (AliasWithNoPredicate != -1) {
1698 // We can't have two aliases from the same mnemonic with no predicate.
1699 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
1700 "two MnemonicAliases with the same 'from' mnemonic!");
1701 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
1704 AliasWithNoPredicate = i;
1708 if (!MatchCode.empty())
1709 MatchCode += "else ";
1710 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
1711 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
1714 if (AliasWithNoPredicate != -1) {
1715 Record *R = ToVec[AliasWithNoPredicate];
1716 if (!MatchCode.empty())
1717 MatchCode += "else\n ";
1718 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
1721 MatchCode += "return;";
1723 Cases.push_back(std::make_pair(I->first, MatchCode));
1727 StringMatcher("Mnemonic", Cases, OS).Emit();
1733 void AsmMatcherEmitter::run(raw_ostream &OS) {
1734 CodeGenTarget Target;
1735 Record *AsmParser = Target.getAsmParser();
1736 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
1738 // Compute the information on the instructions to match.
1739 AsmMatcherInfo Info(AsmParser, Target);
1742 // Sort the instruction table using the partial order on classes. We use
1743 // stable_sort to ensure that ambiguous instructions are still
1744 // deterministically ordered.
1745 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
1746 less_ptr<MatchableInfo>());
1748 DEBUG_WITH_TYPE("instruction_info", {
1749 for (std::vector<MatchableInfo*>::iterator
1750 it = Info.Matchables.begin(), ie = Info.Matchables.end();
1755 // Check for ambiguous matchables.
1756 DEBUG_WITH_TYPE("ambiguous_instrs", {
1757 unsigned NumAmbiguous = 0;
1758 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
1759 for (unsigned j = i + 1; j != e; ++j) {
1760 MatchableInfo &A = *Info.Matchables[i];
1761 MatchableInfo &B = *Info.Matchables[j];
1763 if (A.CouldMatchAmiguouslyWith(B)) {
1764 errs() << "warning: ambiguous matchables:\n";
1766 errs() << "\nis incomparable with:\n";
1774 errs() << "warning: " << NumAmbiguous
1775 << " ambiguous matchables!\n";
1778 // Write the output.
1780 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1782 // Information for the class declaration.
1783 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
1784 OS << "#undef GET_ASSEMBLER_HEADER\n";
1785 OS << " // This should be included into the middle of the declaration of \n";
1786 OS << " // your subclasses implementation of TargetAsmParser.\n";
1787 OS << " unsigned ComputeAvailableFeatures(const " <<
1788 Target.getName() << "Subtarget *Subtarget) const;\n";
1789 OS << " enum MatchResultTy {\n";
1790 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n";
1791 OS << " Match_MissingFeature\n";
1793 OS << " MatchResultTy MatchInstructionImpl(const "
1794 << "SmallVectorImpl<MCParsedAsmOperand*>"
1795 << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n";
1796 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
1801 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
1802 OS << "#undef GET_REGISTER_MATCHER\n\n";
1804 // Emit the subtarget feature enumeration.
1805 EmitSubtargetFeatureFlagEnumeration(Info, OS);
1807 // Emit the function to match a register name to number.
1808 EmitMatchRegisterName(Target, AsmParser, OS);
1810 OS << "#endif // GET_REGISTER_MATCHER\n\n";
1813 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
1814 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
1816 // Generate the function that remaps for mnemonic aliases.
1817 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
1819 // Generate the unified function to convert operands into an MCInst.
1820 EmitConvertToMCInst(Target, Info.Matchables, OS);
1822 // Emit the enumeration for classes which participate in matching.
1823 EmitMatchClassEnumeration(Target, Info.Classes, OS);
1825 // Emit the routine to match token strings to their match class.
1826 EmitMatchTokenString(Target, Info.Classes, OS);
1828 // Emit the routine to classify an operand.
1829 EmitClassifyOperand(Info, OS);
1831 // Emit the subclass predicate routine.
1832 EmitIsSubclass(Target, Info.Classes, OS);
1834 // Emit the available features compute function.
1835 EmitComputeAvailableFeatures(Info, OS);
1838 size_t MaxNumOperands = 0;
1839 for (std::vector<MatchableInfo*>::const_iterator it =
1840 Info.Matchables.begin(), ie = Info.Matchables.end();
1842 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
1845 // Emit the static match table; unused classes get initalized to 0 which is
1846 // guaranteed to be InvalidMatchClass.
1848 // FIXME: We can reduce the size of this table very easily. First, we change
1849 // it so that store the kinds in separate bit-fields for each index, which
1850 // only needs to be the max width used for classes at that index (we also need
1851 // to reject based on this during classification). If we then make sure to
1852 // order the match kinds appropriately (putting mnemonics last), then we
1853 // should only end up using a few bits for each class, especially the ones
1854 // following the mnemonic.
1855 OS << "namespace {\n";
1856 OS << " struct MatchEntry {\n";
1857 OS << " unsigned Opcode;\n";
1858 OS << " const char *Mnemonic;\n";
1859 OS << " ConversionKind ConvertFn;\n";
1860 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1861 OS << " unsigned RequiredFeatures;\n";
1864 OS << "// Predicate for searching for an opcode.\n";
1865 OS << " struct LessOpcode {\n";
1866 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
1867 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
1869 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
1870 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
1872 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
1873 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
1877 OS << "} // end anonymous namespace.\n\n";
1879 OS << "static const MatchEntry MatchTable["
1880 << Info.Matchables.size() << "] = {\n";
1882 for (std::vector<MatchableInfo*>::const_iterator it =
1883 Info.Matchables.begin(), ie = Info.Matchables.end();
1885 MatchableInfo &II = **it;
1888 OS << " { " << Target.getName() << "::"
1889 << II.getResultInst()->TheDef->getName() << ", \"" << II.Mnemonic << "\""
1890 << ", " << II.ConversionFnKind << ", { ";
1891 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1892 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1895 OS << Op.Class->Name;
1899 // Write the required features mask.
1900 if (!II.RequiredFeatures.empty()) {
1901 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
1903 OS << II.RequiredFeatures[i]->getEnumName();
1913 // Finally, build the match function.
1914 OS << Target.getName() << ClassName << "::MatchResultTy "
1915 << Target.getName() << ClassName << "::\n"
1916 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
1918 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
1920 // Emit code to get the available features.
1921 OS << " // Get the current feature set.\n";
1922 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
1924 OS << " // Get the instruction mnemonic, which is the first token.\n";
1925 OS << " StringRef Mnemonic = ((" << Target.getName()
1926 << "Operand*)Operands[0])->getToken();\n\n";
1928 if (HasMnemonicAliases) {
1929 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
1930 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
1933 // Emit code to compute the class list for this operand vector.
1934 OS << " // Eliminate obvious mismatches.\n";
1935 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
1936 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
1937 OS << " return Match_InvalidOperand;\n";
1940 OS << " // Compute the class list for this operand vector.\n";
1941 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1942 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n";
1943 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n";
1945 OS << " // Check for invalid operands before matching.\n";
1946 OS << " if (Classes[i-1] == InvalidMatchClass) {\n";
1947 OS << " ErrorInfo = i;\n";
1948 OS << " return Match_InvalidOperand;\n";
1952 OS << " // Mark unused classes.\n";
1953 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; "
1954 << "i != e; ++i)\n";
1955 OS << " Classes[i] = InvalidMatchClass;\n\n";
1957 OS << " // Some state to try to produce better error messages.\n";
1958 OS << " bool HadMatchOtherThanFeatures = false;\n\n";
1959 OS << " // Set ErrorInfo to the operand that mismatches if it is \n";
1960 OS << " // wrong for all instances of the instruction.\n";
1961 OS << " ErrorInfo = ~0U;\n";
1963 // Emit code to search the table.
1964 OS << " // Search the table.\n";
1965 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
1966 OS << " std::equal_range(MatchTable, MatchTable+"
1967 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
1969 OS << " // Return a more specific error code if no mnemonics match.\n";
1970 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
1971 OS << " return Match_MnemonicFail;\n\n";
1973 OS << " for (const MatchEntry *it = MnemonicRange.first, "
1974 << "*ie = MnemonicRange.second;\n";
1975 OS << " it != ie; ++it) {\n";
1977 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
1978 OS << " assert(Mnemonic == it->Mnemonic);\n";
1980 // Emit check that the subclasses match.
1981 OS << " bool OperandsValid = true;\n";
1982 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
1983 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n";
1984 OS << " continue;\n";
1985 OS << " // If this operand is broken for all of the instances of this\n";
1986 OS << " // mnemonic, keep track of it so we can report loc info.\n";
1987 OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n";
1988 OS << " ErrorInfo = i+1;\n";
1990 OS << " ErrorInfo = ~0U;";
1991 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
1992 OS << " OperandsValid = false;\n";
1996 OS << " if (!OperandsValid) continue;\n";
1998 // Emit check that the required features are available.
1999 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2000 << "!= it->RequiredFeatures) {\n";
2001 OS << " HadMatchOtherThanFeatures = true;\n";
2002 OS << " continue;\n";
2006 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2008 // Call the post-processing function, if used.
2009 std::string InsnCleanupFn =
2010 AsmParser->getValueAsString("AsmParserInstCleanup");
2011 if (!InsnCleanupFn.empty())
2012 OS << " " << InsnCleanupFn << "(Inst);\n";
2014 OS << " return Match_Success;\n";
2017 OS << " // Okay, we had no match. Try to return a useful error code.\n";
2018 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
2019 OS << " return Match_InvalidOperand;\n";
2022 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";