1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures.
13 // The input to the target specific matcher is a list of literal tokens and
14 // operands. The target specific parser should generally eliminate any syntax
15 // which is not relevant for matching; for example, comma tokens should have
16 // already been consumed and eliminated by the parser. Most instructions will
17 // end up with a single literal token (the instruction name) and some number of
20 // Some example inputs, for X86:
21 // 'addl' (immediate ...) (register ...)
22 // 'add' (immediate ...) (memory ...)
25 // The assembly matcher is responsible for converting this input into a precise
26 // machine instruction (i.e., an instruction with a well defined encoding). This
27 // mapping has several properties which complicate matching:
29 // - It may be ambiguous; many architectures can legally encode particular
30 // variants of an instruction in different ways (for example, using a smaller
31 // encoding for small immediates). Such ambiguities should never be
32 // arbitrarily resolved by the assembler, the assembler is always responsible
33 // for choosing the "best" available instruction.
35 // - It may depend on the subtarget or the assembler context. Instructions
36 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
37 // an SSE instruction in a file being assembled for i486) should be accepted
38 // and rejected by the assembler front end. However, if the proper encoding
39 // for an instruction is dependent on the assembler context then the matcher
40 // is responsible for selecting the correct machine instruction for the
43 // The core matching algorithm attempts to exploit the regularity in most
44 // instruction sets to quickly determine the set of possibly matching
45 // instructions, and the simplify the generated code. Additionally, this helps
46 // to ensure that the ambiguities are intentionally resolved by the user.
48 // The matching is divided into two distinct phases:
50 // 1. Classification: Each operand is mapped to the unique set which (a)
51 // contains it, and (b) is the largest such subset for which a single
52 // instruction could match all members.
54 // For register classes, we can generate these subgroups automatically. For
55 // arbitrary operands, we expect the user to define the classes and their
56 // relations to one another (for example, 8-bit signed immediates as a
57 // subset of 32-bit immediates).
59 // By partitioning the operands in this way, we guarantee that for any
60 // tuple of classes, any single instruction must match either all or none
61 // of the sets of operands which could classify to that tuple.
63 // In addition, the subset relation amongst classes induces a partial order
64 // on such tuples, which we use to resolve ambiguities.
66 // 2. The input can now be treated as a tuple of classes (static tokens are
67 // simple singleton sets). Each such tuple should generally map to a single
68 // instruction (we currently ignore cases where this isn't true, whee!!!),
69 // which we can emit a simple matcher for.
71 //===----------------------------------------------------------------------===//
73 #include "AsmMatcherEmitter.h"
74 #include "CodeGenTarget.h"
76 #include "StringMatcher.h"
77 #include "llvm/ADT/OwningPtr.h"
78 #include "llvm/ADT/PointerUnion.h"
79 #include "llvm/ADT/SmallPtrSet.h"
80 #include "llvm/ADT/SmallVector.h"
81 #include "llvm/ADT/STLExtras.h"
82 #include "llvm/ADT/StringExtras.h"
83 #include "llvm/Support/CommandLine.h"
84 #include "llvm/Support/Debug.h"
89 static cl::opt<std::string>
90 MatchPrefix("match-prefix", cl::init(""),
91 cl::desc("Only match instructions with the given prefix"));
96 struct SubtargetFeatureInfo;
98 /// ClassInfo - Helper class for storing the information about a particular
99 /// class of operands which can be matched.
102 /// Invalid kind, for use as a sentinel value.
105 /// The class for a particular token.
108 /// The (first) register class, subsequent register classes are
109 /// RegisterClass0+1, and so on.
112 /// The (first) user defined class, subsequent user defined classes are
113 /// UserClass0+1, and so on.
117 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
118 /// N) for the Nth user defined class.
121 /// SuperClasses - The super classes of this class. Note that for simplicities
122 /// sake user operands only record their immediate super class, while register
123 /// operands include all superclasses.
124 std::vector<ClassInfo*> SuperClasses;
126 /// Name - The full class name, suitable for use in an enum.
129 /// ClassName - The unadorned generic name for this class (e.g., Token).
130 std::string ClassName;
132 /// ValueName - The name of the value this class represents; for a token this
133 /// is the literal token string, for an operand it is the TableGen class (or
134 /// empty if this is a derived class).
135 std::string ValueName;
137 /// PredicateMethod - The name of the operand method to test whether the
138 /// operand matches this class; this is not valid for Token or register kinds.
139 std::string PredicateMethod;
141 /// RenderMethod - The name of the operand method to add this operand to an
142 /// MCInst; this is not valid for Token or register kinds.
143 std::string RenderMethod;
145 /// For register classes, the records for all the registers in this class.
146 std::set<Record*> Registers;
149 /// isRegisterClass() - Check if this is a register class.
150 bool isRegisterClass() const {
151 return Kind >= RegisterClass0 && Kind < UserClass0;
154 /// isUserClass() - Check if this is a user defined class.
155 bool isUserClass() const {
156 return Kind >= UserClass0;
159 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
160 /// are related if they are in the same class hierarchy.
161 bool isRelatedTo(const ClassInfo &RHS) const {
162 // Tokens are only related to tokens.
163 if (Kind == Token || RHS.Kind == Token)
164 return Kind == Token && RHS.Kind == Token;
166 // Registers classes are only related to registers classes, and only if
167 // their intersection is non-empty.
168 if (isRegisterClass() || RHS.isRegisterClass()) {
169 if (!isRegisterClass() || !RHS.isRegisterClass())
172 std::set<Record*> Tmp;
173 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
174 std::set_intersection(Registers.begin(), Registers.end(),
175 RHS.Registers.begin(), RHS.Registers.end(),
181 // Otherwise we have two users operands; they are related if they are in the
182 // same class hierarchy.
184 // FIXME: This is an oversimplification, they should only be related if they
185 // intersect, however we don't have that information.
186 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
187 const ClassInfo *Root = this;
188 while (!Root->SuperClasses.empty())
189 Root = Root->SuperClasses.front();
191 const ClassInfo *RHSRoot = &RHS;
192 while (!RHSRoot->SuperClasses.empty())
193 RHSRoot = RHSRoot->SuperClasses.front();
195 return Root == RHSRoot;
198 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
199 bool isSubsetOf(const ClassInfo &RHS) const {
200 // This is a subset of RHS if it is the same class...
204 // ... or if any of its super classes are a subset of RHS.
205 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
206 ie = SuperClasses.end(); it != ie; ++it)
207 if ((*it)->isSubsetOf(RHS))
213 /// operator< - Compare two classes.
214 bool operator<(const ClassInfo &RHS) const {
218 // Unrelated classes can be ordered by kind.
219 if (!isRelatedTo(RHS))
220 return Kind < RHS.Kind;
224 assert(0 && "Invalid kind!");
226 // Tokens are comparable by value.
228 // FIXME: Compare by enum value.
229 return ValueName < RHS.ValueName;
232 // This class preceeds the RHS if it is a proper subset of the RHS.
235 if (RHS.isSubsetOf(*this))
238 // Otherwise, order by name to ensure we have a total ordering.
239 return ValueName < RHS.ValueName;
244 /// MatchableInfo - Helper class for storing the necessary information for an
245 /// instruction or alias which is capable of being matched.
246 struct MatchableInfo {
248 /// Token - This is the token that the operand came from.
251 /// The unique class instance this operand should match.
254 /// The operand name this is, if anything.
257 explicit AsmOperand(StringRef T) : Token(T), Class(0) {}
260 /// ResOperand - This represents a single operand in the result instruction
261 /// generated by the match. In cases (like addressing modes) where a single
262 /// assembler operand expands to multiple MCOperands, this represents the
263 /// single assembler operand, not the MCOperand.
266 /// RenderAsmOperand - This represents an operand result that is
267 /// generated by calling the render method on the assembly operand. The
268 /// corresponding AsmOperand is specified by AsmOperandNum.
271 /// TiedOperand - This represents a result operand that is a duplicate of
272 /// a previous result operand.
277 /// This is the operand # in the AsmOperands list that this should be
279 unsigned AsmOperandNum;
281 /// TiedOperandNum - This is the (earlier) result operand that should be
283 unsigned TiedOperandNum;
286 /// OpInfo - This is the information about the instruction operand that is
288 const CGIOperandList::OperandInfo *OpInfo;
290 static ResOperand getRenderedOp(unsigned AsmOpNum,
291 const CGIOperandList::OperandInfo *Op) {
293 X.Kind = RenderAsmOperand;
294 X.AsmOperandNum = AsmOpNum;
299 static ResOperand getTiedOp(unsigned TiedOperandNum,
300 const CGIOperandList::OperandInfo *Op) {
302 X.Kind = TiedOperand;
303 X.TiedOperandNum = TiedOperandNum;
309 /// TheDef - This is the definition of the instruction or InstAlias that this
310 /// matchable came from.
311 Record *const TheDef;
313 /// DefRec - This is the definition that it came from.
314 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
317 const CGIOperandList &TheOperandList;
320 /// ResOperands - This is the operand list that should be built for the result
322 std::vector<ResOperand> ResOperands;
324 /// AsmString - The assembly string for this instruction (with variants
325 /// removed), e.g. "movsx $src, $dst".
326 std::string AsmString;
328 /// Mnemonic - This is the first token of the matched instruction, its
332 /// AsmOperands - The textual operands that this instruction matches,
333 /// annotated with a class and where in the OperandList they were defined.
334 /// This directly corresponds to the tokenized AsmString after the mnemonic is
336 SmallVector<AsmOperand, 4> AsmOperands;
338 /// Predicates - The required subtarget features to match this instruction.
339 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
341 /// ConversionFnKind - The enum value which is passed to the generated
342 /// ConvertToMCInst to convert parsed operands into an MCInst for this
344 std::string ConversionFnKind;
346 MatchableInfo(const CodeGenInstruction &CGI)
347 : TheDef(CGI.TheDef), DefRec(&CGI),
348 TheOperandList(CGI.Operands), AsmString(CGI.AsmString) {
351 MatchableInfo(const CodeGenInstAlias *Alias)
352 : TheDef(Alias->TheDef), DefRec(Alias), TheOperandList(Alias->Operands),
353 AsmString(Alias->AsmString) {
356 void Initialize(const AsmMatcherInfo &Info,
357 SmallPtrSet<Record*, 16> &SingletonRegisters);
359 /// Validate - Return true if this matchable is a valid thing to match against
360 /// and perform a bunch of validity checking.
361 bool Validate(StringRef CommentDelimiter, bool Hack) const;
363 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
364 /// register, return the Record for it, otherwise return null.
365 Record *getSingletonRegisterForAsmOperand(unsigned i,
366 const AsmMatcherInfo &Info) const;
368 int FindAsmOperandNamed(StringRef N) const {
369 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
370 if (N == AsmOperands[i].SrcOpName)
375 void BuildResultOperands();
377 /// operator< - Compare two matchables.
378 bool operator<(const MatchableInfo &RHS) const {
379 // The primary comparator is the instruction mnemonic.
380 if (Mnemonic != RHS.Mnemonic)
381 return Mnemonic < RHS.Mnemonic;
383 if (AsmOperands.size() != RHS.AsmOperands.size())
384 return AsmOperands.size() < RHS.AsmOperands.size();
386 // Compare lexicographically by operand. The matcher validates that other
387 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith().
388 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
389 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
391 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
398 /// CouldMatchAmiguouslyWith - Check whether this matchable could
399 /// ambiguously match the same set of operands as \arg RHS (without being a
400 /// strictly superior match).
401 bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) {
402 // The primary comparator is the instruction mnemonic.
403 if (Mnemonic != RHS.Mnemonic)
406 // The number of operands is unambiguous.
407 if (AsmOperands.size() != RHS.AsmOperands.size())
410 // Otherwise, make sure the ordering of the two instructions is unambiguous
411 // by checking that either (a) a token or operand kind discriminates them,
412 // or (b) the ordering among equivalent kinds is consistent.
414 // Tokens and operand kinds are unambiguous (assuming a correct target
416 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
417 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
418 AsmOperands[i].Class->Kind == ClassInfo::Token)
419 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
420 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
423 // Otherwise, this operand could commute if all operands are equivalent, or
424 // there is a pair of operands that compare less than and a pair that
425 // compare greater than.
426 bool HasLT = false, HasGT = false;
427 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
428 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
430 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
434 return !(HasLT ^ HasGT);
440 void TokenizeAsmString(const AsmMatcherInfo &Info);
443 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
444 /// feature which participates in instruction matching.
445 struct SubtargetFeatureInfo {
446 /// \brief The predicate record for this feature.
449 /// \brief An unique index assigned to represent this feature.
452 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
454 /// \brief The name of the enumerated constant identifying this feature.
455 std::string getEnumName() const {
456 return "Feature_" + TheDef->getName();
460 class AsmMatcherInfo {
462 /// The tablegen AsmParser record.
465 /// Target - The target information.
466 CodeGenTarget &Target;
468 /// The AsmParser "RegisterPrefix" value.
469 std::string RegisterPrefix;
471 /// The classes which are needed for matching.
472 std::vector<ClassInfo*> Classes;
474 /// The information on the matchables to match.
475 std::vector<MatchableInfo*> Matchables;
477 /// Map of Register records to their class information.
478 std::map<Record*, ClassInfo*> RegisterClasses;
480 /// Map of Predicate records to their subtarget information.
481 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
484 /// Map of token to class information which has already been constructed.
485 std::map<std::string, ClassInfo*> TokenClasses;
487 /// Map of RegisterClass records to their class information.
488 std::map<Record*, ClassInfo*> RegisterClassClasses;
490 /// Map of AsmOperandClass records to their class information.
491 std::map<Record*, ClassInfo*> AsmOperandClasses;
494 /// getTokenClass - Lookup or create the class for the given token.
495 ClassInfo *getTokenClass(StringRef Token);
497 /// getOperandClass - Lookup or create the class for the given operand.
498 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI);
500 /// BuildRegisterClasses - Build the ClassInfo* instances for register
502 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
504 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
506 void BuildOperandClasses();
508 void BuildInstructionOperandReference(MatchableInfo *II,
510 MatchableInfo::AsmOperand &Op);
511 void BuildAliasOperandReference(MatchableInfo *II,
513 MatchableInfo::AsmOperand &Op);
516 AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target);
518 /// BuildInfo - Construct the various tables used during matching.
521 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
523 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
524 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
525 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
526 SubtargetFeatures.find(Def);
527 return I == SubtargetFeatures.end() ? 0 : I->second;
533 void MatchableInfo::dump() {
534 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
536 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
537 AsmOperand &Op = AsmOperands[i];
538 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
539 errs() << '\"' << Op.Token << "\"\n";
541 if (!Op.OperandInfo) {
542 errs() << "(singleton register)\n";
546 const CGIOperandList::OperandInfo &OI = *Op.OperandInfo;
547 errs() << OI.Name << " " << OI.Rec->getName()
548 << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n";
553 void MatchableInfo::Initialize(const AsmMatcherInfo &Info,
554 SmallPtrSet<Record*, 16> &SingletonRegisters) {
555 // TODO: Eventually support asmparser for Variant != 0.
556 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0);
558 TokenizeAsmString(Info);
560 // Compute the require features.
561 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
562 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
563 if (SubtargetFeatureInfo *Feature =
564 Info.getSubtargetFeature(Predicates[i]))
565 RequiredFeatures.push_back(Feature);
567 // Collect singleton registers, if used.
568 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
569 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
570 SingletonRegisters.insert(Reg);
574 /// TokenizeAsmString - Tokenize a simplified assembly string.
575 void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) {
576 StringRef String = AsmString;
579 for (unsigned i = 0, e = String.size(); i != e; ++i) {
589 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
592 if (!isspace(String[i]) && String[i] != ',')
593 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
599 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
603 assert(i != String.size() && "Invalid quoted character");
604 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
609 // If this isn't "${", treat like a normal token.
610 if (i + 1 == String.size() || String[i + 1] != '{') {
612 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
620 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
624 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
625 assert(End != String.end() && "Missing brace in operand reference!");
626 size_t EndPos = End - String.begin();
627 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
635 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
644 if (InTok && Prev != String.size())
645 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
647 // The first token of the instruction is the mnemonic, which must be a
648 // simple string, not a $foo variable or a singleton register.
649 assert(!AsmOperands.empty() && "Instruction has no tokens?");
650 Mnemonic = AsmOperands[0].Token;
651 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info))
652 throw TGError(TheDef->getLoc(),
653 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
655 // Remove the first operand, it is tracked in the mnemonic field.
656 AsmOperands.erase(AsmOperands.begin());
661 bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const {
662 // Reject matchables with no .s string.
663 if (AsmString.empty())
664 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
666 // Reject any matchables with a newline in them, they should be marked
667 // isCodeGenOnly if they are pseudo instructions.
668 if (AsmString.find('\n') != std::string::npos)
669 throw TGError(TheDef->getLoc(),
670 "multiline instruction is not valid for the asmparser, "
671 "mark it isCodeGenOnly");
673 // Remove comments from the asm string. We know that the asmstring only
675 if (!CommentDelimiter.empty() &&
676 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
677 throw TGError(TheDef->getLoc(),
678 "asmstring for instruction has comment character in it, "
679 "mark it isCodeGenOnly");
681 // Reject matchables with operand modifiers, these aren't something we can
682 /// handle, the target should be refactored to use operands instead of
685 // Also, check for instructions which reference the operand multiple times;
686 // this implies a constraint we would not honor.
687 std::set<std::string> OperandNames;
688 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
689 StringRef Tok = AsmOperands[i].Token;
690 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
691 throw TGError(TheDef->getLoc(),
692 "matchable with operand modifier '" + Tok.str() +
693 "' not supported by asm matcher. Mark isCodeGenOnly!");
695 // Verify that any operand is only mentioned once.
696 // We reject aliases and ignore instructions for now.
697 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
699 throw TGError(TheDef->getLoc(),
700 "ERROR: matchable with tied operand '" + Tok.str() +
701 "' can never be matched!");
702 // FIXME: Should reject these. The ARM backend hits this with $lane in a
703 // bunch of instructions. It is unclear what the right answer is.
705 errs() << "warning: '" << TheDef->getName() << "': "
706 << "ignoring instruction with tied operand '"
707 << Tok.str() << "'\n";
717 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
718 /// register, return the register name, otherwise return a null StringRef.
719 Record *MatchableInfo::
720 getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{
721 StringRef Tok = AsmOperands[i].Token;
722 if (!Tok.startswith(Info.RegisterPrefix))
725 StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
726 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
729 // If there is no register prefix (i.e. "%" in "%eax"), then this may
730 // be some random non-register token, just ignore it.
731 if (Info.RegisterPrefix.empty())
734 // Otherwise, we have something invalid prefixed with the register prefix,
736 std::string Err = "unable to find register for '" + RegName.str() +
737 "' (which matches register prefix)";
738 throw TGError(TheDef->getLoc(), Err);
742 static std::string getEnumNameForToken(StringRef Str) {
745 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
747 case '*': Res += "_STAR_"; break;
748 case '%': Res += "_PCT_"; break;
749 case ':': Res += "_COLON_"; break;
754 Res += "_" + utostr((unsigned) *it) + "_";
761 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
762 ClassInfo *&Entry = TokenClasses[Token];
765 Entry = new ClassInfo();
766 Entry->Kind = ClassInfo::Token;
767 Entry->ClassName = "Token";
768 Entry->Name = "MCK_" + getEnumNameForToken(Token);
769 Entry->ValueName = Token;
770 Entry->PredicateMethod = "<invalid>";
771 Entry->RenderMethod = "<invalid>";
772 Classes.push_back(Entry);
779 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI) {
780 if (OI.Rec->isSubClassOf("RegisterClass")) {
781 if (ClassInfo *CI = RegisterClassClasses[OI.Rec])
783 throw TGError(OI.Rec->getLoc(), "register class has no class info!");
786 assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!");
787 Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
788 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
791 throw TGError(OI.Rec->getLoc(), "operand has no match class!");
794 void AsmMatcherInfo::
795 BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
796 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
797 const std::vector<CodeGenRegisterClass> &RegClassList =
798 Target.getRegisterClasses();
800 // The register sets used for matching.
801 std::set< std::set<Record*> > RegisterSets;
803 // Gather the defined sets.
804 for (std::vector<CodeGenRegisterClass>::const_iterator it =
805 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
806 RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
807 it->Elements.end()));
809 // Add any required singleton sets.
810 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
811 ie = SingletonRegisters.end(); it != ie; ++it) {
813 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
816 // Introduce derived sets where necessary (when a register does not determine
817 // a unique register set class), and build the mapping of registers to the set
818 // they should classify to.
819 std::map<Record*, std::set<Record*> > RegisterMap;
820 for (std::vector<CodeGenRegister>::const_iterator it = Registers.begin(),
821 ie = Registers.end(); it != ie; ++it) {
822 const CodeGenRegister &CGR = *it;
823 // Compute the intersection of all sets containing this register.
824 std::set<Record*> ContainingSet;
826 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
827 ie = RegisterSets.end(); it != ie; ++it) {
828 if (!it->count(CGR.TheDef))
831 if (ContainingSet.empty()) {
836 std::set<Record*> Tmp;
837 std::swap(Tmp, ContainingSet);
838 std::insert_iterator< std::set<Record*> > II(ContainingSet,
839 ContainingSet.begin());
840 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
843 if (!ContainingSet.empty()) {
844 RegisterSets.insert(ContainingSet);
845 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
849 // Construct the register classes.
850 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
852 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
853 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
854 ClassInfo *CI = new ClassInfo();
855 CI->Kind = ClassInfo::RegisterClass0 + Index;
856 CI->ClassName = "Reg" + utostr(Index);
857 CI->Name = "MCK_Reg" + utostr(Index);
859 CI->PredicateMethod = ""; // unused
860 CI->RenderMethod = "addRegOperands";
862 Classes.push_back(CI);
863 RegisterSetClasses.insert(std::make_pair(*it, CI));
866 // Find the superclasses; we could compute only the subgroup lattice edges,
867 // but there isn't really a point.
868 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
869 ie = RegisterSets.end(); it != ie; ++it) {
870 ClassInfo *CI = RegisterSetClasses[*it];
871 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
872 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
874 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
875 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
878 // Name the register classes which correspond to a user defined RegisterClass.
879 for (std::vector<CodeGenRegisterClass>::const_iterator
880 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
881 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
882 it->Elements.end())];
883 if (CI->ValueName.empty()) {
884 CI->ClassName = it->getName();
885 CI->Name = "MCK_" + it->getName();
886 CI->ValueName = it->getName();
888 CI->ValueName = CI->ValueName + "," + it->getName();
890 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
893 // Populate the map for individual registers.
894 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
895 ie = RegisterMap.end(); it != ie; ++it)
896 RegisterClasses[it->first] = RegisterSetClasses[it->second];
898 // Name the register classes which correspond to singleton registers.
899 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
900 ie = SingletonRegisters.end(); it != ie; ++it) {
902 ClassInfo *CI = RegisterClasses[Rec];
903 assert(CI && "Missing singleton register class info!");
905 if (CI->ValueName.empty()) {
906 CI->ClassName = Rec->getName();
907 CI->Name = "MCK_" + Rec->getName();
908 CI->ValueName = Rec->getName();
910 CI->ValueName = CI->ValueName + "," + Rec->getName();
914 void AsmMatcherInfo::BuildOperandClasses() {
915 std::vector<Record*> AsmOperands =
916 Records.getAllDerivedDefinitions("AsmOperandClass");
918 // Pre-populate AsmOperandClasses map.
919 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
920 ie = AsmOperands.end(); it != ie; ++it)
921 AsmOperandClasses[*it] = new ClassInfo();
924 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
925 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
926 ClassInfo *CI = AsmOperandClasses[*it];
927 CI->Kind = ClassInfo::UserClass0 + Index;
929 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
930 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
931 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
933 PrintError((*it)->getLoc(), "Invalid super class reference!");
937 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
939 PrintError((*it)->getLoc(), "Invalid super class reference!");
941 CI->SuperClasses.push_back(SC);
943 CI->ClassName = (*it)->getValueAsString("Name");
944 CI->Name = "MCK_" + CI->ClassName;
945 CI->ValueName = (*it)->getName();
947 // Get or construct the predicate method name.
948 Init *PMName = (*it)->getValueInit("PredicateMethod");
949 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
950 CI->PredicateMethod = SI->getValue();
952 assert(dynamic_cast<UnsetInit*>(PMName) &&
953 "Unexpected PredicateMethod field!");
954 CI->PredicateMethod = "is" + CI->ClassName;
957 // Get or construct the render method name.
958 Init *RMName = (*it)->getValueInit("RenderMethod");
959 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
960 CI->RenderMethod = SI->getValue();
962 assert(dynamic_cast<UnsetInit*>(RMName) &&
963 "Unexpected RenderMethod field!");
964 CI->RenderMethod = "add" + CI->ClassName + "Operands";
967 AsmOperandClasses[*it] = CI;
968 Classes.push_back(CI);
972 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target)
973 : AsmParser(asmParser), Target(target),
974 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
978 void AsmMatcherInfo::BuildInfo() {
979 // Build information about all of the AssemblerPredicates.
980 std::vector<Record*> AllPredicates =
981 Records.getAllDerivedDefinitions("Predicate");
982 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
983 Record *Pred = AllPredicates[i];
984 // Ignore predicates that are not intended for the assembler.
985 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
988 if (Pred->getName().empty())
989 throw TGError(Pred->getLoc(), "Predicate has no name!");
991 unsigned FeatureNo = SubtargetFeatures.size();
992 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
993 assert(FeatureNo < 32 && "Too many subtarget features!");
996 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
998 // Parse the instructions; we need to do this first so that we can gather the
999 // singleton register classes.
1000 SmallPtrSet<Record*, 16> SingletonRegisters;
1001 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1002 E = Target.inst_end(); I != E; ++I) {
1003 const CodeGenInstruction &CGI = **I;
1005 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1006 // filter the set of instructions we consider.
1007 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1010 // Ignore "codegen only" instructions.
1011 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1014 // Validate the operand list to ensure we can handle this instruction.
1015 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1016 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1018 // Validate tied operands.
1019 if (OI.getTiedRegister() != -1) {
1020 // If we have a tied operand that consists of multiple MCOperands, reject
1021 // it. We reject aliases and ignore instructions for now.
1022 if (OI.MINumOperands != 1) {
1023 // FIXME: Should reject these. The ARM backend hits this with $lane
1024 // in a bunch of instructions. It is unclear what the right answer is.
1026 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1027 << "ignoring instruction with multi-operand tied operand '"
1028 << OI.Name << "'\n";
1035 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1037 II->Initialize(*this, SingletonRegisters);
1039 // Ignore instructions which shouldn't be matched and diagnose invalid
1040 // instruction definitions with an error.
1041 if (!II->Validate(CommentDelimiter, true))
1044 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1046 // FIXME: This is a total hack.
1047 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1048 StringRef(II->TheDef->getName()).endswith("_Int"))
1051 Matchables.push_back(II.take());
1054 // Parse all of the InstAlias definitions and stick them in the list of
1056 std::vector<Record*> AllInstAliases =
1057 Records.getAllDerivedDefinitions("InstAlias");
1058 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1059 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1061 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1063 II->Initialize(*this, SingletonRegisters);
1065 // Validate the alias definitions.
1066 II->Validate(CommentDelimiter, false);
1068 Matchables.push_back(II.take());
1071 // Build info for the register classes.
1072 BuildRegisterClasses(SingletonRegisters);
1074 // Build info for the user defined assembly operand classes.
1075 BuildOperandClasses();
1077 // Build the information about matchables, now that we have fully formed
1079 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1080 ie = Matchables.end(); it != ie; ++it) {
1081 MatchableInfo *II = *it;
1083 // Parse the tokens after the mnemonic.
1084 for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) {
1085 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1086 StringRef Token = Op.Token;
1088 // Check for singleton registers.
1089 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) {
1090 Op.Class = RegisterClasses[RegRecord];
1091 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1092 "Unexpected class for singleton register");
1096 // Check for simple tokens.
1097 if (Token[0] != '$') {
1098 Op.Class = getTokenClass(Token);
1102 // Otherwise this is an operand reference.
1103 StringRef OperandName;
1104 if (Token[1] == '{')
1105 OperandName = Token.substr(2, Token.size() - 3);
1107 OperandName = Token.substr(1);
1109 if (II->DefRec.is<const CodeGenInstruction*>())
1110 BuildInstructionOperandReference(II, OperandName, Op);
1112 BuildAliasOperandReference(II, OperandName, Op);
1115 II->BuildResultOperands();
1118 // Reorder classes so that classes preceed super classes.
1119 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1122 /// BuildInstructionOperandReference - The specified operand is a reference to a
1123 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1124 void AsmMatcherInfo::
1125 BuildInstructionOperandReference(MatchableInfo *II,
1126 StringRef OperandName,
1127 MatchableInfo::AsmOperand &Op) {
1128 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1129 const CGIOperandList &Operands = CGI.Operands;
1131 // Map this token to an operand. FIXME: Move elsewhere.
1133 if (!Operands.hasOperandNamed(OperandName, Idx))
1134 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1135 OperandName.str() + "'");
1137 // Set up the operand class.
1138 Op.Class = getOperandClass(Operands[Idx]);
1140 // If the named operand is tied, canonicalize it to the untied operand.
1141 // For example, something like:
1142 // (outs GPR:$dst), (ins GPR:$src)
1143 // with an asmstring of
1145 // we want to canonicalize to:
1147 // so that we know how to provide the $dst operand when filling in the result.
1148 int OITied = Operands[Idx].getTiedRegister();
1150 // The tied operand index is an MIOperand index, find the operand that
1152 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
1153 if (Operands[i].MIOperandNo == unsigned(OITied)) {
1154 OperandName = Operands[i].Name;
1160 Op.SrcOpName = OperandName;
1163 /// BuildAliasOperandReference - When parsing an operand reference out of the
1164 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1165 /// operand reference is by looking it up in the result pattern definition.
1166 void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II,
1167 StringRef OperandName,
1168 MatchableInfo::AsmOperand &Op) {
1169 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1171 // Set up the operand class.
1172 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1173 if (CGA.ResultOperands[i].Name == OperandName) {
1174 Op.Class = getOperandClass(CGA.ResultInst->Operands[i]);
1175 Op.SrcOpName = OperandName;
1179 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1180 OperandName.str() + "'");
1183 void MatchableInfo::BuildResultOperands() {
1184 for (unsigned i = 0, e = TheOperandList.size(); i != e; ++i) {
1185 const CGIOperandList::OperandInfo &OpInfo = TheOperandList[i];
1187 // If this is a tied operand, just copy from the previously handled operand.
1188 int TiedOp = OpInfo.getTiedRegister();
1190 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo));
1194 // Find out what operand from the asmparser that this MCInst operand comes
1196 int SrcOperand = FindAsmOperandNamed(OpInfo.Name);
1198 if (!OpInfo.Name.empty() && SrcOperand != -1) {
1199 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo));
1203 throw TGError(TheDef->getLoc(), "Instruction '" +
1204 TheDef->getName() + "' has operand '" + OpInfo.Name +
1205 "' that doesn't appear in asm string!");
1210 static void EmitConvertToMCInst(CodeGenTarget &Target,
1211 std::vector<MatchableInfo*> &Infos,
1213 // Write the convert function to a separate stream, so we can drop it after
1215 std::string ConvertFnBody;
1216 raw_string_ostream CvtOS(ConvertFnBody);
1218 // Function we have already generated.
1219 std::set<std::string> GeneratedFns;
1221 // Start the unified conversion function.
1222 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
1223 << "unsigned Opcode,\n"
1224 << " const SmallVectorImpl<MCParsedAsmOperand*"
1225 << "> &Operands) {\n";
1226 CvtOS << " Inst.setOpcode(Opcode);\n";
1227 CvtOS << " switch (Kind) {\n";
1228 CvtOS << " default:\n";
1230 // Start the enum, which we will generate inline.
1232 OS << "// Unified function for converting operands to MCInst instances.\n\n";
1233 OS << "enum ConversionKind {\n";
1235 // TargetOperandClass - This is the target's operand class, like X86Operand.
1236 std::string TargetOperandClass = Target.getName() + "Operand";
1238 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1239 ie = Infos.end(); it != ie; ++it) {
1240 MatchableInfo &II = **it;
1242 // Build the conversion function signature.
1243 std::string Signature = "Convert";
1244 std::string CaseBody;
1245 raw_string_ostream CaseOS(CaseBody);
1247 // Compute the convert enum and the case body.
1248 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1249 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1251 // Generate code to populate each result operand.
1252 switch (OpInfo.Kind) {
1253 default: assert(0 && "Unknown result operand kind");
1254 case MatchableInfo::ResOperand::RenderAsmOperand: {
1255 // This comes from something we parsed.
1256 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1258 // Registers are always converted the same, don't duplicate the
1259 // conversion function based on them.
1261 if (Op.Class->isRegisterClass())
1264 Signature += Op.Class->ClassName;
1265 Signature += utostr(OpInfo.OpInfo->MINumOperands);
1266 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1268 CaseOS << " ((" << TargetOperandClass << "*)Operands["
1269 << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod
1270 << "(Inst, " << OpInfo.OpInfo->MINumOperands << ");\n";
1274 case MatchableInfo::ResOperand::TiedOperand: {
1275 // If this operand is tied to a previous one, just copy the MCInst
1276 // operand from the earlier one.We can only tie single MCOperand values.
1277 //assert(OpInfo.OpInfo->MINumOperands == 1 && "Not a singular MCOperand");
1278 unsigned TiedOp = OpInfo.TiedOperandNum;
1279 assert(i > TiedOp && "Tied operand preceeds its target!");
1280 CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
1281 Signature += "__Tie" + utostr(TiedOp);
1287 II.ConversionFnKind = Signature;
1289 // Check if we have already generated this signature.
1290 if (!GeneratedFns.insert(Signature).second)
1293 // If not, emit it now. Add to the enum list.
1294 OS << " " << Signature << ",\n";
1296 CvtOS << " case " << Signature << ":\n";
1297 CvtOS << CaseOS.str();
1298 CvtOS << " return;\n";
1301 // Finish the convert function.
1306 // Finish the enum, and drop the convert function after it.
1308 OS << " NumConversionVariants\n";
1314 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1315 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1316 std::vector<ClassInfo*> &Infos,
1318 OS << "namespace {\n\n";
1320 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1321 << "/// instruction matching.\n";
1322 OS << "enum MatchClassKind {\n";
1323 OS << " InvalidMatchClass = 0,\n";
1324 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1325 ie = Infos.end(); it != ie; ++it) {
1326 ClassInfo &CI = **it;
1327 OS << " " << CI.Name << ", // ";
1328 if (CI.Kind == ClassInfo::Token) {
1329 OS << "'" << CI.ValueName << "'\n";
1330 } else if (CI.isRegisterClass()) {
1331 if (!CI.ValueName.empty())
1332 OS << "register class '" << CI.ValueName << "'\n";
1334 OS << "derived register class\n";
1336 OS << "user defined class '" << CI.ValueName << "'\n";
1339 OS << " NumMatchClassKinds\n";
1345 /// EmitClassifyOperand - Emit the function to classify an operand.
1346 static void EmitClassifyOperand(AsmMatcherInfo &Info,
1348 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
1349 << " " << Info.Target.getName() << "Operand &Operand = *("
1350 << Info.Target.getName() << "Operand*)GOp;\n";
1353 OS << " if (Operand.isToken())\n";
1354 OS << " return MatchTokenString(Operand.getToken());\n\n";
1356 // Classify registers.
1358 // FIXME: Don't hardcode isReg, getReg.
1359 OS << " if (Operand.isReg()) {\n";
1360 OS << " switch (Operand.getReg()) {\n";
1361 OS << " default: return InvalidMatchClass;\n";
1362 for (std::map<Record*, ClassInfo*>::iterator
1363 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1365 OS << " case " << Info.Target.getName() << "::"
1366 << it->first->getName() << ": return " << it->second->Name << ";\n";
1370 // Classify user defined operands.
1371 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1372 ie = Info.Classes.end(); it != ie; ++it) {
1373 ClassInfo &CI = **it;
1375 if (!CI.isUserClass())
1378 OS << " // '" << CI.ClassName << "' class";
1379 if (!CI.SuperClasses.empty()) {
1380 OS << ", subclass of ";
1381 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
1383 OS << "'" << CI.SuperClasses[i]->ClassName << "'";
1384 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
1389 OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
1391 // Validate subclass relationships.
1392 if (!CI.SuperClasses.empty()) {
1393 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
1394 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
1395 << "() && \"Invalid class relationship!\");\n";
1398 OS << " return " << CI.Name << ";\n";
1401 OS << " return InvalidMatchClass;\n";
1405 /// EmitIsSubclass - Emit the subclass predicate function.
1406 static void EmitIsSubclass(CodeGenTarget &Target,
1407 std::vector<ClassInfo*> &Infos,
1409 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1410 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1411 OS << " if (A == B)\n";
1412 OS << " return true;\n\n";
1414 OS << " switch (A) {\n";
1415 OS << " default:\n";
1416 OS << " return false;\n";
1417 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1418 ie = Infos.end(); it != ie; ++it) {
1419 ClassInfo &A = **it;
1421 if (A.Kind != ClassInfo::Token) {
1422 std::vector<StringRef> SuperClasses;
1423 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1424 ie = Infos.end(); it != ie; ++it) {
1425 ClassInfo &B = **it;
1427 if (&A != &B && A.isSubsetOf(B))
1428 SuperClasses.push_back(B.Name);
1431 if (SuperClasses.empty())
1434 OS << "\n case " << A.Name << ":\n";
1436 if (SuperClasses.size() == 1) {
1437 OS << " return B == " << SuperClasses.back() << ";\n";
1441 OS << " switch (B) {\n";
1442 OS << " default: return false;\n";
1443 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1444 OS << " case " << SuperClasses[i] << ": return true;\n";
1454 /// EmitMatchTokenString - Emit the function to match a token string to the
1455 /// appropriate match class value.
1456 static void EmitMatchTokenString(CodeGenTarget &Target,
1457 std::vector<ClassInfo*> &Infos,
1459 // Construct the match list.
1460 std::vector<StringMatcher::StringPair> Matches;
1461 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1462 ie = Infos.end(); it != ie; ++it) {
1463 ClassInfo &CI = **it;
1465 if (CI.Kind == ClassInfo::Token)
1466 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1467 "return " + CI.Name + ";"));
1470 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1472 StringMatcher("Name", Matches, OS).Emit();
1474 OS << " return InvalidMatchClass;\n";
1478 /// EmitMatchRegisterName - Emit the function to match a string to the target
1479 /// specific register enum.
1480 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1482 // Construct the match list.
1483 std::vector<StringMatcher::StringPair> Matches;
1484 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
1485 const CodeGenRegister &Reg = Target.getRegisters()[i];
1486 if (Reg.TheDef->getValueAsString("AsmName").empty())
1489 Matches.push_back(StringMatcher::StringPair(
1490 Reg.TheDef->getValueAsString("AsmName"),
1491 "return " + utostr(i + 1) + ";"));
1494 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1496 StringMatcher("Name", Matches, OS).Emit();
1498 OS << " return 0;\n";
1502 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1504 static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1506 OS << "// Flags for subtarget features that participate in "
1507 << "instruction matching.\n";
1508 OS << "enum SubtargetFeatureFlag {\n";
1509 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1510 it = Info.SubtargetFeatures.begin(),
1511 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1512 SubtargetFeatureInfo &SFI = *it->second;
1513 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1515 OS << " Feature_None = 0\n";
1519 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1520 /// available features given a subtarget.
1521 static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
1523 std::string ClassName =
1524 Info.AsmParser->getValueAsString("AsmParserClassName");
1526 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1527 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1528 << "Subtarget *Subtarget) const {\n";
1529 OS << " unsigned Features = 0;\n";
1530 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1531 it = Info.SubtargetFeatures.begin(),
1532 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1533 SubtargetFeatureInfo &SFI = *it->second;
1534 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1536 OS << " Features |= " << SFI.getEnumName() << ";\n";
1538 OS << " return Features;\n";
1542 static std::string GetAliasRequiredFeatures(Record *R,
1543 const AsmMatcherInfo &Info) {
1544 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
1546 unsigned NumFeatures = 0;
1547 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
1548 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
1551 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
1552 "' is not marked as an AssemblerPredicate!");
1557 Result += F->getEnumName();
1561 if (NumFeatures > 1)
1562 Result = '(' + Result + ')';
1566 /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
1567 /// emit a function for them and return true, otherwise return false.
1568 static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
1569 std::vector<Record*> Aliases =
1570 Records.getAllDerivedDefinitions("MnemonicAlias");
1571 if (Aliases.empty()) return false;
1573 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
1574 "unsigned Features) {\n";
1576 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
1577 // iteration order of the map is stable.
1578 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
1580 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
1581 Record *R = Aliases[i];
1582 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
1585 // Process each alias a "from" mnemonic at a time, building the code executed
1586 // by the string remapper.
1587 std::vector<StringMatcher::StringPair> Cases;
1588 for (std::map<std::string, std::vector<Record*> >::iterator
1589 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
1591 const std::vector<Record*> &ToVec = I->second;
1593 // Loop through each alias and emit code that handles each case. If there
1594 // are two instructions without predicates, emit an error. If there is one,
1596 std::string MatchCode;
1597 int AliasWithNoPredicate = -1;
1599 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
1600 Record *R = ToVec[i];
1601 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
1603 // If this unconditionally matches, remember it for later and diagnose
1605 if (FeatureMask.empty()) {
1606 if (AliasWithNoPredicate != -1) {
1607 // We can't have two aliases from the same mnemonic with no predicate.
1608 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
1609 "two MnemonicAliases with the same 'from' mnemonic!");
1610 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
1613 AliasWithNoPredicate = i;
1617 if (!MatchCode.empty())
1618 MatchCode += "else ";
1619 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
1620 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
1623 if (AliasWithNoPredicate != -1) {
1624 Record *R = ToVec[AliasWithNoPredicate];
1625 if (!MatchCode.empty())
1626 MatchCode += "else\n ";
1627 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
1630 MatchCode += "return;";
1632 Cases.push_back(std::make_pair(I->first, MatchCode));
1636 StringMatcher("Mnemonic", Cases, OS).Emit();
1642 void AsmMatcherEmitter::run(raw_ostream &OS) {
1643 CodeGenTarget Target;
1644 Record *AsmParser = Target.getAsmParser();
1645 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
1647 // Compute the information on the instructions to match.
1648 AsmMatcherInfo Info(AsmParser, Target);
1651 // Sort the instruction table using the partial order on classes. We use
1652 // stable_sort to ensure that ambiguous instructions are still
1653 // deterministically ordered.
1654 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
1655 less_ptr<MatchableInfo>());
1657 DEBUG_WITH_TYPE("instruction_info", {
1658 for (std::vector<MatchableInfo*>::iterator
1659 it = Info.Matchables.begin(), ie = Info.Matchables.end();
1664 // Check for ambiguous matchables.
1665 DEBUG_WITH_TYPE("ambiguous_instrs", {
1666 unsigned NumAmbiguous = 0;
1667 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
1668 for (unsigned j = i + 1; j != e; ++j) {
1669 MatchableInfo &A = *Info.Matchables[i];
1670 MatchableInfo &B = *Info.Matchables[j];
1672 if (A.CouldMatchAmiguouslyWith(B)) {
1673 errs() << "warning: ambiguous matchables:\n";
1675 errs() << "\nis incomparable with:\n";
1683 errs() << "warning: " << NumAmbiguous
1684 << " ambiguous matchables!\n";
1687 // Write the output.
1689 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1691 // Information for the class declaration.
1692 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
1693 OS << "#undef GET_ASSEMBLER_HEADER\n";
1694 OS << " // This should be included into the middle of the declaration of \n";
1695 OS << " // your subclasses implementation of TargetAsmParser.\n";
1696 OS << " unsigned ComputeAvailableFeatures(const " <<
1697 Target.getName() << "Subtarget *Subtarget) const;\n";
1698 OS << " enum MatchResultTy {\n";
1699 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n";
1700 OS << " Match_MissingFeature\n";
1702 OS << " MatchResultTy MatchInstructionImpl(const "
1703 << "SmallVectorImpl<MCParsedAsmOperand*>"
1704 << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n";
1705 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
1710 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
1711 OS << "#undef GET_REGISTER_MATCHER\n\n";
1713 // Emit the subtarget feature enumeration.
1714 EmitSubtargetFeatureFlagEnumeration(Info, OS);
1716 // Emit the function to match a register name to number.
1717 EmitMatchRegisterName(Target, AsmParser, OS);
1719 OS << "#endif // GET_REGISTER_MATCHER\n\n";
1722 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
1723 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
1725 // Generate the function that remaps for mnemonic aliases.
1726 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
1728 // Generate the unified function to convert operands into an MCInst.
1729 EmitConvertToMCInst(Target, Info.Matchables, OS);
1731 // Emit the enumeration for classes which participate in matching.
1732 EmitMatchClassEnumeration(Target, Info.Classes, OS);
1734 // Emit the routine to match token strings to their match class.
1735 EmitMatchTokenString(Target, Info.Classes, OS);
1737 // Emit the routine to classify an operand.
1738 EmitClassifyOperand(Info, OS);
1740 // Emit the subclass predicate routine.
1741 EmitIsSubclass(Target, Info.Classes, OS);
1743 // Emit the available features compute function.
1744 EmitComputeAvailableFeatures(Info, OS);
1747 size_t MaxNumOperands = 0;
1748 for (std::vector<MatchableInfo*>::const_iterator it =
1749 Info.Matchables.begin(), ie = Info.Matchables.end();
1751 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
1754 // Emit the static match table; unused classes get initalized to 0 which is
1755 // guaranteed to be InvalidMatchClass.
1757 // FIXME: We can reduce the size of this table very easily. First, we change
1758 // it so that store the kinds in separate bit-fields for each index, which
1759 // only needs to be the max width used for classes at that index (we also need
1760 // to reject based on this during classification). If we then make sure to
1761 // order the match kinds appropriately (putting mnemonics last), then we
1762 // should only end up using a few bits for each class, especially the ones
1763 // following the mnemonic.
1764 OS << "namespace {\n";
1765 OS << " struct MatchEntry {\n";
1766 OS << " unsigned Opcode;\n";
1767 OS << " const char *Mnemonic;\n";
1768 OS << " ConversionKind ConvertFn;\n";
1769 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1770 OS << " unsigned RequiredFeatures;\n";
1773 OS << "// Predicate for searching for an opcode.\n";
1774 OS << " struct LessOpcode {\n";
1775 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
1776 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
1778 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
1779 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
1781 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
1782 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
1786 OS << "} // end anonymous namespace.\n\n";
1788 OS << "static const MatchEntry MatchTable["
1789 << Info.Matchables.size() << "] = {\n";
1791 for (std::vector<MatchableInfo*>::const_iterator it =
1792 Info.Matchables.begin(), ie = Info.Matchables.end();
1794 MatchableInfo &II = **it;
1797 const CodeGenInstruction *ResultInst;
1798 if (II.DefRec.is<const CodeGenInstruction*>())
1799 ResultInst = II.DefRec.get<const CodeGenInstruction*>();
1801 ResultInst = II.DefRec.get<const CodeGenInstAlias*>()->ResultInst;
1803 OS << " { " << Target.getName() << "::" << ResultInst->TheDef->getName()
1804 << ", \"" << II.Mnemonic << "\""
1805 << ", " << II.ConversionFnKind << ", { ";
1806 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1807 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1810 OS << Op.Class->Name;
1814 // Write the required features mask.
1815 if (!II.RequiredFeatures.empty()) {
1816 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
1818 OS << II.RequiredFeatures[i]->getEnumName();
1828 // Finally, build the match function.
1829 OS << Target.getName() << ClassName << "::MatchResultTy "
1830 << Target.getName() << ClassName << "::\n"
1831 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
1833 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
1835 // Emit code to get the available features.
1836 OS << " // Get the current feature set.\n";
1837 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
1839 OS << " // Get the instruction mnemonic, which is the first token.\n";
1840 OS << " StringRef Mnemonic = ((" << Target.getName()
1841 << "Operand*)Operands[0])->getToken();\n\n";
1843 if (HasMnemonicAliases) {
1844 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
1845 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
1848 // Emit code to compute the class list for this operand vector.
1849 OS << " // Eliminate obvious mismatches.\n";
1850 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
1851 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
1852 OS << " return Match_InvalidOperand;\n";
1855 OS << " // Compute the class list for this operand vector.\n";
1856 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1857 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n";
1858 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n";
1860 OS << " // Check for invalid operands before matching.\n";
1861 OS << " if (Classes[i-1] == InvalidMatchClass) {\n";
1862 OS << " ErrorInfo = i;\n";
1863 OS << " return Match_InvalidOperand;\n";
1867 OS << " // Mark unused classes.\n";
1868 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; "
1869 << "i != e; ++i)\n";
1870 OS << " Classes[i] = InvalidMatchClass;\n\n";
1872 OS << " // Some state to try to produce better error messages.\n";
1873 OS << " bool HadMatchOtherThanFeatures = false;\n\n";
1874 OS << " // Set ErrorInfo to the operand that mismatches if it is \n";
1875 OS << " // wrong for all instances of the instruction.\n";
1876 OS << " ErrorInfo = ~0U;\n";
1878 // Emit code to search the table.
1879 OS << " // Search the table.\n";
1880 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
1881 OS << " std::equal_range(MatchTable, MatchTable+"
1882 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
1884 OS << " // Return a more specific error code if no mnemonics match.\n";
1885 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
1886 OS << " return Match_MnemonicFail;\n\n";
1888 OS << " for (const MatchEntry *it = MnemonicRange.first, "
1889 << "*ie = MnemonicRange.second;\n";
1890 OS << " it != ie; ++it) {\n";
1892 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
1893 OS << " assert(Mnemonic == it->Mnemonic);\n";
1895 // Emit check that the subclasses match.
1896 OS << " bool OperandsValid = true;\n";
1897 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
1898 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n";
1899 OS << " continue;\n";
1900 OS << " // If this operand is broken for all of the instances of this\n";
1901 OS << " // mnemonic, keep track of it so we can report loc info.\n";
1902 OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n";
1903 OS << " ErrorInfo = i+1;\n";
1905 OS << " ErrorInfo = ~0U;";
1906 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
1907 OS << " OperandsValid = false;\n";
1911 OS << " if (!OperandsValid) continue;\n";
1913 // Emit check that the required features are available.
1914 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
1915 << "!= it->RequiredFeatures) {\n";
1916 OS << " HadMatchOtherThanFeatures = true;\n";
1917 OS << " continue;\n";
1921 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
1923 // Call the post-processing function, if used.
1924 std::string InsnCleanupFn =
1925 AsmParser->getValueAsString("AsmParserInstCleanup");
1926 if (!InsnCleanupFn.empty())
1927 OS << " " << InsnCleanupFn << "(Inst);\n";
1929 OS << " return Match_Success;\n";
1932 OS << " // Okay, we had no match. Try to return a useful error code.\n";
1933 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
1934 OS << " return Match_InvalidOperand;\n";
1937 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";