1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific valeus in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "AsmMatcherEmitter.h"
100 #include "CodeGenTarget.h"
103 #include "StringMatcher.h"
104 #include "llvm/ADT/OwningPtr.h"
105 #include "llvm/ADT/PointerUnion.h"
106 #include "llvm/ADT/SmallPtrSet.h"
107 #include "llvm/ADT/SmallVector.h"
108 #include "llvm/ADT/STLExtras.h"
109 #include "llvm/ADT/StringExtras.h"
110 #include "llvm/Support/CommandLine.h"
111 #include "llvm/Support/Debug.h"
114 using namespace llvm;
116 static cl::opt<std::string>
117 MatchPrefix("match-prefix", cl::init(""),
118 cl::desc("Only match instructions with the given prefix"));
121 class AsmMatcherInfo;
122 struct SubtargetFeatureInfo;
124 /// ClassInfo - Helper class for storing the information about a particular
125 /// class of operands which can be matched.
128 /// Invalid kind, for use as a sentinel value.
131 /// The class for a particular token.
134 /// The (first) register class, subsequent register classes are
135 /// RegisterClass0+1, and so on.
138 /// The (first) user defined class, subsequent user defined classes are
139 /// UserClass0+1, and so on.
143 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
144 /// N) for the Nth user defined class.
147 /// SuperClasses - The super classes of this class. Note that for simplicities
148 /// sake user operands only record their immediate super class, while register
149 /// operands include all superclasses.
150 std::vector<ClassInfo*> SuperClasses;
152 /// Name - The full class name, suitable for use in an enum.
155 /// ClassName - The unadorned generic name for this class (e.g., Token).
156 std::string ClassName;
158 /// ValueName - The name of the value this class represents; for a token this
159 /// is the literal token string, for an operand it is the TableGen class (or
160 /// empty if this is a derived class).
161 std::string ValueName;
163 /// PredicateMethod - The name of the operand method to test whether the
164 /// operand matches this class; this is not valid for Token or register kinds.
165 std::string PredicateMethod;
167 /// RenderMethod - The name of the operand method to add this operand to an
168 /// MCInst; this is not valid for Token or register kinds.
169 std::string RenderMethod;
171 /// ParserMethod - The name of the operand method to do a target specific
172 /// parsing on the operand.
173 std::string ParserMethod;
175 /// For register classes, the records for all the registers in this class.
176 std::set<Record*> Registers;
179 /// isRegisterClass() - Check if this is a register class.
180 bool isRegisterClass() const {
181 return Kind >= RegisterClass0 && Kind < UserClass0;
184 /// isUserClass() - Check if this is a user defined class.
185 bool isUserClass() const {
186 return Kind >= UserClass0;
189 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
190 /// are related if they are in the same class hierarchy.
191 bool isRelatedTo(const ClassInfo &RHS) const {
192 // Tokens are only related to tokens.
193 if (Kind == Token || RHS.Kind == Token)
194 return Kind == Token && RHS.Kind == Token;
196 // Registers classes are only related to registers classes, and only if
197 // their intersection is non-empty.
198 if (isRegisterClass() || RHS.isRegisterClass()) {
199 if (!isRegisterClass() || !RHS.isRegisterClass())
202 std::set<Record*> Tmp;
203 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
204 std::set_intersection(Registers.begin(), Registers.end(),
205 RHS.Registers.begin(), RHS.Registers.end(),
211 // Otherwise we have two users operands; they are related if they are in the
212 // same class hierarchy.
214 // FIXME: This is an oversimplification, they should only be related if they
215 // intersect, however we don't have that information.
216 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
217 const ClassInfo *Root = this;
218 while (!Root->SuperClasses.empty())
219 Root = Root->SuperClasses.front();
221 const ClassInfo *RHSRoot = &RHS;
222 while (!RHSRoot->SuperClasses.empty())
223 RHSRoot = RHSRoot->SuperClasses.front();
225 return Root == RHSRoot;
228 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
229 bool isSubsetOf(const ClassInfo &RHS) const {
230 // This is a subset of RHS if it is the same class...
234 // ... or if any of its super classes are a subset of RHS.
235 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
236 ie = SuperClasses.end(); it != ie; ++it)
237 if ((*it)->isSubsetOf(RHS))
243 /// operator< - Compare two classes.
244 bool operator<(const ClassInfo &RHS) const {
248 // Unrelated classes can be ordered by kind.
249 if (!isRelatedTo(RHS))
250 return Kind < RHS.Kind;
254 assert(0 && "Invalid kind!");
256 // Tokens are comparable by value.
258 // FIXME: Compare by enum value.
259 return ValueName < RHS.ValueName;
262 // This class precedes the RHS if it is a proper subset of the RHS.
265 if (RHS.isSubsetOf(*this))
268 // Otherwise, order by name to ensure we have a total ordering.
269 return ValueName < RHS.ValueName;
274 /// MatchableInfo - Helper class for storing the necessary information for an
275 /// instruction or alias which is capable of being matched.
276 struct MatchableInfo {
278 /// Token - This is the token that the operand came from.
281 /// The unique class instance this operand should match.
284 /// The operand name this is, if anything.
287 /// The suboperand index within SrcOpName, or -1 for the entire operand.
290 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1) {}
293 /// ResOperand - This represents a single operand in the result instruction
294 /// generated by the match. In cases (like addressing modes) where a single
295 /// assembler operand expands to multiple MCOperands, this represents the
296 /// single assembler operand, not the MCOperand.
299 /// RenderAsmOperand - This represents an operand result that is
300 /// generated by calling the render method on the assembly operand. The
301 /// corresponding AsmOperand is specified by AsmOperandNum.
304 /// TiedOperand - This represents a result operand that is a duplicate of
305 /// a previous result operand.
308 /// ImmOperand - This represents an immediate value that is dumped into
312 /// RegOperand - This represents a fixed register that is dumped in.
317 /// This is the operand # in the AsmOperands list that this should be
319 unsigned AsmOperandNum;
321 /// TiedOperandNum - This is the (earlier) result operand that should be
323 unsigned TiedOperandNum;
325 /// ImmVal - This is the immediate value added to the instruction.
328 /// Register - This is the register record.
332 /// MINumOperands - The number of MCInst operands populated by this
334 unsigned MINumOperands;
336 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
338 X.Kind = RenderAsmOperand;
339 X.AsmOperandNum = AsmOpNum;
340 X.MINumOperands = NumOperands;
344 static ResOperand getTiedOp(unsigned TiedOperandNum) {
346 X.Kind = TiedOperand;
347 X.TiedOperandNum = TiedOperandNum;
352 static ResOperand getImmOp(int64_t Val) {
360 static ResOperand getRegOp(Record *Reg) {
369 /// TheDef - This is the definition of the instruction or InstAlias that this
370 /// matchable came from.
371 Record *const TheDef;
373 /// DefRec - This is the definition that it came from.
374 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
376 const CodeGenInstruction *getResultInst() const {
377 if (DefRec.is<const CodeGenInstruction*>())
378 return DefRec.get<const CodeGenInstruction*>();
379 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
382 /// ResOperands - This is the operand list that should be built for the result
384 std::vector<ResOperand> ResOperands;
386 /// AsmString - The assembly string for this instruction (with variants
387 /// removed), e.g. "movsx $src, $dst".
388 std::string AsmString;
390 /// Mnemonic - This is the first token of the matched instruction, its
394 /// AsmOperands - The textual operands that this instruction matches,
395 /// annotated with a class and where in the OperandList they were defined.
396 /// This directly corresponds to the tokenized AsmString after the mnemonic is
398 SmallVector<AsmOperand, 4> AsmOperands;
400 /// Predicates - The required subtarget features to match this instruction.
401 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
403 /// ConversionFnKind - The enum value which is passed to the generated
404 /// ConvertToMCInst to convert parsed operands into an MCInst for this
406 std::string ConversionFnKind;
408 MatchableInfo(const CodeGenInstruction &CGI)
409 : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) {
412 MatchableInfo(const CodeGenInstAlias *Alias)
413 : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) {
416 void Initialize(const AsmMatcherInfo &Info,
417 SmallPtrSet<Record*, 16> &SingletonRegisters);
419 /// Validate - Return true if this matchable is a valid thing to match against
420 /// and perform a bunch of validity checking.
421 bool Validate(StringRef CommentDelimiter, bool Hack) const;
423 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
424 /// register, return the Record for it, otherwise return null.
425 Record *getSingletonRegisterForAsmOperand(unsigned i,
426 const AsmMatcherInfo &Info) const;
428 /// FindAsmOperand - Find the AsmOperand with the specified name and
429 /// suboperand index.
430 int FindAsmOperand(StringRef N, int SubOpIdx) const {
431 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
432 if (N == AsmOperands[i].SrcOpName &&
433 SubOpIdx == AsmOperands[i].SubOpIdx)
438 /// FindAsmOperandNamed - Find the first AsmOperand with the specified name.
439 /// This does not check the suboperand index.
440 int FindAsmOperandNamed(StringRef N) const {
441 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
442 if (N == AsmOperands[i].SrcOpName)
447 void BuildInstructionResultOperands();
448 void BuildAliasResultOperands();
450 /// operator< - Compare two matchables.
451 bool operator<(const MatchableInfo &RHS) const {
452 // The primary comparator is the instruction mnemonic.
453 if (Mnemonic != RHS.Mnemonic)
454 return Mnemonic < RHS.Mnemonic;
456 if (AsmOperands.size() != RHS.AsmOperands.size())
457 return AsmOperands.size() < RHS.AsmOperands.size();
459 // Compare lexicographically by operand. The matcher validates that other
460 // orderings wouldn't be ambiguous using \see CouldMatchAmbiguouslyWith().
461 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
462 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
464 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
471 /// CouldMatchAmbiguouslyWith - Check whether this matchable could
472 /// ambiguously match the same set of operands as \arg RHS (without being a
473 /// strictly superior match).
474 bool CouldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
475 // The primary comparator is the instruction mnemonic.
476 if (Mnemonic != RHS.Mnemonic)
479 // The number of operands is unambiguous.
480 if (AsmOperands.size() != RHS.AsmOperands.size())
483 // Otherwise, make sure the ordering of the two instructions is unambiguous
484 // by checking that either (a) a token or operand kind discriminates them,
485 // or (b) the ordering among equivalent kinds is consistent.
487 // Tokens and operand kinds are unambiguous (assuming a correct target
489 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
490 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
491 AsmOperands[i].Class->Kind == ClassInfo::Token)
492 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
493 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
496 // Otherwise, this operand could commute if all operands are equivalent, or
497 // there is a pair of operands that compare less than and a pair that
498 // compare greater than.
499 bool HasLT = false, HasGT = false;
500 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
501 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
503 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
507 return !(HasLT ^ HasGT);
513 void TokenizeAsmString(const AsmMatcherInfo &Info);
516 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
517 /// feature which participates in instruction matching.
518 struct SubtargetFeatureInfo {
519 /// \brief The predicate record for this feature.
522 /// \brief An unique index assigned to represent this feature.
525 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
527 /// \brief The name of the enumerated constant identifying this feature.
528 std::string getEnumName() const {
529 return "Feature_" + TheDef->getName();
533 struct OperandMatchEntry {
534 unsigned OperandMask;
538 static OperandMatchEntry Create(MatchableInfo* mi, ClassInfo *ci,
541 X.OperandMask = opMask;
549 class AsmMatcherInfo {
552 RecordKeeper &Records;
554 /// The tablegen AsmParser record.
557 /// Target - The target information.
558 CodeGenTarget &Target;
560 /// The AsmParser "RegisterPrefix" value.
561 std::string RegisterPrefix;
563 /// The classes which are needed for matching.
564 std::vector<ClassInfo*> Classes;
566 /// The information on the matchables to match.
567 std::vector<MatchableInfo*> Matchables;
569 /// Info for custom matching operands by user defined methods.
570 std::vector<OperandMatchEntry> OperandMatchInfo;
572 /// Map of Register records to their class information.
573 std::map<Record*, ClassInfo*> RegisterClasses;
575 /// Map of Predicate records to their subtarget information.
576 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
579 /// Map of token to class information which has already been constructed.
580 std::map<std::string, ClassInfo*> TokenClasses;
582 /// Map of RegisterClass records to their class information.
583 std::map<Record*, ClassInfo*> RegisterClassClasses;
585 /// Map of AsmOperandClass records to their class information.
586 std::map<Record*, ClassInfo*> AsmOperandClasses;
589 /// getTokenClass - Lookup or create the class for the given token.
590 ClassInfo *getTokenClass(StringRef Token);
592 /// getOperandClass - Lookup or create the class for the given operand.
593 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
596 /// BuildRegisterClasses - Build the ClassInfo* instances for register
598 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
600 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
602 void BuildOperandClasses();
604 void BuildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
606 void BuildAliasOperandReference(MatchableInfo *II, StringRef OpName,
607 MatchableInfo::AsmOperand &Op);
610 AsmMatcherInfo(Record *AsmParser,
611 CodeGenTarget &Target,
612 RecordKeeper &Records);
614 /// BuildInfo - Construct the various tables used during matching.
617 /// BuildOperandMatchInfo - Build the necessary information to handle user
618 /// defined operand parsing methods.
619 void BuildOperandMatchInfo();
621 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
623 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
624 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
625 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
626 SubtargetFeatures.find(Def);
627 return I == SubtargetFeatures.end() ? 0 : I->second;
630 RecordKeeper &getRecords() const {
637 void MatchableInfo::dump() {
638 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
640 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
641 AsmOperand &Op = AsmOperands[i];
642 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
643 errs() << '\"' << Op.Token << "\"\n";
647 void MatchableInfo::Initialize(const AsmMatcherInfo &Info,
648 SmallPtrSet<Record*, 16> &SingletonRegisters) {
649 // TODO: Eventually support asmparser for Variant != 0.
650 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0);
652 TokenizeAsmString(Info);
654 // Compute the require features.
655 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
656 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
657 if (SubtargetFeatureInfo *Feature =
658 Info.getSubtargetFeature(Predicates[i]))
659 RequiredFeatures.push_back(Feature);
661 // Collect singleton registers, if used.
662 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
663 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
664 SingletonRegisters.insert(Reg);
668 /// TokenizeAsmString - Tokenize a simplified assembly string.
669 void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) {
670 StringRef String = AsmString;
673 for (unsigned i = 0, e = String.size(); i != e; ++i) {
683 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
686 if (!isspace(String[i]) && String[i] != ',')
687 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
693 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
697 assert(i != String.size() && "Invalid quoted character");
698 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
704 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
708 // If this isn't "${", treat like a normal token.
709 if (i + 1 == String.size() || String[i + 1] != '{') {
714 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
715 assert(End != String.end() && "Missing brace in operand reference!");
716 size_t EndPos = End - String.begin();
717 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
725 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
734 if (InTok && Prev != String.size())
735 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
737 // The first token of the instruction is the mnemonic, which must be a
738 // simple string, not a $foo variable or a singleton register.
739 assert(!AsmOperands.empty() && "Instruction has no tokens?");
740 Mnemonic = AsmOperands[0].Token;
741 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info))
742 throw TGError(TheDef->getLoc(),
743 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
745 // Remove the first operand, it is tracked in the mnemonic field.
746 AsmOperands.erase(AsmOperands.begin());
749 bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const {
750 // Reject matchables with no .s string.
751 if (AsmString.empty())
752 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
754 // Reject any matchables with a newline in them, they should be marked
755 // isCodeGenOnly if they are pseudo instructions.
756 if (AsmString.find('\n') != std::string::npos)
757 throw TGError(TheDef->getLoc(),
758 "multiline instruction is not valid for the asmparser, "
759 "mark it isCodeGenOnly");
761 // Remove comments from the asm string. We know that the asmstring only
763 if (!CommentDelimiter.empty() &&
764 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
765 throw TGError(TheDef->getLoc(),
766 "asmstring for instruction has comment character in it, "
767 "mark it isCodeGenOnly");
769 // Reject matchables with operand modifiers, these aren't something we can
770 // handle, the target should be refactored to use operands instead of
773 // Also, check for instructions which reference the operand multiple times;
774 // this implies a constraint we would not honor.
775 std::set<std::string> OperandNames;
776 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
777 StringRef Tok = AsmOperands[i].Token;
778 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
779 throw TGError(TheDef->getLoc(),
780 "matchable with operand modifier '" + Tok.str() +
781 "' not supported by asm matcher. Mark isCodeGenOnly!");
783 // Verify that any operand is only mentioned once.
784 // We reject aliases and ignore instructions for now.
785 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
787 throw TGError(TheDef->getLoc(),
788 "ERROR: matchable with tied operand '" + Tok.str() +
789 "' can never be matched!");
790 // FIXME: Should reject these. The ARM backend hits this with $lane in a
791 // bunch of instructions. It is unclear what the right answer is.
793 errs() << "warning: '" << TheDef->getName() << "': "
794 << "ignoring instruction with tied operand '"
795 << Tok.str() << "'\n";
804 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
805 /// register, return the register name, otherwise return a null StringRef.
806 Record *MatchableInfo::
807 getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{
808 StringRef Tok = AsmOperands[i].Token;
809 if (!Tok.startswith(Info.RegisterPrefix))
812 StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
813 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
816 // If there is no register prefix (i.e. "%" in "%eax"), then this may
817 // be some random non-register token, just ignore it.
818 if (Info.RegisterPrefix.empty())
821 // Otherwise, we have something invalid prefixed with the register prefix,
823 std::string Err = "unable to find register for '" + RegName.str() +
824 "' (which matches register prefix)";
825 throw TGError(TheDef->getLoc(), Err);
828 static std::string getEnumNameForToken(StringRef Str) {
831 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
833 case '*': Res += "_STAR_"; break;
834 case '%': Res += "_PCT_"; break;
835 case ':': Res += "_COLON_"; break;
836 case '!': Res += "_EXCLAIM_"; break;
837 case '.': Res += "_DOT_"; break;
842 Res += "_" + utostr((unsigned) *it) + "_";
849 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
850 ClassInfo *&Entry = TokenClasses[Token];
853 Entry = new ClassInfo();
854 Entry->Kind = ClassInfo::Token;
855 Entry->ClassName = "Token";
856 Entry->Name = "MCK_" + getEnumNameForToken(Token);
857 Entry->ValueName = Token;
858 Entry->PredicateMethod = "<invalid>";
859 Entry->RenderMethod = "<invalid>";
860 Entry->ParserMethod = "";
861 Classes.push_back(Entry);
868 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
870 Record *Rec = OI.Rec;
872 Rec = dynamic_cast<DefInit*>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
874 if (Rec->isSubClassOf("RegisterClass")) {
875 if (ClassInfo *CI = RegisterClassClasses[Rec])
877 throw TGError(Rec->getLoc(), "register class has no class info!");
880 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
881 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
882 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
885 throw TGError(Rec->getLoc(), "operand has no match class!");
888 void AsmMatcherInfo::
889 BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
890 const std::vector<CodeGenRegister*> &Registers =
891 Target.getRegBank().getRegisters();
892 const std::vector<CodeGenRegisterClass> &RegClassList =
893 Target.getRegisterClasses();
895 // The register sets used for matching.
896 std::set< std::set<Record*> > RegisterSets;
898 // Gather the defined sets.
899 for (std::vector<CodeGenRegisterClass>::const_iterator it =
900 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
901 RegisterSets.insert(std::set<Record*>(it->getOrder().begin(),
902 it->getOrder().end()));
904 // Add any required singleton sets.
905 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
906 ie = SingletonRegisters.end(); it != ie; ++it) {
908 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
911 // Introduce derived sets where necessary (when a register does not determine
912 // a unique register set class), and build the mapping of registers to the set
913 // they should classify to.
914 std::map<Record*, std::set<Record*> > RegisterMap;
915 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
916 ie = Registers.end(); it != ie; ++it) {
917 const CodeGenRegister &CGR = **it;
918 // Compute the intersection of all sets containing this register.
919 std::set<Record*> ContainingSet;
921 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
922 ie = RegisterSets.end(); it != ie; ++it) {
923 if (!it->count(CGR.TheDef))
926 if (ContainingSet.empty()) {
931 std::set<Record*> Tmp;
932 std::swap(Tmp, ContainingSet);
933 std::insert_iterator< std::set<Record*> > II(ContainingSet,
934 ContainingSet.begin());
935 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
938 if (!ContainingSet.empty()) {
939 RegisterSets.insert(ContainingSet);
940 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
944 // Construct the register classes.
945 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
947 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
948 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
949 ClassInfo *CI = new ClassInfo();
950 CI->Kind = ClassInfo::RegisterClass0 + Index;
951 CI->ClassName = "Reg" + utostr(Index);
952 CI->Name = "MCK_Reg" + utostr(Index);
954 CI->PredicateMethod = ""; // unused
955 CI->RenderMethod = "addRegOperands";
957 Classes.push_back(CI);
958 RegisterSetClasses.insert(std::make_pair(*it, CI));
961 // Find the superclasses; we could compute only the subgroup lattice edges,
962 // but there isn't really a point.
963 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
964 ie = RegisterSets.end(); it != ie; ++it) {
965 ClassInfo *CI = RegisterSetClasses[*it];
966 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
967 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
969 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
970 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
973 // Name the register classes which correspond to a user defined RegisterClass.
974 for (std::vector<CodeGenRegisterClass>::const_iterator
975 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
976 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->getOrder().begin(),
977 it->getOrder().end())];
978 if (CI->ValueName.empty()) {
979 CI->ClassName = it->getName();
980 CI->Name = "MCK_" + it->getName();
981 CI->ValueName = it->getName();
983 CI->ValueName = CI->ValueName + "," + it->getName();
985 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
988 // Populate the map for individual registers.
989 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
990 ie = RegisterMap.end(); it != ie; ++it)
991 RegisterClasses[it->first] = RegisterSetClasses[it->second];
993 // Name the register classes which correspond to singleton registers.
994 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
995 ie = SingletonRegisters.end(); it != ie; ++it) {
997 ClassInfo *CI = RegisterClasses[Rec];
998 assert(CI && "Missing singleton register class info!");
1000 if (CI->ValueName.empty()) {
1001 CI->ClassName = Rec->getName();
1002 CI->Name = "MCK_" + Rec->getName();
1003 CI->ValueName = Rec->getName();
1005 CI->ValueName = CI->ValueName + "," + Rec->getName();
1009 void AsmMatcherInfo::BuildOperandClasses() {
1010 std::vector<Record*> AsmOperands =
1011 Records.getAllDerivedDefinitions("AsmOperandClass");
1013 // Pre-populate AsmOperandClasses map.
1014 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1015 ie = AsmOperands.end(); it != ie; ++it)
1016 AsmOperandClasses[*it] = new ClassInfo();
1019 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1020 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
1021 ClassInfo *CI = AsmOperandClasses[*it];
1022 CI->Kind = ClassInfo::UserClass0 + Index;
1024 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
1025 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1026 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
1028 PrintError((*it)->getLoc(), "Invalid super class reference!");
1032 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1034 PrintError((*it)->getLoc(), "Invalid super class reference!");
1036 CI->SuperClasses.push_back(SC);
1038 CI->ClassName = (*it)->getValueAsString("Name");
1039 CI->Name = "MCK_" + CI->ClassName;
1040 CI->ValueName = (*it)->getName();
1042 // Get or construct the predicate method name.
1043 Init *PMName = (*it)->getValueInit("PredicateMethod");
1044 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
1045 CI->PredicateMethod = SI->getValue();
1047 assert(dynamic_cast<UnsetInit*>(PMName) &&
1048 "Unexpected PredicateMethod field!");
1049 CI->PredicateMethod = "is" + CI->ClassName;
1052 // Get or construct the render method name.
1053 Init *RMName = (*it)->getValueInit("RenderMethod");
1054 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
1055 CI->RenderMethod = SI->getValue();
1057 assert(dynamic_cast<UnsetInit*>(RMName) &&
1058 "Unexpected RenderMethod field!");
1059 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1062 // Get the parse method name or leave it as empty.
1063 Init *PRMName = (*it)->getValueInit("ParserMethod");
1064 if (StringInit *SI = dynamic_cast<StringInit*>(PRMName))
1065 CI->ParserMethod = SI->getValue();
1067 AsmOperandClasses[*it] = CI;
1068 Classes.push_back(CI);
1072 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1073 CodeGenTarget &target,
1074 RecordKeeper &records)
1075 : Records(records), AsmParser(asmParser), Target(target),
1076 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
1079 /// BuildOperandMatchInfo - Build the necessary information to handle user
1080 /// defined operand parsing methods.
1081 void AsmMatcherInfo::BuildOperandMatchInfo() {
1083 /// Map containing a mask with all operands indicies that can be found for
1084 /// that class inside a instruction.
1085 std::map<ClassInfo*, unsigned> OpClassMask;
1087 for (std::vector<MatchableInfo*>::const_iterator it =
1088 Matchables.begin(), ie = Matchables.end();
1090 MatchableInfo &II = **it;
1091 OpClassMask.clear();
1093 // Keep track of all operands of this instructions which belong to the
1095 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1096 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1097 if (Op.Class->ParserMethod.empty())
1099 unsigned &OperandMask = OpClassMask[Op.Class];
1100 OperandMask |= (1 << i);
1103 // Generate operand match info for each mnemonic/operand class pair.
1104 for (std::map<ClassInfo*, unsigned>::iterator iit = OpClassMask.begin(),
1105 iie = OpClassMask.end(); iit != iie; ++iit) {
1106 unsigned OpMask = iit->second;
1107 ClassInfo *CI = iit->first;
1108 OperandMatchInfo.push_back(OperandMatchEntry::Create(&II, CI, OpMask));
1113 void AsmMatcherInfo::BuildInfo() {
1114 // Build information about all of the AssemblerPredicates.
1115 std::vector<Record*> AllPredicates =
1116 Records.getAllDerivedDefinitions("Predicate");
1117 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1118 Record *Pred = AllPredicates[i];
1119 // Ignore predicates that are not intended for the assembler.
1120 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1123 if (Pred->getName().empty())
1124 throw TGError(Pred->getLoc(), "Predicate has no name!");
1126 unsigned FeatureNo = SubtargetFeatures.size();
1127 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1128 assert(FeatureNo < 32 && "Too many subtarget features!");
1131 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
1133 // Parse the instructions; we need to do this first so that we can gather the
1134 // singleton register classes.
1135 SmallPtrSet<Record*, 16> SingletonRegisters;
1136 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1137 E = Target.inst_end(); I != E; ++I) {
1138 const CodeGenInstruction &CGI = **I;
1140 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1141 // filter the set of instructions we consider.
1142 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1145 // Ignore "codegen only" instructions.
1146 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1149 // Validate the operand list to ensure we can handle this instruction.
1150 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1151 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1153 // Validate tied operands.
1154 if (OI.getTiedRegister() != -1) {
1155 // If we have a tied operand that consists of multiple MCOperands,
1156 // reject it. We reject aliases and ignore instructions for now.
1157 if (OI.MINumOperands != 1) {
1158 // FIXME: Should reject these. The ARM backend hits this with $lane
1159 // in a bunch of instructions. It is unclear what the right answer is.
1161 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1162 << "ignoring instruction with multi-operand tied operand '"
1163 << OI.Name << "'\n";
1170 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1172 II->Initialize(*this, SingletonRegisters);
1174 // Ignore instructions which shouldn't be matched and diagnose invalid
1175 // instruction definitions with an error.
1176 if (!II->Validate(CommentDelimiter, true))
1179 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1181 // FIXME: This is a total hack.
1182 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1183 StringRef(II->TheDef->getName()).endswith("_Int"))
1186 Matchables.push_back(II.take());
1189 // Parse all of the InstAlias definitions and stick them in the list of
1191 std::vector<Record*> AllInstAliases =
1192 Records.getAllDerivedDefinitions("InstAlias");
1193 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1194 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1196 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1197 // filter the set of instruction aliases we consider, based on the target
1199 if (!StringRef(Alias->ResultInst->TheDef->getName()).startswith(
1203 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1205 II->Initialize(*this, SingletonRegisters);
1207 // Validate the alias definitions.
1208 II->Validate(CommentDelimiter, false);
1210 Matchables.push_back(II.take());
1213 // Build info for the register classes.
1214 BuildRegisterClasses(SingletonRegisters);
1216 // Build info for the user defined assembly operand classes.
1217 BuildOperandClasses();
1219 // Build the information about matchables, now that we have fully formed
1221 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1222 ie = Matchables.end(); it != ie; ++it) {
1223 MatchableInfo *II = *it;
1225 // Parse the tokens after the mnemonic.
1226 // Note: BuildInstructionOperandReference may insert new AsmOperands, so
1227 // don't precompute the loop bound.
1228 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1229 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1230 StringRef Token = Op.Token;
1232 // Check for singleton registers.
1233 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) {
1234 Op.Class = RegisterClasses[RegRecord];
1235 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1236 "Unexpected class for singleton register");
1240 // Check for simple tokens.
1241 if (Token[0] != '$') {
1242 Op.Class = getTokenClass(Token);
1246 if (Token.size() > 1 && isdigit(Token[1])) {
1247 Op.Class = getTokenClass(Token);
1251 // Otherwise this is an operand reference.
1252 StringRef OperandName;
1253 if (Token[1] == '{')
1254 OperandName = Token.substr(2, Token.size() - 3);
1256 OperandName = Token.substr(1);
1258 if (II->DefRec.is<const CodeGenInstruction*>())
1259 BuildInstructionOperandReference(II, OperandName, i);
1261 BuildAliasOperandReference(II, OperandName, Op);
1264 if (II->DefRec.is<const CodeGenInstruction*>())
1265 II->BuildInstructionResultOperands();
1267 II->BuildAliasResultOperands();
1270 // Reorder classes so that classes precede super classes.
1271 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1274 /// BuildInstructionOperandReference - The specified operand is a reference to a
1275 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1276 void AsmMatcherInfo::
1277 BuildInstructionOperandReference(MatchableInfo *II,
1278 StringRef OperandName,
1279 unsigned AsmOpIdx) {
1280 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1281 const CGIOperandList &Operands = CGI.Operands;
1282 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1284 // Map this token to an operand.
1286 if (!Operands.hasOperandNamed(OperandName, Idx))
1287 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1288 OperandName.str() + "'");
1290 // If the instruction operand has multiple suboperands, but the parser
1291 // match class for the asm operand is still the default "ImmAsmOperand",
1292 // then handle each suboperand separately.
1293 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1294 Record *Rec = Operands[Idx].Rec;
1295 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1296 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1297 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1298 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1299 StringRef Token = Op->Token; // save this in case Op gets moved
1300 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1301 MatchableInfo::AsmOperand NewAsmOp(Token);
1302 NewAsmOp.SubOpIdx = SI;
1303 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1305 // Replace Op with first suboperand.
1306 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1311 // Set up the operand class.
1312 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1314 // If the named operand is tied, canonicalize it to the untied operand.
1315 // For example, something like:
1316 // (outs GPR:$dst), (ins GPR:$src)
1317 // with an asmstring of
1319 // we want to canonicalize to:
1321 // so that we know how to provide the $dst operand when filling in the result.
1322 int OITied = Operands[Idx].getTiedRegister();
1324 // The tied operand index is an MIOperand index, find the operand that
1326 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1327 OperandName = Operands[Idx.first].Name;
1328 Op->SubOpIdx = Idx.second;
1331 Op->SrcOpName = OperandName;
1334 /// BuildAliasOperandReference - When parsing an operand reference out of the
1335 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1336 /// operand reference is by looking it up in the result pattern definition.
1337 void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II,
1338 StringRef OperandName,
1339 MatchableInfo::AsmOperand &Op) {
1340 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1342 // Set up the operand class.
1343 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1344 if (CGA.ResultOperands[i].isRecord() &&
1345 CGA.ResultOperands[i].getName() == OperandName) {
1346 // It's safe to go with the first one we find, because CodeGenInstAlias
1347 // validates that all operands with the same name have the same record.
1348 unsigned ResultIdx = CGA.ResultInstOperandIndex[i].first;
1349 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1350 Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx],
1352 Op.SrcOpName = OperandName;
1356 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1357 OperandName.str() + "'");
1360 void MatchableInfo::BuildInstructionResultOperands() {
1361 const CodeGenInstruction *ResultInst = getResultInst();
1363 // Loop over all operands of the result instruction, determining how to
1365 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1366 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1368 // If this is a tied operand, just copy from the previously handled operand.
1369 int TiedOp = OpInfo.getTiedRegister();
1371 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1375 // Find out what operand from the asmparser this MCInst operand comes from.
1376 int SrcOperand = FindAsmOperandNamed(OpInfo.Name);
1377 if (OpInfo.Name.empty() || SrcOperand == -1)
1378 throw TGError(TheDef->getLoc(), "Instruction '" +
1379 TheDef->getName() + "' has operand '" + OpInfo.Name +
1380 "' that doesn't appear in asm string!");
1382 // Check if the one AsmOperand populates the entire operand.
1383 unsigned NumOperands = OpInfo.MINumOperands;
1384 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1385 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1389 // Add a separate ResOperand for each suboperand.
1390 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1391 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1392 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1393 "unexpected AsmOperands for suboperands");
1394 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1399 void MatchableInfo::BuildAliasResultOperands() {
1400 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1401 const CodeGenInstruction *ResultInst = getResultInst();
1403 // Loop over all operands of the result instruction, determining how to
1405 unsigned AliasOpNo = 0;
1406 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1407 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1408 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1410 // If this is a tied operand, just copy from the previously handled operand.
1411 int TiedOp = OpInfo->getTiedRegister();
1413 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1417 // Handle all the suboperands for this operand.
1418 const std::string &OpName = OpInfo->Name;
1419 for ( ; AliasOpNo < LastOpNo &&
1420 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1421 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1423 // Find out what operand from the asmparser that this MCInst operand
1425 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1426 default: assert(0 && "unexpected InstAlias operand kind");
1427 case CodeGenInstAlias::ResultOperand::K_Record: {
1428 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1429 int SrcOperand = FindAsmOperand(Name, SubIdx);
1430 if (SrcOperand == -1)
1431 throw TGError(TheDef->getLoc(), "Instruction '" +
1432 TheDef->getName() + "' has operand '" + OpName +
1433 "' that doesn't appear in asm string!");
1434 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1435 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1439 case CodeGenInstAlias::ResultOperand::K_Imm: {
1440 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1441 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1444 case CodeGenInstAlias::ResultOperand::K_Reg: {
1445 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1446 ResOperands.push_back(ResOperand::getRegOp(Reg));
1454 static void EmitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName,
1455 std::vector<MatchableInfo*> &Infos,
1457 // Write the convert function to a separate stream, so we can drop it after
1459 std::string ConvertFnBody;
1460 raw_string_ostream CvtOS(ConvertFnBody);
1462 // Function we have already generated.
1463 std::set<std::string> GeneratedFns;
1465 // Start the unified conversion function.
1466 CvtOS << "bool " << Target.getName() << ClassName << "::\n";
1467 CvtOS << "ConvertToMCInst(unsigned Kind, MCInst &Inst, "
1468 << "unsigned Opcode,\n"
1469 << " const SmallVectorImpl<MCParsedAsmOperand*"
1470 << "> &Operands) {\n";
1471 CvtOS << " Inst.setOpcode(Opcode);\n";
1472 CvtOS << " switch (Kind) {\n";
1473 CvtOS << " default:\n";
1475 // Start the enum, which we will generate inline.
1477 OS << "// Unified function for converting operands to MCInst instances.\n\n";
1478 OS << "enum ConversionKind {\n";
1480 // TargetOperandClass - This is the target's operand class, like X86Operand.
1481 std::string TargetOperandClass = Target.getName() + "Operand";
1483 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1484 ie = Infos.end(); it != ie; ++it) {
1485 MatchableInfo &II = **it;
1487 // Check if we have a custom match function.
1488 std::string AsmMatchConverter =
1489 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1490 if (!AsmMatchConverter.empty()) {
1491 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1492 II.ConversionFnKind = Signature;
1494 // Check if we have already generated this signature.
1495 if (!GeneratedFns.insert(Signature).second)
1498 // If not, emit it now. Add to the enum list.
1499 OS << " " << Signature << ",\n";
1501 CvtOS << " case " << Signature << ":\n";
1502 CvtOS << " return " << AsmMatchConverter
1503 << "(Inst, Opcode, Operands);\n";
1507 // Build the conversion function signature.
1508 std::string Signature = "Convert";
1509 std::string CaseBody;
1510 raw_string_ostream CaseOS(CaseBody);
1512 // Compute the convert enum and the case body.
1513 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1514 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1516 // Generate code to populate each result operand.
1517 switch (OpInfo.Kind) {
1518 case MatchableInfo::ResOperand::RenderAsmOperand: {
1519 // This comes from something we parsed.
1520 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1522 // Registers are always converted the same, don't duplicate the
1523 // conversion function based on them.
1525 if (Op.Class->isRegisterClass())
1528 Signature += Op.Class->ClassName;
1529 Signature += utostr(OpInfo.MINumOperands);
1530 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1532 CaseOS << " ((" << TargetOperandClass << "*)Operands["
1533 << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod
1534 << "(Inst, " << OpInfo.MINumOperands << ");\n";
1538 case MatchableInfo::ResOperand::TiedOperand: {
1539 // If this operand is tied to a previous one, just copy the MCInst
1540 // operand from the earlier one.We can only tie single MCOperand values.
1541 //assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1542 unsigned TiedOp = OpInfo.TiedOperandNum;
1543 assert(i > TiedOp && "Tied operand precedes its target!");
1544 CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
1545 Signature += "__Tie" + utostr(TiedOp);
1548 case MatchableInfo::ResOperand::ImmOperand: {
1549 int64_t Val = OpInfo.ImmVal;
1550 CaseOS << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n";
1551 Signature += "__imm" + itostr(Val);
1554 case MatchableInfo::ResOperand::RegOperand: {
1555 if (OpInfo.Register == 0) {
1556 CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
1557 Signature += "__reg0";
1559 std::string N = getQualifiedName(OpInfo.Register);
1560 CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n";
1561 Signature += "__reg" + OpInfo.Register->getName();
1567 II.ConversionFnKind = Signature;
1569 // Check if we have already generated this signature.
1570 if (!GeneratedFns.insert(Signature).second)
1573 // If not, emit it now. Add to the enum list.
1574 OS << " " << Signature << ",\n";
1576 CvtOS << " case " << Signature << ":\n";
1577 CvtOS << CaseOS.str();
1578 CvtOS << " return true;\n";
1581 // Finish the convert function.
1584 CvtOS << " return false;\n";
1587 // Finish the enum, and drop the convert function after it.
1589 OS << " NumConversionVariants\n";
1595 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1596 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1597 std::vector<ClassInfo*> &Infos,
1599 OS << "namespace {\n\n";
1601 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1602 << "/// instruction matching.\n";
1603 OS << "enum MatchClassKind {\n";
1604 OS << " InvalidMatchClass = 0,\n";
1605 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1606 ie = Infos.end(); it != ie; ++it) {
1607 ClassInfo &CI = **it;
1608 OS << " " << CI.Name << ", // ";
1609 if (CI.Kind == ClassInfo::Token) {
1610 OS << "'" << CI.ValueName << "'\n";
1611 } else if (CI.isRegisterClass()) {
1612 if (!CI.ValueName.empty())
1613 OS << "register class '" << CI.ValueName << "'\n";
1615 OS << "derived register class\n";
1617 OS << "user defined class '" << CI.ValueName << "'\n";
1620 OS << " NumMatchClassKinds\n";
1626 /// EmitValidateOperandClass - Emit the function to validate an operand class.
1627 static void EmitValidateOperandClass(AsmMatcherInfo &Info,
1629 OS << "static bool ValidateOperandClass(MCParsedAsmOperand *GOp, "
1630 << "MatchClassKind Kind) {\n";
1631 OS << " " << Info.Target.getName() << "Operand &Operand = *("
1632 << Info.Target.getName() << "Operand*)GOp;\n";
1634 // Check for Token operands first.
1635 OS << " if (Operand.isToken())\n";
1636 OS << " return MatchTokenString(Operand.getToken()) == Kind;\n\n";
1638 // Check for register operands, including sub-classes.
1639 OS << " if (Operand.isReg()) {\n";
1640 OS << " MatchClassKind OpKind;\n";
1641 OS << " switch (Operand.getReg()) {\n";
1642 OS << " default: OpKind = InvalidMatchClass; break;\n";
1643 for (std::map<Record*, ClassInfo*>::iterator
1644 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1646 OS << " case " << Info.Target.getName() << "::"
1647 << it->first->getName() << ": OpKind = " << it->second->Name
1650 OS << " return IsSubclass(OpKind, Kind);\n";
1653 // Check the user classes. We don't care what order since we're only
1654 // actually matching against one of them.
1655 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1656 ie = Info.Classes.end(); it != ie; ++it) {
1657 ClassInfo &CI = **it;
1659 if (!CI.isUserClass())
1662 OS << " // '" << CI.ClassName << "' class\n";
1663 OS << " if (Kind == " << CI.Name
1664 << " && Operand." << CI.PredicateMethod << "()) {\n";
1665 OS << " return true;\n";
1669 OS << " return false;\n";
1673 /// EmitIsSubclass - Emit the subclass predicate function.
1674 static void EmitIsSubclass(CodeGenTarget &Target,
1675 std::vector<ClassInfo*> &Infos,
1677 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1678 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1679 OS << " if (A == B)\n";
1680 OS << " return true;\n\n";
1682 OS << " switch (A) {\n";
1683 OS << " default:\n";
1684 OS << " return false;\n";
1685 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1686 ie = Infos.end(); it != ie; ++it) {
1687 ClassInfo &A = **it;
1689 if (A.Kind != ClassInfo::Token) {
1690 std::vector<StringRef> SuperClasses;
1691 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1692 ie = Infos.end(); it != ie; ++it) {
1693 ClassInfo &B = **it;
1695 if (&A != &B && A.isSubsetOf(B))
1696 SuperClasses.push_back(B.Name);
1699 if (SuperClasses.empty())
1702 OS << "\n case " << A.Name << ":\n";
1704 if (SuperClasses.size() == 1) {
1705 OS << " return B == " << SuperClasses.back() << ";\n";
1709 OS << " switch (B) {\n";
1710 OS << " default: return false;\n";
1711 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1712 OS << " case " << SuperClasses[i] << ": return true;\n";
1720 /// EmitMatchTokenString - Emit the function to match a token string to the
1721 /// appropriate match class value.
1722 static void EmitMatchTokenString(CodeGenTarget &Target,
1723 std::vector<ClassInfo*> &Infos,
1725 // Construct the match list.
1726 std::vector<StringMatcher::StringPair> Matches;
1727 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1728 ie = Infos.end(); it != ie; ++it) {
1729 ClassInfo &CI = **it;
1731 if (CI.Kind == ClassInfo::Token)
1732 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1733 "return " + CI.Name + ";"));
1736 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1738 StringMatcher("Name", Matches, OS).Emit();
1740 OS << " return InvalidMatchClass;\n";
1744 /// EmitMatchRegisterName - Emit the function to match a string to the target
1745 /// specific register enum.
1746 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1748 // Construct the match list.
1749 std::vector<StringMatcher::StringPair> Matches;
1750 const std::vector<CodeGenRegister*> &Regs =
1751 Target.getRegBank().getRegisters();
1752 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1753 const CodeGenRegister *Reg = Regs[i];
1754 if (Reg->TheDef->getValueAsString("AsmName").empty())
1757 Matches.push_back(StringMatcher::StringPair(
1758 Reg->TheDef->getValueAsString("AsmName"),
1759 "return " + utostr(Reg->EnumValue) + ";"));
1762 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1764 StringMatcher("Name", Matches, OS).Emit();
1766 OS << " return 0;\n";
1770 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1772 static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1774 OS << "// Flags for subtarget features that participate in "
1775 << "instruction matching.\n";
1776 OS << "enum SubtargetFeatureFlag {\n";
1777 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1778 it = Info.SubtargetFeatures.begin(),
1779 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1780 SubtargetFeatureInfo &SFI = *it->second;
1781 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1783 OS << " Feature_None = 0\n";
1787 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1788 /// available features given a subtarget.
1789 static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
1791 std::string ClassName =
1792 Info.AsmParser->getValueAsString("AsmParserClassName");
1794 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1795 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1796 << "Subtarget *Subtarget) const {\n";
1797 OS << " unsigned Features = 0;\n";
1798 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1799 it = Info.SubtargetFeatures.begin(),
1800 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1801 SubtargetFeatureInfo &SFI = *it->second;
1802 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1804 OS << " Features |= " << SFI.getEnumName() << ";\n";
1806 OS << " return Features;\n";
1810 static std::string GetAliasRequiredFeatures(Record *R,
1811 const AsmMatcherInfo &Info) {
1812 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
1814 unsigned NumFeatures = 0;
1815 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
1816 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
1819 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
1820 "' is not marked as an AssemblerPredicate!");
1825 Result += F->getEnumName();
1829 if (NumFeatures > 1)
1830 Result = '(' + Result + ')';
1834 /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
1835 /// emit a function for them and return true, otherwise return false.
1836 static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
1837 // Ignore aliases when match-prefix is set.
1838 if (!MatchPrefix.empty())
1841 std::vector<Record*> Aliases =
1842 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
1843 if (Aliases.empty()) return false;
1845 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
1846 "unsigned Features) {\n";
1848 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
1849 // iteration order of the map is stable.
1850 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
1852 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
1853 Record *R = Aliases[i];
1854 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
1857 // Process each alias a "from" mnemonic at a time, building the code executed
1858 // by the string remapper.
1859 std::vector<StringMatcher::StringPair> Cases;
1860 for (std::map<std::string, std::vector<Record*> >::iterator
1861 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
1863 const std::vector<Record*> &ToVec = I->second;
1865 // Loop through each alias and emit code that handles each case. If there
1866 // are two instructions without predicates, emit an error. If there is one,
1868 std::string MatchCode;
1869 int AliasWithNoPredicate = -1;
1871 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
1872 Record *R = ToVec[i];
1873 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
1875 // If this unconditionally matches, remember it for later and diagnose
1877 if (FeatureMask.empty()) {
1878 if (AliasWithNoPredicate != -1) {
1879 // We can't have two aliases from the same mnemonic with no predicate.
1880 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
1881 "two MnemonicAliases with the same 'from' mnemonic!");
1882 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
1885 AliasWithNoPredicate = i;
1888 if (R->getValueAsString("ToMnemonic") == I->first)
1889 throw TGError(R->getLoc(), "MnemonicAlias to the same string");
1891 if (!MatchCode.empty())
1892 MatchCode += "else ";
1893 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
1894 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
1897 if (AliasWithNoPredicate != -1) {
1898 Record *R = ToVec[AliasWithNoPredicate];
1899 if (!MatchCode.empty())
1900 MatchCode += "else\n ";
1901 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
1904 MatchCode += "return;";
1906 Cases.push_back(std::make_pair(I->first, MatchCode));
1909 StringMatcher("Mnemonic", Cases, OS).Emit();
1915 static void EmitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
1916 const AsmMatcherInfo &Info, StringRef ClassName) {
1917 // Emit the static custom operand parsing table;
1918 OS << "namespace {\n";
1919 OS << " struct OperandMatchEntry {\n";
1920 OS << " const char *Mnemonic;\n";
1921 OS << " unsigned OperandMask;\n";
1922 OS << " MatchClassKind Class;\n";
1923 OS << " unsigned RequiredFeatures;\n";
1926 OS << " // Predicate for searching for an opcode.\n";
1927 OS << " struct LessOpcodeOperand {\n";
1928 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
1929 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
1931 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
1932 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
1934 OS << " bool operator()(const OperandMatchEntry &LHS,";
1935 OS << " const OperandMatchEntry &RHS) {\n";
1936 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
1940 OS << "} // end anonymous namespace.\n\n";
1942 OS << "static const OperandMatchEntry OperandMatchTable["
1943 << Info.OperandMatchInfo.size() << "] = {\n";
1945 OS << " /* Mnemonic, Operand List Mask, Operand Class, Features */\n";
1946 for (std::vector<OperandMatchEntry>::const_iterator it =
1947 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
1949 const OperandMatchEntry &OMI = *it;
1950 const MatchableInfo &II = *OMI.MI;
1952 OS << " { \"" << II.Mnemonic << "\""
1953 << ", " << OMI.OperandMask;
1956 bool printComma = false;
1957 for (int i = 0, e = 31; i !=e; ++i)
1958 if (OMI.OperandMask & (1 << i)) {
1966 OS << ", " << OMI.CI->Name
1969 // Write the required features mask.
1970 if (!II.RequiredFeatures.empty()) {
1971 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
1973 OS << II.RequiredFeatures[i]->getEnumName();
1981 // Emit the operand class switch to call the correct custom parser for
1982 // the found operand class.
1983 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
1984 << Target.getName() << ClassName << "::\n"
1985 << "TryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
1986 << " &Operands,\n unsigned MCK) {\n\n"
1987 << " switch(MCK) {\n";
1989 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
1990 ie = Info.Classes.end(); it != ie; ++it) {
1991 ClassInfo *CI = *it;
1992 if (CI->ParserMethod.empty())
1994 OS << " case " << CI->Name << ":\n"
1995 << " return " << CI->ParserMethod << "(Operands);\n";
1998 OS << " default:\n";
1999 OS << " return MatchOperand_NoMatch;\n";
2001 OS << " return MatchOperand_NoMatch;\n";
2004 // Emit the static custom operand parser. This code is very similar with
2005 // the other matcher. Also use MatchResultTy here just in case we go for
2006 // a better error handling.
2007 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2008 << Target.getName() << ClassName << "::\n"
2009 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
2010 << " &Operands,\n StringRef Mnemonic) {\n";
2012 // Emit code to get the available features.
2013 OS << " // Get the current feature set.\n";
2014 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2016 OS << " // Get the next operand index.\n";
2017 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2019 // Emit code to search the table.
2020 OS << " // Search the table.\n";
2021 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2022 OS << " MnemonicRange =\n";
2023 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2024 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2025 << " LessOpcodeOperand());\n\n";
2027 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2028 OS << " return MatchOperand_NoMatch;\n\n";
2030 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2031 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2033 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2034 OS << " assert(Mnemonic == it->Mnemonic);\n\n";
2036 // Emit check that the required features are available.
2037 OS << " // check if the available features match\n";
2038 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2039 << "!= it->RequiredFeatures) {\n";
2040 OS << " continue;\n";
2043 // Emit check to ensure the operand number matches.
2044 OS << " // check if the operand in question has a custom parser.\n";
2045 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2046 OS << " continue;\n\n";
2048 // Emit call to the custom parser method
2049 OS << " // call custom parse method to handle the operand\n";
2050 OS << " OperandMatchResultTy Result = ";
2051 OS << "TryCustomParseOperand(Operands, it->Class);\n";
2052 OS << " if (Result != MatchOperand_NoMatch)\n";
2053 OS << " return Result;\n";
2056 OS << " // Okay, we had no match.\n";
2057 OS << " return MatchOperand_NoMatch;\n";
2061 void AsmMatcherEmitter::run(raw_ostream &OS) {
2062 CodeGenTarget Target(Records);
2063 Record *AsmParser = Target.getAsmParser();
2064 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2066 // Compute the information on the instructions to match.
2067 AsmMatcherInfo Info(AsmParser, Target, Records);
2070 // Sort the instruction table using the partial order on classes. We use
2071 // stable_sort to ensure that ambiguous instructions are still
2072 // deterministically ordered.
2073 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2074 less_ptr<MatchableInfo>());
2076 DEBUG_WITH_TYPE("instruction_info", {
2077 for (std::vector<MatchableInfo*>::iterator
2078 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2083 // Check for ambiguous matchables.
2084 DEBUG_WITH_TYPE("ambiguous_instrs", {
2085 unsigned NumAmbiguous = 0;
2086 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2087 for (unsigned j = i + 1; j != e; ++j) {
2088 MatchableInfo &A = *Info.Matchables[i];
2089 MatchableInfo &B = *Info.Matchables[j];
2091 if (A.CouldMatchAmbiguouslyWith(B)) {
2092 errs() << "warning: ambiguous matchables:\n";
2094 errs() << "\nis incomparable with:\n";
2102 errs() << "warning: " << NumAmbiguous
2103 << " ambiguous matchables!\n";
2106 // Compute the information on the custom operand parsing.
2107 Info.BuildOperandMatchInfo();
2109 // Write the output.
2111 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
2113 // Information for the class declaration.
2114 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2115 OS << "#undef GET_ASSEMBLER_HEADER\n";
2116 OS << " // This should be included into the middle of the declaration of\n";
2117 OS << " // your subclasses implementation of TargetAsmParser.\n";
2118 OS << " unsigned ComputeAvailableFeatures(const " <<
2119 Target.getName() << "Subtarget *Subtarget) const;\n";
2120 OS << " enum MatchResultTy {\n";
2121 OS << " Match_ConversionFail,\n";
2122 OS << " Match_InvalidOperand,\n";
2123 OS << " Match_MissingFeature,\n";
2124 OS << " Match_MnemonicFail,\n";
2125 OS << " Match_Success\n";
2127 OS << " bool ConvertToMCInst(unsigned Kind, MCInst &Inst, "
2128 << "unsigned Opcode,\n"
2129 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2131 OS << " bool MnemonicIsValid(StringRef Mnemonic);\n";
2132 OS << " MatchResultTy MatchInstructionImpl(\n";
2133 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2134 OS << " MCInst &Inst, unsigned &ErrorInfo);\n";
2136 if (Info.OperandMatchInfo.size()) {
2137 OS << "\n enum OperandMatchResultTy {\n";
2138 OS << " MatchOperand_Success, // operand matched successfully\n";
2139 OS << " MatchOperand_NoMatch, // operand did not match\n";
2140 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2142 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2143 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2144 OS << " StringRef Mnemonic);\n";
2146 OS << " OperandMatchResultTy TryCustomParseOperand(\n";
2147 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2148 OS << " unsigned MCK);\n\n";
2151 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2153 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2154 OS << "#undef GET_REGISTER_MATCHER\n\n";
2156 // Emit the subtarget feature enumeration.
2157 EmitSubtargetFeatureFlagEnumeration(Info, OS);
2159 // Emit the function to match a register name to number.
2160 EmitMatchRegisterName(Target, AsmParser, OS);
2162 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2165 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2166 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2168 // Generate the function that remaps for mnemonic aliases.
2169 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
2171 // Generate the unified function to convert operands into an MCInst.
2172 EmitConvertToMCInst(Target, ClassName, Info.Matchables, OS);
2174 // Emit the enumeration for classes which participate in matching.
2175 EmitMatchClassEnumeration(Target, Info.Classes, OS);
2177 // Emit the routine to match token strings to their match class.
2178 EmitMatchTokenString(Target, Info.Classes, OS);
2180 // Emit the subclass predicate routine.
2181 EmitIsSubclass(Target, Info.Classes, OS);
2183 // Emit the routine to validate an operand against a match class.
2184 EmitValidateOperandClass(Info, OS);
2186 // Emit the available features compute function.
2187 EmitComputeAvailableFeatures(Info, OS);
2190 size_t MaxNumOperands = 0;
2191 for (std::vector<MatchableInfo*>::const_iterator it =
2192 Info.Matchables.begin(), ie = Info.Matchables.end();
2194 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
2196 // Emit the static match table; unused classes get initalized to 0 which is
2197 // guaranteed to be InvalidMatchClass.
2199 // FIXME: We can reduce the size of this table very easily. First, we change
2200 // it so that store the kinds in separate bit-fields for each index, which
2201 // only needs to be the max width used for classes at that index (we also need
2202 // to reject based on this during classification). If we then make sure to
2203 // order the match kinds appropriately (putting mnemonics last), then we
2204 // should only end up using a few bits for each class, especially the ones
2205 // following the mnemonic.
2206 OS << "namespace {\n";
2207 OS << " struct MatchEntry {\n";
2208 OS << " unsigned Opcode;\n";
2209 OS << " const char *Mnemonic;\n";
2210 OS << " ConversionKind ConvertFn;\n";
2211 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
2212 OS << " unsigned RequiredFeatures;\n";
2215 OS << " // Predicate for searching for an opcode.\n";
2216 OS << " struct LessOpcode {\n";
2217 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2218 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
2220 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2221 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
2223 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2224 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
2228 OS << "} // end anonymous namespace.\n\n";
2230 OS << "static const MatchEntry MatchTable["
2231 << Info.Matchables.size() << "] = {\n";
2233 for (std::vector<MatchableInfo*>::const_iterator it =
2234 Info.Matchables.begin(), ie = Info.Matchables.end();
2236 MatchableInfo &II = **it;
2238 OS << " { " << Target.getName() << "::"
2239 << II.getResultInst()->TheDef->getName() << ", \"" << II.Mnemonic << "\""
2240 << ", " << II.ConversionFnKind << ", { ";
2241 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2242 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2245 OS << Op.Class->Name;
2249 // Write the required features mask.
2250 if (!II.RequiredFeatures.empty()) {
2251 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2253 OS << II.RequiredFeatures[i]->getEnumName();
2263 // A method to determine if a mnemonic is in the list.
2264 OS << "bool " << Target.getName() << ClassName << "::\n"
2265 << "MnemonicIsValid(StringRef Mnemonic) {\n";
2266 OS << " // Search the table.\n";
2267 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2268 OS << " std::equal_range(MatchTable, MatchTable+"
2269 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n";
2270 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2273 // Finally, build the match function.
2274 OS << Target.getName() << ClassName << "::MatchResultTy "
2275 << Target.getName() << ClassName << "::\n"
2276 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2278 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
2280 // Emit code to get the available features.
2281 OS << " // Get the current feature set.\n";
2282 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2284 OS << " // Get the instruction mnemonic, which is the first token.\n";
2285 OS << " StringRef Mnemonic = ((" << Target.getName()
2286 << "Operand*)Operands[0])->getToken();\n\n";
2288 if (HasMnemonicAliases) {
2289 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2290 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
2293 // Emit code to compute the class list for this operand vector.
2294 OS << " // Eliminate obvious mismatches.\n";
2295 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2296 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2297 OS << " return Match_InvalidOperand;\n";
2300 OS << " // Some state to try to produce better error messages.\n";
2301 OS << " bool HadMatchOtherThanFeatures = false;\n\n";
2302 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2303 OS << " // wrong for all instances of the instruction.\n";
2304 OS << " ErrorInfo = ~0U;\n";
2306 // Emit code to search the table.
2307 OS << " // Search the table.\n";
2308 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2309 OS << " std::equal_range(MatchTable, MatchTable+"
2310 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
2312 OS << " // Return a more specific error code if no mnemonics match.\n";
2313 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2314 OS << " return Match_MnemonicFail;\n\n";
2316 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2317 << "*ie = MnemonicRange.second;\n";
2318 OS << " it != ie; ++it) {\n";
2320 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2321 OS << " assert(Mnemonic == it->Mnemonic);\n";
2323 // Emit check that the subclasses match.
2324 OS << " bool OperandsValid = true;\n";
2325 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2326 OS << " if (i + 1 >= Operands.size()) {\n";
2327 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2330 OS << " if (ValidateOperandClass(Operands[i+1], it->Classes[i]))\n";
2331 OS << " continue;\n";
2332 OS << " // If this operand is broken for all of the instances of this\n";
2333 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2334 OS << " if (it == MnemonicRange.first || ErrorInfo <= i+1)\n";
2335 OS << " ErrorInfo = i+1;\n";
2336 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2337 OS << " OperandsValid = false;\n";
2341 OS << " if (!OperandsValid) continue;\n";
2343 // Emit check that the required features are available.
2344 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2345 << "!= it->RequiredFeatures) {\n";
2346 OS << " HadMatchOtherThanFeatures = true;\n";
2347 OS << " continue;\n";
2350 OS << " // We have selected a definite instruction, convert the parsed\n"
2351 << " // operands into the appropriate MCInst.\n";
2352 OS << " if (!ConvertToMCInst(it->ConvertFn, Inst,\n"
2353 << " it->Opcode, Operands))\n";
2354 OS << " return Match_ConversionFail;\n";
2357 // Call the post-processing function, if used.
2358 std::string InsnCleanupFn =
2359 AsmParser->getValueAsString("AsmParserInstCleanup");
2360 if (!InsnCleanupFn.empty())
2361 OS << " " << InsnCleanupFn << "(Inst);\n";
2363 OS << " return Match_Success;\n";
2366 OS << " // Okay, we had no match. Try to return a useful error code.\n";
2367 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
2368 OS << " return Match_InvalidOperand;\n";
2371 if (Info.OperandMatchInfo.size())
2372 EmitCustomOperandParsing(OS, Target, Info, ClassName);
2374 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";