test/TableGen/TargetInstrSpec.td

   1 // RUN: llvm-tblgen %s | FileCheck %s
   2 // XFAIL: vg_leak
   3
   4 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
   5 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
   6
   7 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
   8 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
   9
  10 class ValueType<int size, int value> {
  11   int Size = size;
  12   int Value = value;
  13 }
  14
  15 def v2i64  : ValueType<128, 22>;   //  2 x i64 vector value
  16 def v2f64  : ValueType<128, 28>;   //  2 x f64 vector value
  17
  18 class Intrinsic<string name> {
  19   string Name = name;
  20 }
  21
  22 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
  23            list<dag> pattern> {
  24   bits<8> Opcode = opcode;
  25   dag OutOperands = oopnds;
  26   dag InOperands = iopnds;
  27   string AssemblyString = asmstr;
  28   list<dag> Pattern = pattern;
  29 }
  30
  31 def ops;
  32 def outs;
  33 def ins;
  34
  35 def set;
  36
  37 // Define registers
  38 class Register<string n> {
  39   string Name = n;
  40 }
  41
  42 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
  43   list<ValueType> RegTypes = regTypes;
  44   list<Register> MemberList = regList;
  45 }
  46
  47 def XMM0: Register<"xmm0">;
  48 def XMM1: Register<"xmm1">;
  49 def XMM2: Register<"xmm2">;
  50 def XMM3: Register<"xmm3">;
  51 def XMM4: Register<"xmm4">;
  52 def XMM5: Register<"xmm5">;
  53 def XMM6: Register<"xmm6">;
  54 def XMM7: Register<"xmm7">;
  55 def XMM8:  Register<"xmm8">;
  56 def XMM9:  Register<"xmm9">;
  57 def XMM10: Register<"xmm10">;
  58 def XMM11: Register<"xmm11">;
  59 def XMM12: Register<"xmm12">;
  60 def XMM13: Register<"xmm13">;
  61 def XMM14: Register<"xmm14">;
  62 def XMM15: Register<"xmm15">;
  63
  64 def VR128 : RegisterClass<[v2i64, v2f64],
  65                           [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
  66                            XMM8, XMM9, XMM10, XMM11,
  67                            XMM12, XMM13, XMM14, XMM15]>;
  68
  69 // Dummy for subst
  70 def REGCLASS : RegisterClass<[], []>;
  71
  72 class decls {
  73   // Dummy for foreach
  74   dag pattern;
  75   int operand;
  76 }
  77
  78 def Decls : decls;
  79
  80 // Define intrinsics
  81 def int_x86_sse2_add_ps : Intrinsic<"addps">;
  82 def int_x86_sse2_add_pd : Intrinsic<"addpd">;
  83 def INTRINSIC : Intrinsic<"Dummy">;
  84
  85 multiclass arith<bits<8> opcode, string asmstr, string intr, list<dag> patterns> {
  86   def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
  87                  !strconcat(asmstr, "\t$dst, $src1, $src2"),
  88                  !foreach(Decls.pattern, patterns,
  89                           !foreach(Decls.operand, Decls.pattern,
  90                                    !subst(INTRINSIC, !cast<Intrinsic>(!subst("SUFFIX", "_ps", intr)),
  91                                           !subst(REGCLASS, VR128, Decls.operand))))>;
  92
  93   def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
  94                  !strconcat(asmstr, "\t$dst, $src1, $src2"),
  95                  !foreach(Decls.pattern, patterns,
  96                           !foreach(Decls.operand, Decls.pattern,
  97                                    !subst(INTRINSIC, !cast<Intrinsic>(!subst("SUFFIX", "_pd", intr)),
  98                                           !subst(REGCLASS, VR128, Decls.operand))))>;
  99 }
 100
 101 defm ADD : arith<0x58, "add", "int_x86_sse2_addSUFFIX",
 102                  [(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))]>;
 103