test/TableGen/MultiPat.td

   1 // RUN: llvm-tblgen %s | FileCheck %s
   2
   3 class ValueType<int size, int value> {
   4   int Size = size;
   5   int Value = value;
   6 }
   7
   8 def v2i64  : ValueType<128, 22>;   //  2 x i64 vector value
   9 def v2f64  : ValueType<128, 28>;   //  2 x f64 vector value
  10
  11 class Intrinsic<string name> {
  12   string Name = name;
  13 }
  14
  15 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
  16   dag             PatternToMatch  = patternToMatch;
  17   list<dag>       ResultInstrs    = resultInstrs;
  18 }
  19
  20 // Pat - A simple (but common) form of a pattern, which produces a simple result
  21 // not needing a full list.
  22 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
  23
  24 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
  25            list<dag> pattern> {
  26   bits<8> Opcode = opcode;
  27   dag OutOperands = oopnds;
  28   dag InOperands = iopnds;
  29   string AssemblyString = asmstr;
  30   list<dag> Pattern = pattern;
  31 }
  32
  33 def ops;
  34 def outs;
  35 def ins;
  36
  37 def set;
  38
  39 // Define registers
  40 class Register<string n> {
  41   string Name = n;
  42 }
  43
  44 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
  45   list<ValueType> RegTypes = regTypes;
  46   list<Register> MemberList = regList;
  47 }
  48
  49 def XMM0: Register<"xmm0">;
  50 def XMM1: Register<"xmm1">;
  51 def XMM2: Register<"xmm2">;
  52 def XMM3: Register<"xmm3">;
  53 def XMM4: Register<"xmm4">;
  54 def XMM5: Register<"xmm5">;
  55 def XMM6: Register<"xmm6">;
  56 def XMM7: Register<"xmm7">;
  57 def XMM8:  Register<"xmm8">;
  58 def XMM9:  Register<"xmm9">;
  59 def XMM10: Register<"xmm10">;
  60 def XMM11: Register<"xmm11">;
  61 def XMM12: Register<"xmm12">;
  62 def XMM13: Register<"xmm13">;
  63 def XMM14: Register<"xmm14">;
  64 def XMM15: Register<"xmm15">;
  65
  66 def VR128 : RegisterClass<[v2i64, v2f64],
  67                           [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
  68                            XMM8, XMM9, XMM10, XMM11,
  69                            XMM12, XMM13, XMM14, XMM15]>;
  70
  71 // Dummy for subst
  72 def REGCLASS : RegisterClass<[], []>;
  73 def MNEMONIC;
  74
  75 class decls {
  76   // Dummy for foreach
  77   dag pattern;
  78   int operand;
  79 }
  80
  81 def Decls : decls;
  82
  83 // Define intrinsics
  84 def int_x86_sse2_add_ps : Intrinsic<"addps">;
  85 def int_x86_sse2_add_pd : Intrinsic<"addpd">;
  86 def INTRINSIC : Intrinsic<"Dummy">;
  87 def bitconvert;
  88 def add;
  89
  90 class MakePatImpl<list<dag> patterns> : Pat<patterns[0], patterns[1]>;
  91 class MakePat<list<dag> patterns,
  92               string suffix,
  93               string intr> : MakePatImpl<!foreach(Decls.pattern, patterns,
  94                                                          !foreach(Decls.operand, Decls.pattern,
  95                                                                  !subst(INTRINSIC, !cast<Intrinsic>(!subst("SUFFIX", suffix, intr)),
  96                                                                  !subst(REGCLASS, VR128,
  97                                                                  !subst(MNEMONIC, set, Decls.operand)))))>;
  98
  99 class Base<bits<8> opcode, dag opnds, dag iopnds, string asmstr, Intrinsic intr,
 100            list<list<dag>> patterns>
 101       : Inst<opcode, opnds, iopnds, asmstr,
 102              !foreach(Decls.pattern, patterns[0],
 103                       !foreach(Decls.operand, Decls.pattern,
 104                                !subst(INTRINSIC, intr,
 105                                !subst(REGCLASS, VR128,
 106                                !subst(MNEMONIC, set, Decls.operand)))))>;
 107
 108 multiclass arith<bits<8> opcode, string asmstr, string intr, list<list<dag>> patterns> {
 109   def PS : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
 110                  !strconcat(asmstr, "\t$dst, $src1, $src2"), !cast<Intrinsic>(!subst("SUFFIX", "_ps", intr)), patterns>;
 111
 112   def PD : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
 113                  !strconcat(asmstr, "\t$dst, $src1, $src2"), !cast<Intrinsic>(!subst("SUFFIX", "_pd", intr)), patterns>;
 114
 115   multidef <patterns, list<dag> pats, 1> : MakePat<pats, "_ps", intr>;
 116   multidef <patterns, list<dag> pats, 1> : MakePat<pats, "_pd", intr>;
 117 }
 118
 119 defm ADD : arith<0x58, "add", "int_x86_sse2_addSUFFIX",
 120                   // rr Patterns
 121                  [[(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))],
 122                    [(set REGCLASS:$dst, (bitconvert (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))),
 123                     (MNEMONIC REGCLASS:$dst, REGCLASS:$src)],
 124                    [(set REGCLASS:$dst, (add (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))),
 125                     (MNEMONIC (add REGCLASS:$dst, REGCLASS:$src))]]>;
 126
 127 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
 128 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]