[AVX512] Extended avx512_sqrt_packed (sqrt instructions) to VL subset.
[oota-llvm.git] / test / MC / ARM / neont2-bitcount-encoding.s
1 @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
2
3 .code 16
4
5         vcnt.8  d16, d16
6         vcnt.8  q8, q8
7
8 @ CHECK: vcnt.8 d16, d16                @ encoding: [0xf0,0xff,0x20,0x05]
9 @ CHECK: vcnt.8 q8, q8                  @ encoding: [0xf0,0xff,0x60,0x05]
10
11         vclz.i8 d16, d16
12         vclz.i16        d16, d16
13         vclz.i32        d16, d16
14         vclz.i8 q8, q8
15         vclz.i16        q8, q8
16         vclz.i32        q8, q8
17
18 @ CHECK: vclz.i8        d16, d16        @ encoding: [0xf0,0xff,0xa0,0x04]
19 @ CHECK: vclz.i16       d16, d16        @ encoding: [0xf4,0xff,0xa0,0x04]
20 @ CHECK: vclz.i32       d16, d16        @ encoding: [0xf8,0xff,0xa0,0x04]
21 @ CHECK: vclz.i8        q8, q8          @ encoding: [0xf0,0xff,0xe0,0x04]
22 @ CHECK: vclz.i16       q8, q8          @ encoding: [0xf4,0xff,0xe0,0x04]
23 @ CHECK: vclz.i32       q8, q8          @ encoding: [0xf8,0xff,0xe0,0x04]
24
25         vcls.s8 d16, d16
26         vcls.s16        d16, d16
27         vcls.s32        d16, d16
28         vcls.s8 q8, q8
29         vcls.s16        q8, q8
30         vcls.s32        q8, q8
31
32 @ CHECK: vcls.s8        d16, d16        @ encoding: [0xf0,0xff,0x20,0x04]
33 @ CHECK: vcls.s16       d16, d16        @ encoding: [0xf4,0xff,0x20,0x04]
34 @ CHECK: vcls.s32       d16, d16        @ encoding: [0xf8,0xff,0x20,0x04]
35 @ CHECK: vcls.s8        q8, q8          @ encoding: [0xf0,0xff,0x60,0x04]
36 @ CHECK: vcls.s16       q8, q8          @ encoding: [0xf4,0xff,0x60,0x04]
37 @ CHECK: vcls.s32       q8, q8          @ encoding: [0xf8,0xff,0x60,0x04]
38