1 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7 ; Verify that the DAG combiner correctly folds bitwise operations across
8 ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
9 ; basic and always-safe patterns. Also test that the DAG combiner will combine
10 ; target-specific shuffle instructions where reasonable.
12 target triple = "x86_64-unknown-unknown"
14 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
15 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
16 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
18 define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
19 ; ALL-LABEL: combine_pshufd1:
20 ; ALL: # BB#0: # %entry
23 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
24 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
28 define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
29 ; ALL-LABEL: combine_pshufd2:
30 ; ALL: # BB#0: # %entry
33 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
34 %b.cast = bitcast <4 x i32> %b to <8 x i16>
35 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
36 %c.cast = bitcast <8 x i16> %c to <4 x i32>
37 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
41 define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
42 ; ALL-LABEL: combine_pshufd3:
43 ; ALL: # BB#0: # %entry
46 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
47 %b.cast = bitcast <4 x i32> %b to <8 x i16>
48 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
49 %c.cast = bitcast <8 x i16> %c to <4 x i32>
50 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
54 define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
55 ; SSE-LABEL: combine_pshufd4:
56 ; SSE: # BB#0: # %entry
57 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
60 ; AVX-LABEL: combine_pshufd4:
61 ; AVX: # BB#0: # %entry
62 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
65 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
66 %b.cast = bitcast <4 x i32> %b to <8 x i16>
67 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
68 %c.cast = bitcast <8 x i16> %c to <4 x i32>
69 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
73 define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
74 ; SSE-LABEL: combine_pshufd5:
75 ; SSE: # BB#0: # %entry
76 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
79 ; AVX-LABEL: combine_pshufd5:
80 ; AVX: # BB#0: # %entry
81 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
84 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
85 %b.cast = bitcast <4 x i32> %b to <8 x i16>
86 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
87 %c.cast = bitcast <8 x i16> %c to <4 x i32>
88 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
92 define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
93 ; SSE-LABEL: combine_pshufd6:
94 ; SSE: # BB#0: # %entry
95 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
98 ; AVX-LABEL: combine_pshufd6:
99 ; AVX: # BB#0: # %entry
100 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
103 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
104 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
108 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
109 ; ALL-LABEL: combine_pshuflw1:
110 ; ALL: # BB#0: # %entry
113 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
114 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
118 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
119 ; ALL-LABEL: combine_pshuflw2:
120 ; ALL: # BB#0: # %entry
123 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
124 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
125 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
129 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
130 ; SSE-LABEL: combine_pshuflw3:
131 ; SSE: # BB#0: # %entry
132 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
135 ; AVX-LABEL: combine_pshuflw3:
136 ; AVX: # BB#0: # %entry
137 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
140 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
141 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
142 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
146 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
147 ; SSE-LABEL: combine_pshufhw1:
148 ; SSE: # BB#0: # %entry
149 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
152 ; AVX-LABEL: combine_pshufhw1:
153 ; AVX: # BB#0: # %entry
154 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
157 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
158 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
159 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
163 define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164 ; SSE-LABEL: combine_bitwise_ops_test1:
166 ; SSE-NEXT: pand %xmm1, %xmm0
167 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
170 ; AVX-LABEL: combine_bitwise_ops_test1:
172 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
173 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
175 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
176 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177 %and = and <4 x i32> %shuf1, %shuf2
181 define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
182 ; SSE-LABEL: combine_bitwise_ops_test2:
184 ; SSE-NEXT: por %xmm1, %xmm0
185 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
188 ; AVX-LABEL: combine_bitwise_ops_test2:
190 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
191 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
193 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
194 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195 %or = or <4 x i32> %shuf1, %shuf2
199 define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
200 ; SSE-LABEL: combine_bitwise_ops_test3:
202 ; SSE-NEXT: pxor %xmm1, %xmm0
203 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
206 ; AVX-LABEL: combine_bitwise_ops_test3:
208 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
209 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
211 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
212 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213 %xor = xor <4 x i32> %shuf1, %shuf2
217 define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218 ; SSE-LABEL: combine_bitwise_ops_test4:
220 ; SSE-NEXT: pand %xmm1, %xmm0
221 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
224 ; AVX-LABEL: combine_bitwise_ops_test4:
226 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
227 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
229 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
230 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231 %and = and <4 x i32> %shuf1, %shuf2
235 define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
236 ; SSE-LABEL: combine_bitwise_ops_test5:
238 ; SSE-NEXT: por %xmm1, %xmm0
239 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
242 ; AVX-LABEL: combine_bitwise_ops_test5:
244 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
245 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
247 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
248 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249 %or = or <4 x i32> %shuf1, %shuf2
253 define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
254 ; SSE-LABEL: combine_bitwise_ops_test6:
256 ; SSE-NEXT: pxor %xmm1, %xmm0
257 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
260 ; AVX-LABEL: combine_bitwise_ops_test6:
262 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
263 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
265 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
266 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267 %xor = xor <4 x i32> %shuf1, %shuf2
272 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
273 ; are not performing a swizzle operations.
275 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
276 ; SSE2-LABEL: combine_bitwise_ops_test1b:
278 ; SSE2-NEXT: andps %xmm1, %xmm0
279 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
280 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
283 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
285 ; SSSE3-NEXT: andps %xmm1, %xmm0
286 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
287 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
290 ; SSE41-LABEL: combine_bitwise_ops_test1b:
292 ; SSE41-NEXT: pand %xmm1, %xmm0
293 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
296 ; AVX1-LABEL: combine_bitwise_ops_test1b:
298 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
299 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
302 ; AVX2-LABEL: combine_bitwise_ops_test1b:
304 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
305 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
307 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
308 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
309 %and = and <4 x i32> %shuf1, %shuf2
313 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
314 ; SSE2-LABEL: combine_bitwise_ops_test2b:
316 ; SSE2-NEXT: orps %xmm1, %xmm0
317 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
318 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
321 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
323 ; SSSE3-NEXT: orps %xmm1, %xmm0
324 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
325 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
328 ; SSE41-LABEL: combine_bitwise_ops_test2b:
330 ; SSE41-NEXT: por %xmm1, %xmm0
331 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
334 ; AVX1-LABEL: combine_bitwise_ops_test2b:
336 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
337 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
340 ; AVX2-LABEL: combine_bitwise_ops_test2b:
342 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
343 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
345 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
346 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
347 %or = or <4 x i32> %shuf1, %shuf2
351 define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
352 ; SSE2-LABEL: combine_bitwise_ops_test3b:
354 ; SSE2-NEXT: xorps %xmm1, %xmm0
355 ; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
358 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
360 ; SSSE3-NEXT: xorps %xmm1, %xmm0
361 ; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
364 ; SSE41-LABEL: combine_bitwise_ops_test3b:
366 ; SSE41-NEXT: pxor %xmm1, %xmm0
367 ; SSE41-NEXT: pxor %xmm1, %xmm1
368 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
371 ; AVX1-LABEL: combine_bitwise_ops_test3b:
373 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
374 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
375 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
378 ; AVX2-LABEL: combine_bitwise_ops_test3b:
380 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
381 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
382 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
384 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
385 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
386 %xor = xor <4 x i32> %shuf1, %shuf2
390 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
391 ; SSE2-LABEL: combine_bitwise_ops_test4b:
393 ; SSE2-NEXT: andps %xmm1, %xmm0
394 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
395 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
396 ; SSE2-NEXT: movaps %xmm2, %xmm0
399 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
401 ; SSSE3-NEXT: andps %xmm1, %xmm0
402 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
403 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
404 ; SSSE3-NEXT: movaps %xmm2, %xmm0
407 ; SSE41-LABEL: combine_bitwise_ops_test4b:
409 ; SSE41-NEXT: pand %xmm1, %xmm0
410 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
413 ; AVX1-LABEL: combine_bitwise_ops_test4b:
415 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
416 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
419 ; AVX2-LABEL: combine_bitwise_ops_test4b:
421 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
422 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
424 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
425 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
426 %and = and <4 x i32> %shuf1, %shuf2
430 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
431 ; SSE2-LABEL: combine_bitwise_ops_test5b:
433 ; SSE2-NEXT: orps %xmm1, %xmm0
434 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
435 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
436 ; SSE2-NEXT: movaps %xmm2, %xmm0
439 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
441 ; SSSE3-NEXT: orps %xmm1, %xmm0
442 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
443 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
444 ; SSSE3-NEXT: movaps %xmm2, %xmm0
447 ; SSE41-LABEL: combine_bitwise_ops_test5b:
449 ; SSE41-NEXT: por %xmm1, %xmm0
450 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
453 ; AVX1-LABEL: combine_bitwise_ops_test5b:
455 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
456 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
459 ; AVX2-LABEL: combine_bitwise_ops_test5b:
461 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
462 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
464 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
465 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
466 %or = or <4 x i32> %shuf1, %shuf2
470 define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
471 ; SSE2-LABEL: combine_bitwise_ops_test6b:
473 ; SSE2-NEXT: xorps %xmm1, %xmm0
474 ; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
477 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
479 ; SSSE3-NEXT: xorps %xmm1, %xmm0
480 ; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
483 ; SSE41-LABEL: combine_bitwise_ops_test6b:
485 ; SSE41-NEXT: pxor %xmm1, %xmm0
486 ; SSE41-NEXT: pxor %xmm1, %xmm1
487 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
490 ; AVX1-LABEL: combine_bitwise_ops_test6b:
492 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
493 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
494 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
497 ; AVX2-LABEL: combine_bitwise_ops_test6b:
499 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
500 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
501 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
503 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
504 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
505 %xor = xor <4 x i32> %shuf1, %shuf2
509 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
510 ; SSE-LABEL: combine_bitwise_ops_test1c:
512 ; SSE-NEXT: andps %xmm1, %xmm0
513 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
516 ; AVX-LABEL: combine_bitwise_ops_test1c:
518 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
519 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
521 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
522 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
523 %and = and <4 x i32> %shuf1, %shuf2
527 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
528 ; SSE-LABEL: combine_bitwise_ops_test2c:
530 ; SSE-NEXT: orps %xmm1, %xmm0
531 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
534 ; AVX-LABEL: combine_bitwise_ops_test2c:
536 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
537 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
539 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
540 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
541 %or = or <4 x i32> %shuf1, %shuf2
545 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
546 ; SSE2-LABEL: combine_bitwise_ops_test3c:
548 ; SSE2-NEXT: xorps %xmm1, %xmm0
549 ; SSE2-NEXT: xorps %xmm1, %xmm1
550 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
553 ; SSSE3-LABEL: combine_bitwise_ops_test3c:
555 ; SSSE3-NEXT: xorps %xmm1, %xmm0
556 ; SSSE3-NEXT: xorps %xmm1, %xmm1
557 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
560 ; SSE41-LABEL: combine_bitwise_ops_test3c:
562 ; SSE41-NEXT: xorps %xmm1, %xmm0
563 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
566 ; AVX-LABEL: combine_bitwise_ops_test3c:
568 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
569 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
571 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
572 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
573 %xor = xor <4 x i32> %shuf1, %shuf2
577 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
578 ; SSE-LABEL: combine_bitwise_ops_test4c:
580 ; SSE-NEXT: andps %xmm1, %xmm0
581 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
582 ; SSE-NEXT: movaps %xmm2, %xmm0
585 ; AVX-LABEL: combine_bitwise_ops_test4c:
587 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
588 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
590 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
591 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
592 %and = and <4 x i32> %shuf1, %shuf2
596 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
597 ; SSE-LABEL: combine_bitwise_ops_test5c:
599 ; SSE-NEXT: orps %xmm1, %xmm0
600 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
601 ; SSE-NEXT: movaps %xmm2, %xmm0
604 ; AVX-LABEL: combine_bitwise_ops_test5c:
606 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
607 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
609 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
610 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
611 %or = or <4 x i32> %shuf1, %shuf2
615 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
616 ; SSE-LABEL: combine_bitwise_ops_test6c:
618 ; SSE-NEXT: xorps %xmm1, %xmm0
619 ; SSE-NEXT: xorps %xmm1, %xmm1
620 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
621 ; SSE-NEXT: movaps %xmm1, %xmm0
624 ; AVX-LABEL: combine_bitwise_ops_test6c:
626 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
627 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
628 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[1,3]
630 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
631 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
632 %xor = xor <4 x i32> %shuf1, %shuf2
636 define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
637 ; SSE-LABEL: combine_nested_undef_test1:
639 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
642 ; AVX-LABEL: combine_nested_undef_test1:
644 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
646 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
647 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
651 define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
652 ; SSE-LABEL: combine_nested_undef_test2:
654 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
657 ; AVX-LABEL: combine_nested_undef_test2:
659 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
661 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
662 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
666 define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
667 ; SSE-LABEL: combine_nested_undef_test3:
669 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
672 ; AVX-LABEL: combine_nested_undef_test3:
674 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
676 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
677 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
681 define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
682 ; SSE-LABEL: combine_nested_undef_test4:
684 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
687 ; AVX1-LABEL: combine_nested_undef_test4:
689 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
692 ; AVX2-LABEL: combine_nested_undef_test4:
694 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
696 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
697 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
701 define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
702 ; SSE-LABEL: combine_nested_undef_test5:
704 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
707 ; AVX-LABEL: combine_nested_undef_test5:
709 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
711 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
712 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
716 define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
717 ; SSE-LABEL: combine_nested_undef_test6:
719 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
722 ; AVX-LABEL: combine_nested_undef_test6:
724 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
726 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
727 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
731 define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
732 ; SSE-LABEL: combine_nested_undef_test7:
734 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
737 ; AVX-LABEL: combine_nested_undef_test7:
739 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
741 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
742 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
746 define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
747 ; SSE-LABEL: combine_nested_undef_test8:
749 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
752 ; AVX-LABEL: combine_nested_undef_test8:
754 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
756 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
757 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
761 define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
762 ; SSE-LABEL: combine_nested_undef_test9:
764 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
767 ; AVX-LABEL: combine_nested_undef_test9:
769 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
771 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
772 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
776 define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
777 ; SSE-LABEL: combine_nested_undef_test10:
779 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
782 ; AVX-LABEL: combine_nested_undef_test10:
784 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
786 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
787 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
791 define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
792 ; SSE-LABEL: combine_nested_undef_test11:
794 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
797 ; AVX-LABEL: combine_nested_undef_test11:
799 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
801 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
802 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
806 define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
807 ; SSE-LABEL: combine_nested_undef_test12:
809 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
812 ; AVX1-LABEL: combine_nested_undef_test12:
814 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
817 ; AVX2-LABEL: combine_nested_undef_test12:
819 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
821 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
822 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
826 ; The following pair of shuffles is folded into vector %A.
827 define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
828 ; ALL-LABEL: combine_nested_undef_test13:
831 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
832 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
836 ; The following pair of shuffles is folded into vector %B.
837 define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
838 ; SSE-LABEL: combine_nested_undef_test14:
840 ; SSE-NEXT: movaps %xmm1, %xmm0
843 ; AVX-LABEL: combine_nested_undef_test14:
845 ; AVX-NEXT: vmovaps %xmm1, %xmm0
847 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
848 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
853 ; Verify that we don't optimize the following cases. We expect more than one shuffle.
855 ; FIXME: Many of these already don't make sense, and the rest should stop
856 ; making sense with th enew vector shuffle lowering. Revisit at least testing for
859 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
860 ; SSE-LABEL: combine_nested_undef_test15:
862 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
863 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,1]
864 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
867 ; AVX-LABEL: combine_nested_undef_test15:
869 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
870 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[3,1]
871 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
873 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
874 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
878 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
879 ; SSE2-LABEL: combine_nested_undef_test16:
881 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
882 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
883 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
886 ; SSSE3-LABEL: combine_nested_undef_test16:
888 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
889 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
890 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
893 ; SSE41-LABEL: combine_nested_undef_test16:
895 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
896 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
899 ; AVX1-LABEL: combine_nested_undef_test16:
901 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
902 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
905 ; AVX2-LABEL: combine_nested_undef_test16:
907 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
908 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
910 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
911 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
915 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
916 ; SSE-LABEL: combine_nested_undef_test17:
918 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
919 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
920 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
923 ; AVX-LABEL: combine_nested_undef_test17:
925 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
926 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
927 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
929 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
930 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
934 define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
935 ; SSE-LABEL: combine_nested_undef_test18:
937 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
940 ; AVX-LABEL: combine_nested_undef_test18:
942 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
944 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
945 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
949 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
950 ; SSE-LABEL: combine_nested_undef_test19:
952 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
953 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
954 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
957 ; AVX-LABEL: combine_nested_undef_test19:
959 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
960 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
961 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
963 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
964 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
968 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
969 ; SSE-LABEL: combine_nested_undef_test20:
971 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
972 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
975 ; AVX-LABEL: combine_nested_undef_test20:
977 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
978 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
980 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
981 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
985 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
986 ; SSE-LABEL: combine_nested_undef_test21:
988 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
989 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
990 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
993 ; AVX-LABEL: combine_nested_undef_test21:
995 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
996 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
997 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
999 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
1000 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1005 ; Test that we correctly combine shuffles according to rule
1006 ; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
1008 define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
1009 ; SSE-LABEL: combine_nested_undef_test22:
1011 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1014 ; AVX-LABEL: combine_nested_undef_test22:
1016 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1018 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1019 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
1023 define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1024 ; SSE-LABEL: combine_nested_undef_test23:
1026 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1029 ; AVX-LABEL: combine_nested_undef_test23:
1031 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1033 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1034 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1038 define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1039 ; SSE-LABEL: combine_nested_undef_test24:
1041 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1044 ; AVX-LABEL: combine_nested_undef_test24:
1046 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1048 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1049 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1053 define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1054 ; SSE-LABEL: combine_nested_undef_test25:
1056 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1059 ; AVX1-LABEL: combine_nested_undef_test25:
1061 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1064 ; AVX2-LABEL: combine_nested_undef_test25:
1066 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1068 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1069 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1073 define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1074 ; SSE-LABEL: combine_nested_undef_test26:
1076 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1079 ; AVX-LABEL: combine_nested_undef_test26:
1081 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1083 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1084 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1088 define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1089 ; SSE-LABEL: combine_nested_undef_test27:
1091 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1094 ; AVX1-LABEL: combine_nested_undef_test27:
1096 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1099 ; AVX2-LABEL: combine_nested_undef_test27:
1101 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1103 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1104 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1108 define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1109 ; SSE-LABEL: combine_nested_undef_test28:
1111 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1114 ; AVX-LABEL: combine_nested_undef_test28:
1116 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1118 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1119 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1123 define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1124 ; SSE-LABEL: combine_test1:
1126 ; SSE-NEXT: movaps %xmm1, %xmm0
1129 ; AVX-LABEL: combine_test1:
1131 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1133 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1134 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1138 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1139 ; SSE2-LABEL: combine_test2:
1141 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1142 ; SSE2-NEXT: movaps %xmm1, %xmm0
1145 ; SSSE3-LABEL: combine_test2:
1147 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1148 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1151 ; SSE41-LABEL: combine_test2:
1153 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1156 ; AVX-LABEL: combine_test2:
1158 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1160 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1161 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1165 define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1166 ; SSE-LABEL: combine_test3:
1168 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1171 ; AVX-LABEL: combine_test3:
1173 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1175 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1176 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1180 define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1181 ; SSE-LABEL: combine_test4:
1183 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1184 ; SSE-NEXT: movapd %xmm1, %xmm0
1187 ; AVX-LABEL: combine_test4:
1189 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1191 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1192 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1196 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1197 ; SSE2-LABEL: combine_test5:
1199 ; SSE2-NEXT: movaps %xmm1, %xmm2
1200 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1201 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1202 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1203 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1204 ; SSE2-NEXT: movaps %xmm2, %xmm0
1207 ; SSSE3-LABEL: combine_test5:
1209 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1210 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1211 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1212 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1213 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1214 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1217 ; SSE41-LABEL: combine_test5:
1219 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1222 ; AVX-LABEL: combine_test5:
1224 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1226 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1227 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1231 define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1232 ; SSE-LABEL: combine_test6:
1234 ; SSE-NEXT: movaps %xmm1, %xmm0
1237 ; AVX-LABEL: combine_test6:
1239 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1241 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1242 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1246 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1247 ; SSE2-LABEL: combine_test7:
1249 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1250 ; SSE2-NEXT: movaps %xmm1, %xmm0
1253 ; SSSE3-LABEL: combine_test7:
1255 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1256 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1259 ; SSE41-LABEL: combine_test7:
1261 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1264 ; AVX1-LABEL: combine_test7:
1266 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1269 ; AVX2-LABEL: combine_test7:
1271 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1273 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1274 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1278 define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1279 ; SSE-LABEL: combine_test8:
1281 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1284 ; AVX-LABEL: combine_test8:
1286 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1288 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1289 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1293 define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1294 ; SSE-LABEL: combine_test9:
1296 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1297 ; SSE-NEXT: movdqa %xmm1, %xmm0
1300 ; AVX-LABEL: combine_test9:
1302 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1304 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1305 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1309 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1310 ; SSE2-LABEL: combine_test10:
1312 ; SSE2-NEXT: movaps %xmm1, %xmm2
1313 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1314 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1315 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1316 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1317 ; SSE2-NEXT: movaps %xmm2, %xmm0
1320 ; SSSE3-LABEL: combine_test10:
1322 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1323 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1324 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1325 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1326 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1327 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1330 ; SSE41-LABEL: combine_test10:
1332 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1335 ; AVX1-LABEL: combine_test10:
1337 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1340 ; AVX2-LABEL: combine_test10:
1342 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1344 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1345 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1349 define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1350 ; ALL-LABEL: combine_test11:
1353 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1354 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1358 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1359 ; SSE2-LABEL: combine_test12:
1361 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1362 ; SSE2-NEXT: movaps %xmm1, %xmm0
1365 ; SSSE3-LABEL: combine_test12:
1367 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1368 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1371 ; SSE41-LABEL: combine_test12:
1373 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1376 ; AVX-LABEL: combine_test12:
1378 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1380 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1381 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1385 define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1386 ; SSE-LABEL: combine_test13:
1388 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1391 ; AVX-LABEL: combine_test13:
1393 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1395 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1396 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1400 define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1401 ; SSE-LABEL: combine_test14:
1403 ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1406 ; AVX-LABEL: combine_test14:
1408 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1410 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1411 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1415 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1416 ; SSE2-LABEL: combine_test15:
1418 ; SSE2-NEXT: movaps %xmm0, %xmm2
1419 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1420 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1421 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1422 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1425 ; SSSE3-LABEL: combine_test15:
1427 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1428 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1429 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1430 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1431 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1434 ; SSE41-LABEL: combine_test15:
1436 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1439 ; AVX-LABEL: combine_test15:
1441 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1443 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1444 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1448 define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1449 ; ALL-LABEL: combine_test16:
1452 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1453 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1457 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1458 ; SSE2-LABEL: combine_test17:
1460 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1461 ; SSE2-NEXT: movaps %xmm1, %xmm0
1464 ; SSSE3-LABEL: combine_test17:
1466 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1467 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1470 ; SSE41-LABEL: combine_test17:
1472 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1475 ; AVX1-LABEL: combine_test17:
1477 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1480 ; AVX2-LABEL: combine_test17:
1482 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1484 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1485 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1489 define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1490 ; SSE-LABEL: combine_test18:
1492 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1495 ; AVX-LABEL: combine_test18:
1497 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1499 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1500 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1504 define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1505 ; SSE-LABEL: combine_test19:
1507 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1510 ; AVX-LABEL: combine_test19:
1512 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1514 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1515 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1519 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1520 ; SSE2-LABEL: combine_test20:
1522 ; SSE2-NEXT: movaps %xmm0, %xmm2
1523 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1524 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1525 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1526 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1529 ; SSSE3-LABEL: combine_test20:
1531 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1532 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1533 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1534 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1535 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1538 ; SSE41-LABEL: combine_test20:
1540 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1543 ; AVX1-LABEL: combine_test20:
1545 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1548 ; AVX2-LABEL: combine_test20:
1550 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1552 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1553 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1557 define <4 x i32> @combine_test21(<8 x i32> %a, <4 x i32>* %ptr) {
1558 ; SSE-LABEL: combine_test21:
1560 ; SSE-NEXT: movdqa %xmm0, %xmm2
1561 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
1562 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1563 ; SSE-NEXT: movdqa %xmm2, (%rdi)
1566 ; AVX1-LABEL: combine_test21:
1568 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
1569 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1570 ; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1571 ; AVX1-NEXT: vmovdqa %xmm2, (%rdi)
1572 ; AVX1-NEXT: vzeroupper
1575 ; AVX2-LABEL: combine_test21:
1577 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1578 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1579 ; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1580 ; AVX2-NEXT: vmovdqa %xmm2, (%rdi)
1581 ; AVX2-NEXT: vzeroupper
1583 %1 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1584 %2 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
1585 store <4 x i32> %1, <4 x i32>* %ptr, align 16
1589 define <8 x float> @combine_test22(<2 x float>* %a, <2 x float>* %b) {
1590 ; SSE-LABEL: combine_test22:
1592 ; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
1593 ; SSE-NEXT: movhpd (%rsi), %xmm0
1596 ; AVX-LABEL: combine_test22:
1598 ; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
1599 ; AVX-NEXT: vmovhpd (%rsi), %xmm0, %xmm0
1601 ; Current AVX2 lowering of this is still awful, not adding a test case.
1602 %1 = load <2 x float>* %a, align 8
1603 %2 = load <2 x float>* %b, align 8
1604 %3 = shufflevector <2 x float> %1, <2 x float> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
1608 ; Check some negative cases.
1609 ; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1611 define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1612 ; SSE-LABEL: combine_test1b:
1614 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,2,0]
1615 ; SSE-NEXT: movaps %xmm1, %xmm0
1618 ; AVX-LABEL: combine_test1b:
1620 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[0,1,2,0]
1622 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1623 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1627 define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1628 ; SSE2-LABEL: combine_test2b:
1630 ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0,0]
1631 ; SSE2-NEXT: movaps %xmm1, %xmm0
1634 ; SSSE3-LABEL: combine_test2b:
1636 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
1639 ; SSE41-LABEL: combine_test2b:
1641 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
1644 ; AVX-LABEL: combine_test2b:
1646 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm1[0,0]
1648 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1649 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
1653 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1654 ; SSE-LABEL: combine_test3b:
1656 ; SSE-NEXT: movaps %xmm1, %xmm2
1657 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[3,0]
1658 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1659 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1660 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1663 ; AVX-LABEL: combine_test3b:
1665 ; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,0],xmm0[3,0]
1666 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1667 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1668 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1670 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1671 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1675 define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1676 ; SSE-LABEL: combine_test4b:
1678 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
1679 ; SSE-NEXT: movaps %xmm1, %xmm0
1682 ; AVX-LABEL: combine_test4b:
1684 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[1,1,2,3]
1686 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1687 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1692 ; Verify that we correctly fold shuffles even when we use illegal vector types.
1694 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1695 ; SSE2-LABEL: combine_test1c:
1697 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1698 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1699 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1700 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1701 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1702 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1703 ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1706 ; SSSE3-LABEL: combine_test1c:
1708 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1709 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1710 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1711 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1712 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1713 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1714 ; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1717 ; SSE41-LABEL: combine_test1c:
1719 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1720 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1721 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1724 ; AVX1-LABEL: combine_test1c:
1726 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1727 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1728 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1731 ; AVX2-LABEL: combine_test1c:
1733 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1734 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1735 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1737 %A = load <4 x i8>* %a
1738 %B = load <4 x i8>* %b
1739 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1740 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1744 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1745 ; SSE2-LABEL: combine_test2c:
1747 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1748 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1749 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1750 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1751 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1752 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1753 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1756 ; SSSE3-LABEL: combine_test2c:
1758 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1759 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1760 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1761 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1762 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1763 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1764 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1767 ; SSE41-LABEL: combine_test2c:
1769 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1770 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1771 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1774 ; AVX-LABEL: combine_test2c:
1776 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1777 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1778 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1780 %A = load <4 x i8>* %a
1781 %B = load <4 x i8>* %b
1782 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1783 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1787 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1788 ; SSE2-LABEL: combine_test3c:
1790 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1791 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1792 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1793 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1794 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1795 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1796 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1799 ; SSSE3-LABEL: combine_test3c:
1801 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1802 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1803 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1804 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1805 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1806 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1807 ; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1810 ; SSE41-LABEL: combine_test3c:
1812 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1813 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1814 ; SSE41-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1817 ; AVX-LABEL: combine_test3c:
1819 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1820 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1821 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1823 %A = load <4 x i8>* %a
1824 %B = load <4 x i8>* %b
1825 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1826 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1830 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
1831 ; SSE2-LABEL: combine_test4c:
1833 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1834 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1835 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1836 ; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
1837 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1838 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1839 ; SSE2-NEXT: movdqa %xmm2, %xmm0
1840 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1841 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1842 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1843 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1846 ; SSSE3-LABEL: combine_test4c:
1848 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1849 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1850 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1851 ; SSSE3-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
1852 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1853 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1854 ; SSSE3-NEXT: movdqa %xmm2, %xmm0
1855 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1856 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1857 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1858 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1861 ; SSE41-LABEL: combine_test4c:
1863 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1864 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1865 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1868 ; AVX1-LABEL: combine_test4c:
1870 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1871 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1872 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1875 ; AVX2-LABEL: combine_test4c:
1877 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1878 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1879 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1881 %A = load <4 x i8>* %a
1882 %B = load <4 x i8>* %b
1883 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1884 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1889 ; The following test cases are generated from this C++ code
1891 ;__m128 blend_01(__m128 a, __m128 b)
1894 ; s = _mm_blend_ps( s, b, 1<<0 );
1895 ; s = _mm_blend_ps( s, b, 1<<1 );
1899 ;__m128 blend_02(__m128 a, __m128 b)
1902 ; s = _mm_blend_ps( s, b, 1<<0 );
1903 ; s = _mm_blend_ps( s, b, 1<<2 );
1907 ;__m128 blend_123(__m128 a, __m128 b)
1910 ; s = _mm_blend_ps( s, b, 1<<1 );
1911 ; s = _mm_blend_ps( s, b, 1<<2 );
1912 ; s = _mm_blend_ps( s, b, 1<<3 );
1916 ; Ideally, we should collapse the following shuffles into a single one.
1918 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
1919 ; SSE2-LABEL: combine_blend_01:
1921 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1924 ; SSSE3-LABEL: combine_blend_01:
1926 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1929 ; SSE41-LABEL: combine_blend_01:
1931 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1934 ; AVX-LABEL: combine_blend_01:
1936 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1938 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
1939 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1940 ret <4 x float> %shuffle6
1943 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
1944 ; SSE2-LABEL: combine_blend_02:
1946 ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1947 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1948 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1951 ; SSSE3-LABEL: combine_blend_02:
1953 ; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1954 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1955 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1958 ; SSE41-LABEL: combine_blend_02:
1960 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1963 ; AVX-LABEL: combine_blend_02:
1965 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1967 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
1968 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1969 ret <4 x float> %shuffle6
1972 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
1973 ; SSE2-LABEL: combine_blend_123:
1975 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1976 ; SSE2-NEXT: movaps %xmm1, %xmm0
1979 ; SSSE3-LABEL: combine_blend_123:
1981 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1982 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1985 ; SSE41-LABEL: combine_blend_123:
1987 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1990 ; AVX-LABEL: combine_blend_123:
1992 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1994 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
1995 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
1996 %shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1997 ret <4 x float> %shuffle12
2000 define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
2001 ; SSE-LABEL: combine_test_movhl_1:
2003 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2004 ; SSE-NEXT: movdqa %xmm1, %xmm0
2007 ; AVX-LABEL: combine_test_movhl_1:
2009 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2011 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
2012 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
2016 define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
2017 ; SSE-LABEL: combine_test_movhl_2:
2019 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2020 ; SSE-NEXT: movdqa %xmm1, %xmm0
2023 ; AVX-LABEL: combine_test_movhl_2:
2025 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2027 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
2028 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
2032 define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
2033 ; SSE-LABEL: combine_test_movhl_3:
2035 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2036 ; SSE-NEXT: movdqa %xmm1, %xmm0
2039 ; AVX-LABEL: combine_test_movhl_3:
2041 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2043 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
2044 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>
2049 ; Verify that we fold shuffles according to rule:
2050 ; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
2052 define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
2053 ; SSE2-LABEL: combine_undef_input_test1:
2055 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2058 ; SSSE3-LABEL: combine_undef_input_test1:
2060 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2063 ; SSE41-LABEL: combine_undef_input_test1:
2065 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2068 ; AVX-LABEL: combine_undef_input_test1:
2070 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2072 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2073 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2077 define <4 x float> @combine_undef_input_test2(<4 x float> %a, <4 x float> %b) {
2078 ; SSE-LABEL: combine_undef_input_test2:
2080 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2083 ; AVX-LABEL: combine_undef_input_test2:
2085 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2087 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2088 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2092 define <4 x float> @combine_undef_input_test3(<4 x float> %a, <4 x float> %b) {
2093 ; SSE-LABEL: combine_undef_input_test3:
2095 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2098 ; AVX-LABEL: combine_undef_input_test3:
2100 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2102 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2103 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2107 define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
2108 ; SSE-LABEL: combine_undef_input_test4:
2110 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2111 ; SSE-NEXT: movapd %xmm1, %xmm0
2114 ; AVX-LABEL: combine_undef_input_test4:
2116 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2118 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2119 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2123 define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
2124 ; SSE2-LABEL: combine_undef_input_test5:
2126 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2127 ; SSE2-NEXT: movaps %xmm1, %xmm0
2130 ; SSSE3-LABEL: combine_undef_input_test5:
2132 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2133 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2136 ; SSE41-LABEL: combine_undef_input_test5:
2138 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2141 ; AVX-LABEL: combine_undef_input_test5:
2143 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2145 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2146 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2151 ; Verify that we fold shuffles according to rule:
2152 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2154 define <4 x float> @combine_undef_input_test6(<4 x float> %a) {
2155 ; ALL-LABEL: combine_undef_input_test6:
2158 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2159 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2163 define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
2164 ; SSE2-LABEL: combine_undef_input_test7:
2166 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2169 ; SSSE3-LABEL: combine_undef_input_test7:
2171 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2174 ; SSE41-LABEL: combine_undef_input_test7:
2176 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2179 ; AVX-LABEL: combine_undef_input_test7:
2181 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2183 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2184 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2188 define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
2189 ; SSE2-LABEL: combine_undef_input_test8:
2191 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2194 ; SSSE3-LABEL: combine_undef_input_test8:
2196 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2199 ; SSE41-LABEL: combine_undef_input_test8:
2201 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2204 ; AVX-LABEL: combine_undef_input_test8:
2206 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2208 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2209 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2213 define <4 x float> @combine_undef_input_test9(<4 x float> %a) {
2214 ; SSE-LABEL: combine_undef_input_test9:
2216 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2219 ; AVX-LABEL: combine_undef_input_test9:
2221 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2223 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2224 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2228 define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
2229 ; ALL-LABEL: combine_undef_input_test10:
2232 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2233 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2237 define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
2238 ; SSE2-LABEL: combine_undef_input_test11:
2240 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2243 ; SSSE3-LABEL: combine_undef_input_test11:
2245 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2248 ; SSE41-LABEL: combine_undef_input_test11:
2250 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2253 ; AVX-LABEL: combine_undef_input_test11:
2255 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2257 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2258 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 6>
2262 define <4 x float> @combine_undef_input_test12(<4 x float> %a, <4 x float> %b) {
2263 ; SSE-LABEL: combine_undef_input_test12:
2265 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2268 ; AVX-LABEL: combine_undef_input_test12:
2270 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2272 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2273 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2277 define <4 x float> @combine_undef_input_test13(<4 x float> %a, <4 x float> %b) {
2278 ; SSE-LABEL: combine_undef_input_test13:
2280 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2283 ; AVX-LABEL: combine_undef_input_test13:
2285 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2287 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2288 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 5, i32 0, i32 5>
2292 define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
2293 ; SSE-LABEL: combine_undef_input_test14:
2295 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2296 ; SSE-NEXT: movapd %xmm1, %xmm0
2299 ; AVX-LABEL: combine_undef_input_test14:
2301 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2303 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2304 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2308 define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
2309 ; SSE2-LABEL: combine_undef_input_test15:
2311 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2312 ; SSE2-NEXT: movaps %xmm1, %xmm0
2315 ; SSSE3-LABEL: combine_undef_input_test15:
2317 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2318 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2321 ; SSE41-LABEL: combine_undef_input_test15:
2323 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2326 ; AVX-LABEL: combine_undef_input_test15:
2328 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2330 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2331 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2336 ; Verify that shuffles are canonicalized according to rules:
2337 ; shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
2339 ; This allows to trigger the following combine rule:
2340 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2342 ; As a result, all the shuffle pairs in each function below should be
2343 ; combined into a single legal shuffle operation.
2345 define <4 x float> @combine_undef_input_test16(<4 x float> %a) {
2346 ; ALL-LABEL: combine_undef_input_test16:
2349 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2350 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
2354 define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
2355 ; SSE2-LABEL: combine_undef_input_test17:
2357 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2360 ; SSSE3-LABEL: combine_undef_input_test17:
2362 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2365 ; SSE41-LABEL: combine_undef_input_test17:
2367 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2370 ; AVX-LABEL: combine_undef_input_test17:
2372 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2374 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2375 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2379 define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
2380 ; SSE2-LABEL: combine_undef_input_test18:
2382 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2385 ; SSSE3-LABEL: combine_undef_input_test18:
2387 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2390 ; SSE41-LABEL: combine_undef_input_test18:
2392 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2395 ; AVX-LABEL: combine_undef_input_test18:
2397 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2399 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2400 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
2404 define <4 x float> @combine_undef_input_test19(<4 x float> %a) {
2405 ; SSE-LABEL: combine_undef_input_test19:
2407 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2410 ; AVX-LABEL: combine_undef_input_test19:
2412 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2414 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2415 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2419 define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
2420 ; ALL-LABEL: combine_undef_input_test20:
2423 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2424 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2428 ; These tests are designed to test the ability to combine away unnecessary
2429 ; operations feeding into a shuffle. The AVX cases are the important ones as
2430 ; they leverage operations which cannot be done naturally on the entire vector
2431 ; and thus are decomposed into multiple smaller operations.
2433 define <8 x i32> @combine_unneeded_subvector1(<8 x i32> %a) {
2434 ; SSE-LABEL: combine_unneeded_subvector1:
2436 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2437 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
2438 ; SSE-NEXT: movdqa %xmm0, %xmm1
2441 ; AVX1-LABEL: combine_unneeded_subvector1:
2443 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2444 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2445 ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2446 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2449 ; AVX2-LABEL: combine_unneeded_subvector1:
2451 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2452 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
2453 ; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
2455 %b = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2456 %c = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
2460 define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
2461 ; SSE-LABEL: combine_unneeded_subvector2:
2463 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2464 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,2,1,0]
2465 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
2468 ; AVX1-LABEL: combine_unneeded_subvector2:
2470 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2471 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2472 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2473 ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2474 ; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2477 ; AVX2-LABEL: combine_unneeded_subvector2:
2479 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2480 ; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2481 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2483 %c = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2484 %d = shufflevector <8 x i32> %b, <8 x i32> %c, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>
2488 define <4 x float> @combine_insertps1(<4 x float> %a, <4 x float> %b) {
2489 ; SSE2-LABEL: combine_insertps1:
2491 ; SSE2-NEXT: movaps %xmm0, %xmm2
2492 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[2,0]
2493 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
2494 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,2],xmm0[1,3]
2495 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
2496 ; SSE2-NEXT: movaps %xmm2, %xmm0
2499 ; SSSE3-LABEL: combine_insertps1:
2501 ; SSSE3-NEXT: movaps %xmm0, %xmm2
2502 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[2,0]
2503 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
2504 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,2],xmm0[1,3]
2505 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
2506 ; SSSE3-NEXT: movaps %xmm2, %xmm0
2509 ; SSE41-LABEL: combine_insertps1:
2511 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2514 ; AVX-LABEL: combine_insertps1:
2516 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2519 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 6, i32 2, i32 4>
2520 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 5, i32 1, i32 6, i32 3>
2524 define <4 x float> @combine_insertps2(<4 x float> %a, <4 x float> %b) {
2525 ; SSE2-LABEL: combine_insertps2:
2527 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2528 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
2529 ; SSE2-NEXT: movaps %xmm1, %xmm0
2532 ; SSSE3-LABEL: combine_insertps2:
2534 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2535 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
2536 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2539 ; SSE41-LABEL: combine_insertps2:
2541 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2544 ; AVX-LABEL: combine_insertps2:
2546 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2549 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 1, i32 6, i32 7>
2550 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2554 define <4 x float> @combine_insertps3(<4 x float> %a, <4 x float> %b) {
2555 ; SSE2-LABEL: combine_insertps3:
2557 ; SSE2-NEXT: movaps %xmm0, %xmm2
2558 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,1]
2559 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
2560 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1,3]
2561 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
2562 ; SSE2-NEXT: movaps %xmm2, %xmm0
2565 ; SSSE3-LABEL: combine_insertps3:
2567 ; SSSE3-NEXT: movaps %xmm0, %xmm2
2568 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,1]
2569 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
2570 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1,3]
2571 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
2572 ; SSSE3-NEXT: movaps %xmm2, %xmm0
2575 ; SSE41-LABEL: combine_insertps3:
2577 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2580 ; AVX-LABEL: combine_insertps3:
2582 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2585 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2586 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 5, i32 3>
2590 define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) {
2591 ; SSE2-LABEL: combine_insertps4:
2593 ; SSE2-NEXT: movaps %xmm0, %xmm2
2594 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,1]
2595 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
2596 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
2597 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,1]
2600 ; SSSE3-LABEL: combine_insertps4:
2602 ; SSSE3-NEXT: movaps %xmm0, %xmm2
2603 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,1]
2604 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
2605 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
2606 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,1]
2609 ; SSE41-LABEL: combine_insertps4:
2611 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2614 ; AVX-LABEL: combine_insertps4:
2616 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2619 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2620 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 6, i32 5>