1 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7 ; Verify that the DAG combiner correctly folds bitwise operations across
8 ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
9 ; basic and always-safe patterns. Also test that the DAG combiner will combine
10 ; target-specific shuffle instructions where reasonable.
12 target triple = "x86_64-unknown-unknown"
14 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
15 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
16 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
18 define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
19 ; ALL-LABEL: combine_pshufd1:
20 ; ALL: # BB#0: # %entry
23 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
24 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
28 define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
29 ; ALL-LABEL: combine_pshufd2:
30 ; ALL: # BB#0: # %entry
33 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
34 %b.cast = bitcast <4 x i32> %b to <8 x i16>
35 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
36 %c.cast = bitcast <8 x i16> %c to <4 x i32>
37 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
41 define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
42 ; ALL-LABEL: combine_pshufd3:
43 ; ALL: # BB#0: # %entry
46 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
47 %b.cast = bitcast <4 x i32> %b to <8 x i16>
48 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
49 %c.cast = bitcast <8 x i16> %c to <4 x i32>
50 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
54 define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
55 ; SSE-LABEL: combine_pshufd4:
56 ; SSE: # BB#0: # %entry
57 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
60 ; AVX-LABEL: combine_pshufd4:
61 ; AVX: # BB#0: # %entry
62 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
65 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
66 %b.cast = bitcast <4 x i32> %b to <8 x i16>
67 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
68 %c.cast = bitcast <8 x i16> %c to <4 x i32>
69 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
73 define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
74 ; SSE-LABEL: combine_pshufd5:
75 ; SSE: # BB#0: # %entry
76 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
79 ; AVX-LABEL: combine_pshufd5:
80 ; AVX: # BB#0: # %entry
81 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
84 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
85 %b.cast = bitcast <4 x i32> %b to <8 x i16>
86 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
87 %c.cast = bitcast <8 x i16> %c to <4 x i32>
88 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
92 define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
93 ; SSE-LABEL: combine_pshufd6:
94 ; SSE: # BB#0: # %entry
95 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
98 ; AVX-LABEL: combine_pshufd6:
99 ; AVX: # BB#0: # %entry
100 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
103 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
104 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
108 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
109 ; ALL-LABEL: combine_pshuflw1:
110 ; ALL: # BB#0: # %entry
113 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
114 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
118 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
119 ; ALL-LABEL: combine_pshuflw2:
120 ; ALL: # BB#0: # %entry
123 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
124 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
125 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
129 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
130 ; SSE-LABEL: combine_pshuflw3:
131 ; SSE: # BB#0: # %entry
132 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
135 ; AVX-LABEL: combine_pshuflw3:
136 ; AVX: # BB#0: # %entry
137 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
140 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
141 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
142 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
146 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
147 ; SSE-LABEL: combine_pshufhw1:
148 ; SSE: # BB#0: # %entry
149 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
152 ; AVX-LABEL: combine_pshufhw1:
153 ; AVX: # BB#0: # %entry
154 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
157 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
158 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
159 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
163 define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164 ; SSE-LABEL: combine_bitwise_ops_test1:
166 ; SSE-NEXT: pand %xmm1, %xmm0
167 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
170 ; AVX-LABEL: combine_bitwise_ops_test1:
172 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
173 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
175 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
176 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177 %and = and <4 x i32> %shuf1, %shuf2
181 define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
182 ; SSE-LABEL: combine_bitwise_ops_test2:
184 ; SSE-NEXT: por %xmm1, %xmm0
185 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
188 ; AVX-LABEL: combine_bitwise_ops_test2:
190 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
191 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
193 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
194 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195 %or = or <4 x i32> %shuf1, %shuf2
199 define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
200 ; SSE-LABEL: combine_bitwise_ops_test3:
202 ; SSE-NEXT: pxor %xmm1, %xmm0
203 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
206 ; AVX-LABEL: combine_bitwise_ops_test3:
208 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
209 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
211 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
212 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213 %xor = xor <4 x i32> %shuf1, %shuf2
217 define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218 ; SSE-LABEL: combine_bitwise_ops_test4:
220 ; SSE-NEXT: pand %xmm1, %xmm0
221 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
224 ; AVX-LABEL: combine_bitwise_ops_test4:
226 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
227 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
229 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
230 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231 %and = and <4 x i32> %shuf1, %shuf2
235 define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
236 ; SSE-LABEL: combine_bitwise_ops_test5:
238 ; SSE-NEXT: por %xmm1, %xmm0
239 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
242 ; AVX-LABEL: combine_bitwise_ops_test5:
244 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
245 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
247 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
248 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249 %or = or <4 x i32> %shuf1, %shuf2
253 define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
254 ; SSE-LABEL: combine_bitwise_ops_test6:
256 ; SSE-NEXT: pxor %xmm1, %xmm0
257 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
260 ; AVX-LABEL: combine_bitwise_ops_test6:
262 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
263 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
265 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
266 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267 %xor = xor <4 x i32> %shuf1, %shuf2
272 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
273 ; are not performing a swizzle operations.
275 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
276 ; SSE2-LABEL: combine_bitwise_ops_test1b:
278 ; SSE2-NEXT: andps %xmm1, %xmm0
279 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
280 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
283 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
285 ; SSSE3-NEXT: andps %xmm1, %xmm0
286 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
287 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
290 ; SSE41-LABEL: combine_bitwise_ops_test1b:
292 ; SSE41-NEXT: pand %xmm1, %xmm0
293 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
296 ; AVX1-LABEL: combine_bitwise_ops_test1b:
298 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
299 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
302 ; AVX2-LABEL: combine_bitwise_ops_test1b:
304 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
305 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
307 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
308 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
309 %and = and <4 x i32> %shuf1, %shuf2
313 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
314 ; SSE2-LABEL: combine_bitwise_ops_test2b:
316 ; SSE2-NEXT: orps %xmm1, %xmm0
317 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
318 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
321 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
323 ; SSSE3-NEXT: orps %xmm1, %xmm0
324 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
325 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
328 ; SSE41-LABEL: combine_bitwise_ops_test2b:
330 ; SSE41-NEXT: por %xmm1, %xmm0
331 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
334 ; AVX1-LABEL: combine_bitwise_ops_test2b:
336 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
337 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
340 ; AVX2-LABEL: combine_bitwise_ops_test2b:
342 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
343 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
345 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
346 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
347 %or = or <4 x i32> %shuf1, %shuf2
351 define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
352 ; SSE2-LABEL: combine_bitwise_ops_test3b:
354 ; SSE2-NEXT: xorps %xmm1, %xmm0
355 ; SSE2-NEXT: xorps %xmm1, %xmm1
356 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
357 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
360 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
362 ; SSSE3-NEXT: xorps %xmm1, %xmm0
363 ; SSSE3-NEXT: xorps %xmm1, %xmm1
364 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
365 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
368 ; SSE41-LABEL: combine_bitwise_ops_test3b:
370 ; SSE41-NEXT: pxor %xmm1, %xmm0
371 ; SSE41-NEXT: pxor %xmm1, %xmm1
372 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
375 ; AVX1-LABEL: combine_bitwise_ops_test3b:
377 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
378 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
379 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
382 ; AVX2-LABEL: combine_bitwise_ops_test3b:
384 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
385 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
386 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
388 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
389 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
390 %xor = xor <4 x i32> %shuf1, %shuf2
394 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
395 ; SSE2-LABEL: combine_bitwise_ops_test4b:
397 ; SSE2-NEXT: andps %xmm1, %xmm0
398 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
399 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
400 ; SSE2-NEXT: movaps %xmm2, %xmm0
403 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
405 ; SSSE3-NEXT: andps %xmm1, %xmm0
406 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
407 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
408 ; SSSE3-NEXT: movaps %xmm2, %xmm0
411 ; SSE41-LABEL: combine_bitwise_ops_test4b:
413 ; SSE41-NEXT: pand %xmm1, %xmm0
414 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
417 ; AVX1-LABEL: combine_bitwise_ops_test4b:
419 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
420 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
423 ; AVX2-LABEL: combine_bitwise_ops_test4b:
425 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
426 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
428 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
429 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
430 %and = and <4 x i32> %shuf1, %shuf2
434 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
435 ; SSE2-LABEL: combine_bitwise_ops_test5b:
437 ; SSE2-NEXT: orps %xmm1, %xmm0
438 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
439 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
440 ; SSE2-NEXT: movaps %xmm2, %xmm0
443 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
445 ; SSSE3-NEXT: orps %xmm1, %xmm0
446 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
447 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
448 ; SSSE3-NEXT: movaps %xmm2, %xmm0
451 ; SSE41-LABEL: combine_bitwise_ops_test5b:
453 ; SSE41-NEXT: por %xmm1, %xmm0
454 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
457 ; AVX1-LABEL: combine_bitwise_ops_test5b:
459 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
460 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
463 ; AVX2-LABEL: combine_bitwise_ops_test5b:
465 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
466 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
468 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
469 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
470 %or = or <4 x i32> %shuf1, %shuf2
474 define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
475 ; SSE2-LABEL: combine_bitwise_ops_test6b:
477 ; SSE2-NEXT: xorps %xmm1, %xmm0
478 ; SSE2-NEXT: xorps %xmm1, %xmm1
479 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
480 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
481 ; SSE2-NEXT: movaps %xmm1, %xmm0
484 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
486 ; SSSE3-NEXT: xorps %xmm1, %xmm0
487 ; SSSE3-NEXT: xorps %xmm1, %xmm1
488 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
489 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
490 ; SSSE3-NEXT: movaps %xmm1, %xmm0
493 ; SSE41-LABEL: combine_bitwise_ops_test6b:
495 ; SSE41-NEXT: pxor %xmm1, %xmm0
496 ; SSE41-NEXT: pxor %xmm1, %xmm1
497 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
500 ; AVX1-LABEL: combine_bitwise_ops_test6b:
502 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
503 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
504 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
507 ; AVX2-LABEL: combine_bitwise_ops_test6b:
509 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
510 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
511 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
513 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
514 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
515 %xor = xor <4 x i32> %shuf1, %shuf2
519 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
520 ; SSE-LABEL: combine_bitwise_ops_test1c:
522 ; SSE-NEXT: andps %xmm1, %xmm0
523 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
526 ; AVX-LABEL: combine_bitwise_ops_test1c:
528 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
529 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
531 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
532 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
533 %and = and <4 x i32> %shuf1, %shuf2
537 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
538 ; SSE-LABEL: combine_bitwise_ops_test2c:
540 ; SSE-NEXT: orps %xmm1, %xmm0
541 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
544 ; AVX-LABEL: combine_bitwise_ops_test2c:
546 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
547 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
549 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
550 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
551 %or = or <4 x i32> %shuf1, %shuf2
555 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
556 ; SSE-LABEL: combine_bitwise_ops_test3c:
558 ; SSE-NEXT: xorps %xmm1, %xmm0
559 ; SSE-NEXT: xorps %xmm1, %xmm1
560 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
563 ; AVX-LABEL: combine_bitwise_ops_test3c:
565 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
566 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
567 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
569 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
570 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
571 %xor = xor <4 x i32> %shuf1, %shuf2
575 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
576 ; SSE-LABEL: combine_bitwise_ops_test4c:
578 ; SSE-NEXT: andps %xmm1, %xmm0
579 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
580 ; SSE-NEXT: movaps %xmm2, %xmm0
583 ; AVX-LABEL: combine_bitwise_ops_test4c:
585 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
586 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
588 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
589 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
590 %and = and <4 x i32> %shuf1, %shuf2
594 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
595 ; SSE-LABEL: combine_bitwise_ops_test5c:
597 ; SSE-NEXT: orps %xmm1, %xmm0
598 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
599 ; SSE-NEXT: movaps %xmm2, %xmm0
602 ; AVX-LABEL: combine_bitwise_ops_test5c:
604 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
605 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
607 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
608 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
609 %or = or <4 x i32> %shuf1, %shuf2
613 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
614 ; SSE-LABEL: combine_bitwise_ops_test6c:
616 ; SSE-NEXT: xorps %xmm1, %xmm0
617 ; SSE-NEXT: xorps %xmm1, %xmm1
618 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
619 ; SSE-NEXT: movaps %xmm1, %xmm0
622 ; AVX-LABEL: combine_bitwise_ops_test6c:
624 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
625 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
626 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[1,3]
628 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
629 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
630 %xor = xor <4 x i32> %shuf1, %shuf2
634 define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
635 ; SSE-LABEL: combine_nested_undef_test1:
637 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
640 ; AVX-LABEL: combine_nested_undef_test1:
642 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
644 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
645 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
649 define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
650 ; SSE-LABEL: combine_nested_undef_test2:
652 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
655 ; AVX-LABEL: combine_nested_undef_test2:
657 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
659 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
660 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
664 define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
665 ; SSE-LABEL: combine_nested_undef_test3:
667 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
670 ; AVX-LABEL: combine_nested_undef_test3:
672 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
674 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
675 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
679 define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
680 ; SSE-LABEL: combine_nested_undef_test4:
682 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
685 ; AVX1-LABEL: combine_nested_undef_test4:
687 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
690 ; AVX2-LABEL: combine_nested_undef_test4:
692 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
694 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
695 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
699 define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
700 ; SSE-LABEL: combine_nested_undef_test5:
702 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
705 ; AVX-LABEL: combine_nested_undef_test5:
707 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
709 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
710 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
714 define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
715 ; SSE-LABEL: combine_nested_undef_test6:
717 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
720 ; AVX-LABEL: combine_nested_undef_test6:
722 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
724 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
725 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
729 define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
730 ; SSE-LABEL: combine_nested_undef_test7:
732 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
735 ; AVX-LABEL: combine_nested_undef_test7:
737 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
739 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
740 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
744 define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
745 ; SSE-LABEL: combine_nested_undef_test8:
747 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
750 ; AVX-LABEL: combine_nested_undef_test8:
752 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
754 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
755 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
759 define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
760 ; SSE-LABEL: combine_nested_undef_test9:
762 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
765 ; AVX-LABEL: combine_nested_undef_test9:
767 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
769 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
770 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
774 define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
775 ; SSE-LABEL: combine_nested_undef_test10:
777 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
780 ; AVX-LABEL: combine_nested_undef_test10:
782 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
784 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
785 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
789 define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
790 ; SSE-LABEL: combine_nested_undef_test11:
792 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
795 ; AVX-LABEL: combine_nested_undef_test11:
797 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
799 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
800 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
804 define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
805 ; SSE-LABEL: combine_nested_undef_test12:
807 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
810 ; AVX1-LABEL: combine_nested_undef_test12:
812 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
815 ; AVX2-LABEL: combine_nested_undef_test12:
817 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
819 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
820 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
824 ; The following pair of shuffles is folded into vector %A.
825 define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
826 ; ALL-LABEL: combine_nested_undef_test13:
829 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
830 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
834 ; The following pair of shuffles is folded into vector %B.
835 define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
836 ; SSE-LABEL: combine_nested_undef_test14:
838 ; SSE-NEXT: movaps %xmm1, %xmm0
841 ; AVX-LABEL: combine_nested_undef_test14:
843 ; AVX-NEXT: vmovaps %xmm1, %xmm0
845 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
846 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
851 ; Verify that we don't optimize the following cases. We expect more than one shuffle.
853 ; FIXME: Many of these already don't make sense, and the rest should stop
854 ; making sense with th enew vector shuffle lowering. Revisit at least testing for
857 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
858 ; SSE-LABEL: combine_nested_undef_test15:
860 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
861 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,1]
862 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
865 ; AVX-LABEL: combine_nested_undef_test15:
867 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
868 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[3,1]
869 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
871 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
872 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
876 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
877 ; SSE2-LABEL: combine_nested_undef_test16:
879 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
880 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
881 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
884 ; SSSE3-LABEL: combine_nested_undef_test16:
886 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
887 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
888 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
891 ; SSE41-LABEL: combine_nested_undef_test16:
893 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
894 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
897 ; AVX1-LABEL: combine_nested_undef_test16:
899 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
900 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
903 ; AVX2-LABEL: combine_nested_undef_test16:
905 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
906 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
908 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
909 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
913 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
914 ; SSE-LABEL: combine_nested_undef_test17:
916 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
917 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
918 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
921 ; AVX-LABEL: combine_nested_undef_test17:
923 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
924 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
925 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
927 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
928 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
932 define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
933 ; SSE-LABEL: combine_nested_undef_test18:
935 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
938 ; AVX-LABEL: combine_nested_undef_test18:
940 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
942 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
943 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
947 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
948 ; SSE-LABEL: combine_nested_undef_test19:
950 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
951 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
952 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
955 ; AVX-LABEL: combine_nested_undef_test19:
957 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
958 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
959 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
961 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
962 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
966 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
967 ; SSE-LABEL: combine_nested_undef_test20:
969 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
970 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
973 ; AVX-LABEL: combine_nested_undef_test20:
975 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
976 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
978 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
979 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
983 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
984 ; SSE-LABEL: combine_nested_undef_test21:
986 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
987 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
988 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
991 ; AVX-LABEL: combine_nested_undef_test21:
993 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
994 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
995 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
997 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
998 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1003 ; Test that we correctly combine shuffles according to rule
1004 ; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
1006 define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
1007 ; SSE-LABEL: combine_nested_undef_test22:
1009 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1012 ; AVX-LABEL: combine_nested_undef_test22:
1014 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1016 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1017 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
1021 define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1022 ; SSE-LABEL: combine_nested_undef_test23:
1024 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1027 ; AVX-LABEL: combine_nested_undef_test23:
1029 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1031 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1032 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1036 define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1037 ; SSE-LABEL: combine_nested_undef_test24:
1039 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1042 ; AVX-LABEL: combine_nested_undef_test24:
1044 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1046 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1047 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1051 define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1052 ; SSE-LABEL: combine_nested_undef_test25:
1054 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1057 ; AVX1-LABEL: combine_nested_undef_test25:
1059 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1062 ; AVX2-LABEL: combine_nested_undef_test25:
1064 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1066 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1067 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1071 define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1072 ; SSE-LABEL: combine_nested_undef_test26:
1074 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1077 ; AVX-LABEL: combine_nested_undef_test26:
1079 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1081 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1082 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1086 define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1087 ; SSE-LABEL: combine_nested_undef_test27:
1089 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1092 ; AVX1-LABEL: combine_nested_undef_test27:
1094 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1097 ; AVX2-LABEL: combine_nested_undef_test27:
1099 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1101 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1102 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1106 define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1107 ; SSE-LABEL: combine_nested_undef_test28:
1109 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1112 ; AVX-LABEL: combine_nested_undef_test28:
1114 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1116 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1117 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1121 define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1122 ; SSE-LABEL: combine_test1:
1124 ; SSE-NEXT: movaps %xmm1, %xmm0
1127 ; AVX-LABEL: combine_test1:
1129 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1131 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1132 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1136 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1137 ; SSE2-LABEL: combine_test2:
1139 ; SSE2-NEXT: movss %xmm0, %xmm1
1140 ; SSE2-NEXT: movaps %xmm1, %xmm0
1143 ; SSSE3-LABEL: combine_test2:
1145 ; SSSE3-NEXT: movss %xmm0, %xmm1
1146 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1149 ; SSE41-LABEL: combine_test2:
1151 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1154 ; AVX-LABEL: combine_test2:
1156 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1158 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1159 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1163 define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1164 ; SSE-LABEL: combine_test3:
1166 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1169 ; AVX-LABEL: combine_test3:
1171 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1173 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1174 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1178 define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1179 ; SSE-LABEL: combine_test4:
1181 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1182 ; SSE-NEXT: movapd %xmm1, %xmm0
1185 ; AVX-LABEL: combine_test4:
1187 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1189 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1190 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1194 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1195 ; SSE2-LABEL: combine_test5:
1197 ; SSE2-NEXT: movaps %xmm1, %xmm2
1198 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1199 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1200 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1201 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1202 ; SSE2-NEXT: movaps %xmm2, %xmm0
1205 ; SSSE3-LABEL: combine_test5:
1207 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1208 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1209 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1210 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1211 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1212 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1215 ; SSE41-LABEL: combine_test5:
1217 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1220 ; AVX-LABEL: combine_test5:
1222 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1224 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1225 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1229 define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1230 ; SSE-LABEL: combine_test6:
1232 ; SSE-NEXT: movaps %xmm1, %xmm0
1235 ; AVX-LABEL: combine_test6:
1237 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1239 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1240 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1244 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1245 ; SSE2-LABEL: combine_test7:
1247 ; SSE2-NEXT: movss %xmm0, %xmm1
1248 ; SSE2-NEXT: movaps %xmm1, %xmm0
1251 ; SSSE3-LABEL: combine_test7:
1253 ; SSSE3-NEXT: movss %xmm0, %xmm1
1254 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1257 ; SSE41-LABEL: combine_test7:
1259 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1262 ; AVX1-LABEL: combine_test7:
1264 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1267 ; AVX2-LABEL: combine_test7:
1269 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1271 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1272 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1276 define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1277 ; SSE-LABEL: combine_test8:
1279 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1282 ; AVX-LABEL: combine_test8:
1284 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1286 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1287 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1291 define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1292 ; SSE-LABEL: combine_test9:
1294 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1295 ; SSE-NEXT: movdqa %xmm1, %xmm0
1298 ; AVX-LABEL: combine_test9:
1300 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1302 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1303 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1307 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1308 ; SSE2-LABEL: combine_test10:
1310 ; SSE2-NEXT: movaps %xmm1, %xmm2
1311 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1312 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1313 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1314 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1315 ; SSE2-NEXT: movaps %xmm2, %xmm0
1318 ; SSSE3-LABEL: combine_test10:
1320 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1321 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1322 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1323 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1324 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1325 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1328 ; SSE41-LABEL: combine_test10:
1330 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1333 ; AVX1-LABEL: combine_test10:
1335 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1338 ; AVX2-LABEL: combine_test10:
1340 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1342 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1343 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1347 define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1348 ; ALL-LABEL: combine_test11:
1351 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1352 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1356 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1357 ; SSE2-LABEL: combine_test12:
1359 ; SSE2-NEXT: movss %xmm0, %xmm1
1360 ; SSE2-NEXT: movaps %xmm1, %xmm0
1363 ; SSSE3-LABEL: combine_test12:
1365 ; SSSE3-NEXT: movss %xmm0, %xmm1
1366 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1369 ; SSE41-LABEL: combine_test12:
1371 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1374 ; AVX-LABEL: combine_test12:
1376 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1378 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1379 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1383 define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1384 ; SSE-LABEL: combine_test13:
1386 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1389 ; AVX-LABEL: combine_test13:
1391 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1393 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1394 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1398 define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1399 ; SSE-LABEL: combine_test14:
1401 ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1404 ; AVX-LABEL: combine_test14:
1406 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1408 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1409 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1413 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1414 ; SSE2-LABEL: combine_test15:
1416 ; SSE2-NEXT: movaps %xmm0, %xmm2
1417 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1418 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1419 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1420 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1423 ; SSSE3-LABEL: combine_test15:
1425 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1426 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1427 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1428 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1429 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1432 ; SSE41-LABEL: combine_test15:
1434 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1437 ; AVX-LABEL: combine_test15:
1439 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1441 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1442 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1446 define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1447 ; ALL-LABEL: combine_test16:
1450 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1451 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1455 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1456 ; SSE2-LABEL: combine_test17:
1458 ; SSE2-NEXT: movss %xmm0, %xmm1
1459 ; SSE2-NEXT: movaps %xmm1, %xmm0
1462 ; SSSE3-LABEL: combine_test17:
1464 ; SSSE3-NEXT: movss %xmm0, %xmm1
1465 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1468 ; SSE41-LABEL: combine_test17:
1470 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1473 ; AVX1-LABEL: combine_test17:
1475 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1478 ; AVX2-LABEL: combine_test17:
1480 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1482 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1483 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1487 define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1488 ; SSE-LABEL: combine_test18:
1490 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1493 ; AVX-LABEL: combine_test18:
1495 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1497 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1498 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1502 define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1503 ; SSE-LABEL: combine_test19:
1505 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1508 ; AVX-LABEL: combine_test19:
1510 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1512 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1513 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1517 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1518 ; SSE2-LABEL: combine_test20:
1520 ; SSE2-NEXT: movaps %xmm0, %xmm2
1521 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1522 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1523 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1524 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1527 ; SSSE3-LABEL: combine_test20:
1529 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1530 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1531 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1532 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1533 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1536 ; SSE41-LABEL: combine_test20:
1538 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1541 ; AVX1-LABEL: combine_test20:
1543 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1546 ; AVX2-LABEL: combine_test20:
1548 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1550 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1551 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1556 ; Check some negative cases.
1557 ; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1559 define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1560 ; SSE-LABEL: combine_test1b:
1562 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,2,0]
1563 ; SSE-NEXT: movaps %xmm1, %xmm0
1566 ; AVX-LABEL: combine_test1b:
1568 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[0,1,2,0]
1570 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1571 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1575 define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1576 ; SSE2-LABEL: combine_test2b:
1578 ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0,0]
1579 ; SSE2-NEXT: movaps %xmm1, %xmm0
1582 ; SSSE3-LABEL: combine_test2b:
1584 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
1585 ; SSSE3-NEXT: movapd %xmm1, %xmm0
1588 ; SSE41-LABEL: combine_test2b:
1590 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
1591 ; SSE41-NEXT: movapd %xmm1, %xmm0
1594 ; AVX-LABEL: combine_test2b:
1596 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0,0]
1598 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1599 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
1603 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1604 ; SSE-LABEL: combine_test3b:
1606 ; SSE-NEXT: movaps %xmm1, %xmm2
1607 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[3,0]
1608 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1609 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1610 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1613 ; AVX-LABEL: combine_test3b:
1615 ; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,0],xmm0[3,0]
1616 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1617 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1618 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1620 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1621 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1625 define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1626 ; SSE-LABEL: combine_test4b:
1628 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
1629 ; SSE-NEXT: movaps %xmm1, %xmm0
1632 ; AVX-LABEL: combine_test4b:
1634 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[1,1,2,3]
1636 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1637 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1642 ; Verify that we correctly fold shuffles even when we use illegal vector types.
1644 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1645 ; SSE2-LABEL: combine_test1c:
1647 ; SSE2-NEXT: movd (%rdi), %xmm1
1648 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1649 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1650 ; SSE2-NEXT: movd (%rsi), %xmm0
1651 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1652 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1653 ; SSE2-NEXT: movss %xmm1, %xmm0
1656 ; SSSE3-LABEL: combine_test1c:
1658 ; SSSE3-NEXT: movd (%rdi), %xmm1
1659 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1660 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1661 ; SSSE3-NEXT: movd (%rsi), %xmm0
1662 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1663 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1664 ; SSSE3-NEXT: movss %xmm1, %xmm0
1667 ; SSE41-LABEL: combine_test1c:
1669 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1670 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1671 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1674 ; AVX1-LABEL: combine_test1c:
1676 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1677 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1678 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1681 ; AVX2-LABEL: combine_test1c:
1683 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1684 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1685 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1687 %A = load <4 x i8>* %a
1688 %B = load <4 x i8>* %b
1689 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1690 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1694 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1695 ; SSE2-LABEL: combine_test2c:
1697 ; SSE2-NEXT: movd (%rdi), %xmm0
1698 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1699 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1700 ; SSE2-NEXT: movd (%rsi), %xmm1
1701 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1702 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1703 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1706 ; SSSE3-LABEL: combine_test2c:
1708 ; SSSE3-NEXT: movd (%rdi), %xmm0
1709 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1710 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1711 ; SSSE3-NEXT: movd (%rsi), %xmm1
1712 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1713 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1714 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1717 ; SSE41-LABEL: combine_test2c:
1719 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm0
1720 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm1
1721 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1724 ; AVX-LABEL: combine_test2c:
1726 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1727 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1728 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1730 %A = load <4 x i8>* %a
1731 %B = load <4 x i8>* %b
1732 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1733 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1737 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1738 ; SSE2-LABEL: combine_test3c:
1740 ; SSE2-NEXT: movd (%rdi), %xmm1
1741 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1742 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1743 ; SSE2-NEXT: movd (%rsi), %xmm0
1744 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1745 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1746 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1749 ; SSSE3-LABEL: combine_test3c:
1751 ; SSSE3-NEXT: movd (%rdi), %xmm1
1752 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1753 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1754 ; SSSE3-NEXT: movd (%rsi), %xmm0
1755 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1756 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1757 ; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1760 ; SSE41-LABEL: combine_test3c:
1762 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1763 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1764 ; SSE41-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1767 ; AVX-LABEL: combine_test3c:
1769 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1770 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1771 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1773 %A = load <4 x i8>* %a
1774 %B = load <4 x i8>* %b
1775 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1776 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1780 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
1781 ; SSE2-LABEL: combine_test4c:
1783 ; SSE2-NEXT: movd (%rdi), %xmm1
1784 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1785 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1786 ; SSE2-NEXT: movd (%rsi), %xmm2
1787 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1788 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1789 ; SSE2-NEXT: movdqa %xmm2, %xmm0
1790 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1791 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1792 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1793 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1796 ; SSSE3-LABEL: combine_test4c:
1798 ; SSSE3-NEXT: movd (%rdi), %xmm1
1799 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1800 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1801 ; SSSE3-NEXT: movd (%rsi), %xmm2
1802 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1803 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1804 ; SSSE3-NEXT: movdqa %xmm2, %xmm0
1805 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1806 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1807 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1808 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1811 ; SSE41-LABEL: combine_test4c:
1813 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1814 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1815 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1818 ; AVX1-LABEL: combine_test4c:
1820 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1821 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1822 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1825 ; AVX2-LABEL: combine_test4c:
1827 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1828 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1829 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1831 %A = load <4 x i8>* %a
1832 %B = load <4 x i8>* %b
1833 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1834 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1839 ; The following test cases are generated from this C++ code
1841 ;__m128 blend_01(__m128 a, __m128 b)
1844 ; s = _mm_blend_ps( s, b, 1<<0 );
1845 ; s = _mm_blend_ps( s, b, 1<<1 );
1849 ;__m128 blend_02(__m128 a, __m128 b)
1852 ; s = _mm_blend_ps( s, b, 1<<0 );
1853 ; s = _mm_blend_ps( s, b, 1<<2 );
1857 ;__m128 blend_123(__m128 a, __m128 b)
1860 ; s = _mm_blend_ps( s, b, 1<<1 );
1861 ; s = _mm_blend_ps( s, b, 1<<2 );
1862 ; s = _mm_blend_ps( s, b, 1<<3 );
1866 ; Ideally, we should collapse the following shuffles into a single one.
1868 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
1869 ; SSE2-LABEL: combine_blend_01:
1871 ; SSE2-NEXT: movsd %xmm1, %xmm0
1874 ; SSSE3-LABEL: combine_blend_01:
1876 ; SSSE3-NEXT: movsd %xmm1, %xmm0
1879 ; SSE41-LABEL: combine_blend_01:
1881 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1884 ; AVX-LABEL: combine_blend_01:
1886 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1888 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
1889 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1890 ret <4 x float> %shuffle6
1893 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
1894 ; SSE2-LABEL: combine_blend_02:
1896 ; SSE2-NEXT: movss %xmm1, %xmm0
1897 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1898 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1901 ; SSSE3-LABEL: combine_blend_02:
1903 ; SSSE3-NEXT: movss %xmm1, %xmm0
1904 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1905 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1908 ; SSE41-LABEL: combine_blend_02:
1910 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1913 ; AVX-LABEL: combine_blend_02:
1915 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1917 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
1918 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1919 ret <4 x float> %shuffle6
1922 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
1923 ; SSE2-LABEL: combine_blend_123:
1925 ; SSE2-NEXT: movss %xmm0, %xmm1
1926 ; SSE2-NEXT: movaps %xmm1, %xmm0
1929 ; SSSE3-LABEL: combine_blend_123:
1931 ; SSSE3-NEXT: movss %xmm0, %xmm1
1932 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1935 ; SSE41-LABEL: combine_blend_123:
1937 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1940 ; AVX-LABEL: combine_blend_123:
1942 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1944 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
1945 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
1946 %shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1947 ret <4 x float> %shuffle12
1950 define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
1951 ; SSE-LABEL: combine_test_movhl_1:
1953 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1954 ; SSE-NEXT: movdqa %xmm1, %xmm0
1957 ; AVX-LABEL: combine_test_movhl_1:
1959 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1961 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
1962 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
1966 define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
1967 ; SSE-LABEL: combine_test_movhl_2:
1969 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1970 ; SSE-NEXT: movdqa %xmm1, %xmm0
1973 ; AVX-LABEL: combine_test_movhl_2:
1975 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1977 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
1978 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
1982 define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
1983 ; SSE-LABEL: combine_test_movhl_3:
1985 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1986 ; SSE-NEXT: movdqa %xmm1, %xmm0
1989 ; AVX-LABEL: combine_test_movhl_3:
1991 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1993 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
1994 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>
1999 ; Verify that we fold shuffles according to rule:
2000 ; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
2002 define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
2003 ; SSE2-LABEL: combine_undef_input_test1:
2005 ; SSE2-NEXT: movsd %xmm1, %xmm0
2008 ; SSSE3-LABEL: combine_undef_input_test1:
2010 ; SSSE3-NEXT: movsd %xmm1, %xmm0
2013 ; SSE41-LABEL: combine_undef_input_test1:
2015 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2018 ; AVX-LABEL: combine_undef_input_test1:
2020 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2022 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2023 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2027 define <4 x float> @combine_undef_input_test2(<4 x float> %a, <4 x float> %b) {
2028 ; SSE-LABEL: combine_undef_input_test2:
2030 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2033 ; AVX-LABEL: combine_undef_input_test2:
2035 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2037 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2038 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2042 define <4 x float> @combine_undef_input_test3(<4 x float> %a, <4 x float> %b) {
2043 ; SSE-LABEL: combine_undef_input_test3:
2045 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2048 ; AVX-LABEL: combine_undef_input_test3:
2050 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2052 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2053 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2057 define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
2058 ; SSE-LABEL: combine_undef_input_test4:
2060 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2061 ; SSE-NEXT: movapd %xmm1, %xmm0
2064 ; AVX-LABEL: combine_undef_input_test4:
2066 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2068 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2069 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2073 define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
2074 ; SSE2-LABEL: combine_undef_input_test5:
2076 ; SSE2-NEXT: movsd %xmm0, %xmm1
2077 ; SSE2-NEXT: movaps %xmm1, %xmm0
2080 ; SSSE3-LABEL: combine_undef_input_test5:
2082 ; SSSE3-NEXT: movsd %xmm0, %xmm1
2083 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2086 ; SSE41-LABEL: combine_undef_input_test5:
2088 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2091 ; AVX-LABEL: combine_undef_input_test5:
2093 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2095 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2096 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2101 ; Verify that we fold shuffles according to rule:
2102 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2104 define <4 x float> @combine_undef_input_test6(<4 x float> %a) {
2105 ; ALL-LABEL: combine_undef_input_test6:
2108 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2109 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2113 define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
2114 ; SSE2-LABEL: combine_undef_input_test7:
2116 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2119 ; SSSE3-LABEL: combine_undef_input_test7:
2121 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2124 ; SSE41-LABEL: combine_undef_input_test7:
2126 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2129 ; AVX-LABEL: combine_undef_input_test7:
2131 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2133 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2134 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2138 define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
2139 ; SSE2-LABEL: combine_undef_input_test8:
2141 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2144 ; SSSE3-LABEL: combine_undef_input_test8:
2146 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2149 ; SSE41-LABEL: combine_undef_input_test8:
2151 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2154 ; AVX-LABEL: combine_undef_input_test8:
2156 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2158 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2159 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2163 define <4 x float> @combine_undef_input_test9(<4 x float> %a) {
2164 ; SSE-LABEL: combine_undef_input_test9:
2166 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2169 ; AVX-LABEL: combine_undef_input_test9:
2171 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2173 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2174 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2178 define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
2179 ; ALL-LABEL: combine_undef_input_test10:
2182 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2183 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2187 define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
2188 ; SSE2-LABEL: combine_undef_input_test11:
2190 ; SSE2-NEXT: movsd %xmm1, %xmm0
2193 ; SSSE3-LABEL: combine_undef_input_test11:
2195 ; SSSE3-NEXT: movsd %xmm1, %xmm0
2198 ; SSE41-LABEL: combine_undef_input_test11:
2200 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2203 ; AVX-LABEL: combine_undef_input_test11:
2205 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2207 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2208 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 6>
2212 define <4 x float> @combine_undef_input_test12(<4 x float> %a, <4 x float> %b) {
2213 ; SSE-LABEL: combine_undef_input_test12:
2215 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2218 ; AVX-LABEL: combine_undef_input_test12:
2220 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2222 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2223 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2227 define <4 x float> @combine_undef_input_test13(<4 x float> %a, <4 x float> %b) {
2228 ; SSE-LABEL: combine_undef_input_test13:
2230 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2233 ; AVX-LABEL: combine_undef_input_test13:
2235 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2237 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2238 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 5, i32 0, i32 5>
2242 define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
2243 ; SSE-LABEL: combine_undef_input_test14:
2245 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2246 ; SSE-NEXT: movapd %xmm1, %xmm0
2249 ; AVX-LABEL: combine_undef_input_test14:
2251 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2253 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2254 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2258 define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
2259 ; SSE2-LABEL: combine_undef_input_test15:
2261 ; SSE2-NEXT: movsd %xmm0, %xmm1
2262 ; SSE2-NEXT: movaps %xmm1, %xmm0
2265 ; SSSE3-LABEL: combine_undef_input_test15:
2267 ; SSSE3-NEXT: movsd %xmm0, %xmm1
2268 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2271 ; SSE41-LABEL: combine_undef_input_test15:
2273 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2276 ; AVX-LABEL: combine_undef_input_test15:
2278 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2280 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2281 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2286 ; Verify that shuffles are canonicalized according to rules:
2287 ; shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
2289 ; This allows to trigger the following combine rule:
2290 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2292 ; As a result, all the shuffle pairs in each function below should be
2293 ; combined into a single legal shuffle operation.
2295 define <4 x float> @combine_undef_input_test16(<4 x float> %a) {
2296 ; ALL-LABEL: combine_undef_input_test16:
2299 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2300 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
2304 define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
2305 ; SSE2-LABEL: combine_undef_input_test17:
2307 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2310 ; SSSE3-LABEL: combine_undef_input_test17:
2312 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2315 ; SSE41-LABEL: combine_undef_input_test17:
2317 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2320 ; AVX-LABEL: combine_undef_input_test17:
2322 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2324 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2325 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2329 define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
2330 ; SSE2-LABEL: combine_undef_input_test18:
2332 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2335 ; SSSE3-LABEL: combine_undef_input_test18:
2337 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2340 ; SSE41-LABEL: combine_undef_input_test18:
2342 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2345 ; AVX-LABEL: combine_undef_input_test18:
2347 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2349 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2350 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
2354 define <4 x float> @combine_undef_input_test19(<4 x float> %a) {
2355 ; SSE-LABEL: combine_undef_input_test19:
2357 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2360 ; AVX-LABEL: combine_undef_input_test19:
2362 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2364 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2365 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2369 define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
2370 ; ALL-LABEL: combine_undef_input_test20:
2373 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2374 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2378 ; These tests are designed to test the ability to combine away unnecessary
2379 ; operations feeding into a shuffle. The AVX cases are the important ones as
2380 ; they leverage operations which cannot be done naturally on the entire vector
2381 ; and thus are decomposed into multiple smaller operations.
2383 define <8 x i32> @combine_unneeded_subvector1(<8 x i32> %a) {
2384 ; SSE-LABEL: combine_unneeded_subvector1:
2386 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2387 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
2388 ; SSE-NEXT: movdqa %xmm0, %xmm1
2391 ; AVX1-LABEL: combine_unneeded_subvector1:
2393 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2394 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2395 ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2396 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2399 ; AVX2-LABEL: combine_unneeded_subvector1:
2401 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2402 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
2403 ; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
2405 %b = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2406 %c = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
2410 define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
2411 ; SSE-LABEL: combine_unneeded_subvector2:
2413 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2414 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,2,1,0]
2415 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
2418 ; AVX1-LABEL: combine_unneeded_subvector2:
2420 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2421 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2422 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2423 ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2424 ; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2427 ; AVX2-LABEL: combine_unneeded_subvector2:
2429 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2430 ; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2431 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2433 %c = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2434 %d = shufflevector <8 x i32> %b, <8 x i32> %c, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>
2438 define <4 x float> @combine_insertps1(<4 x float> %a, <4 x float> %b) {
2439 ; SSE41-LABEL: combine_insertps1:
2441 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2444 ; AVX-LABEL: combine_insertps1:
2446 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2449 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 6, i32 2, i32 4>
2450 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 5, i32 1, i32 6, i32 3>
2454 define <4 x float> @combine_insertps2(<4 x float> %a, <4 x float> %b) {
2455 ; SSE41-LABEL: combine_insertps2:
2457 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2460 ; AVX-LABEL: combine_insertps2:
2462 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2465 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 1, i32 6, i32 7>
2466 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2470 define <4 x float> @combine_insertps3(<4 x float> %a, <4 x float> %b) {
2471 ; SSE41-LABEL: combine_insertps3:
2473 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2476 ; AVX-LABEL: combine_insertps3:
2478 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2481 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2482 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 5, i32 3>
2486 define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) {
2487 ; SSE41-LABEL: combine_insertps4:
2489 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2492 ; AVX-LABEL: combine_insertps4:
2494 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2497 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2498 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 6, i32 5>