1 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7 ; Verify that the DAG combiner correctly folds bitwise operations across
8 ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
9 ; basic and always-safe patterns. Also test that the DAG combiner will combine
10 ; target-specific shuffle instructions where reasonable.
12 target triple = "x86_64-unknown-unknown"
14 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
15 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
16 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
18 define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
19 ; ALL-LABEL: combine_pshufd1:
20 ; ALL: # BB#0: # %entry
23 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
24 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
28 define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
29 ; ALL-LABEL: combine_pshufd2:
30 ; ALL: # BB#0: # %entry
33 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
34 %b.cast = bitcast <4 x i32> %b to <8 x i16>
35 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
36 %c.cast = bitcast <8 x i16> %c to <4 x i32>
37 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
41 define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
42 ; ALL-LABEL: combine_pshufd3:
43 ; ALL: # BB#0: # %entry
46 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
47 %b.cast = bitcast <4 x i32> %b to <8 x i16>
48 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
49 %c.cast = bitcast <8 x i16> %c to <4 x i32>
50 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
54 define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
55 ; SSE-LABEL: combine_pshufd4:
56 ; SSE: # BB#0: # %entry
57 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
60 ; AVX-LABEL: combine_pshufd4:
61 ; AVX: # BB#0: # %entry
62 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
65 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
66 %b.cast = bitcast <4 x i32> %b to <8 x i16>
67 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
68 %c.cast = bitcast <8 x i16> %c to <4 x i32>
69 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
73 define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
74 ; SSE-LABEL: combine_pshufd5:
75 ; SSE: # BB#0: # %entry
76 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
79 ; AVX-LABEL: combine_pshufd5:
80 ; AVX: # BB#0: # %entry
81 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
84 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
85 %b.cast = bitcast <4 x i32> %b to <8 x i16>
86 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
87 %c.cast = bitcast <8 x i16> %c to <4 x i32>
88 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
92 define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
93 ; SSE-LABEL: combine_pshufd6:
94 ; SSE: # BB#0: # %entry
95 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
98 ; AVX-LABEL: combine_pshufd6:
99 ; AVX: # BB#0: # %entry
100 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
103 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
104 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
108 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
109 ; ALL-LABEL: combine_pshuflw1:
110 ; ALL: # BB#0: # %entry
113 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
114 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
118 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
119 ; ALL-LABEL: combine_pshuflw2:
120 ; ALL: # BB#0: # %entry
123 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
124 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
125 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
129 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
130 ; SSE-LABEL: combine_pshuflw3:
131 ; SSE: # BB#0: # %entry
132 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
135 ; AVX-LABEL: combine_pshuflw3:
136 ; AVX: # BB#0: # %entry
137 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
140 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
141 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
142 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
146 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
147 ; SSE-LABEL: combine_pshufhw1:
148 ; SSE: # BB#0: # %entry
149 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
152 ; AVX-LABEL: combine_pshufhw1:
153 ; AVX: # BB#0: # %entry
154 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
157 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
158 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
159 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
163 define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164 ; SSE-LABEL: combine_bitwise_ops_test1:
166 ; SSE-NEXT: pand %xmm1, %xmm0
167 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
170 ; AVX-LABEL: combine_bitwise_ops_test1:
172 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
173 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
175 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
176 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177 %and = and <4 x i32> %shuf1, %shuf2
181 define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
182 ; SSE-LABEL: combine_bitwise_ops_test2:
184 ; SSE-NEXT: por %xmm1, %xmm0
185 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
188 ; AVX-LABEL: combine_bitwise_ops_test2:
190 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
191 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
193 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
194 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195 %or = or <4 x i32> %shuf1, %shuf2
199 define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
200 ; SSE-LABEL: combine_bitwise_ops_test3:
202 ; SSE-NEXT: pxor %xmm1, %xmm0
203 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
206 ; AVX-LABEL: combine_bitwise_ops_test3:
208 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
209 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
211 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
212 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213 %xor = xor <4 x i32> %shuf1, %shuf2
217 define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218 ; SSE-LABEL: combine_bitwise_ops_test4:
220 ; SSE-NEXT: pand %xmm1, %xmm0
221 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
224 ; AVX-LABEL: combine_bitwise_ops_test4:
226 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
227 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
229 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
230 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231 %and = and <4 x i32> %shuf1, %shuf2
235 define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
236 ; SSE-LABEL: combine_bitwise_ops_test5:
238 ; SSE-NEXT: por %xmm1, %xmm0
239 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
242 ; AVX-LABEL: combine_bitwise_ops_test5:
244 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
245 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
247 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
248 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249 %or = or <4 x i32> %shuf1, %shuf2
253 define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
254 ; SSE-LABEL: combine_bitwise_ops_test6:
256 ; SSE-NEXT: pxor %xmm1, %xmm0
257 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
260 ; AVX-LABEL: combine_bitwise_ops_test6:
262 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
263 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
265 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
266 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267 %xor = xor <4 x i32> %shuf1, %shuf2
272 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
273 ; are not performing a swizzle operations.
275 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
276 ; SSE2-LABEL: combine_bitwise_ops_test1b:
278 ; SSE2-NEXT: andps %xmm1, %xmm0
279 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
280 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
283 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
285 ; SSSE3-NEXT: andps %xmm1, %xmm0
286 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
287 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
290 ; SSE41-LABEL: combine_bitwise_ops_test1b:
292 ; SSE41-NEXT: pand %xmm1, %xmm0
293 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
296 ; AVX1-LABEL: combine_bitwise_ops_test1b:
298 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
299 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
302 ; AVX2-LABEL: combine_bitwise_ops_test1b:
304 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
305 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
307 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
308 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
309 %and = and <4 x i32> %shuf1, %shuf2
313 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
314 ; SSE2-LABEL: combine_bitwise_ops_test2b:
316 ; SSE2-NEXT: orps %xmm1, %xmm0
317 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
318 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
321 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
323 ; SSSE3-NEXT: orps %xmm1, %xmm0
324 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
325 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
328 ; SSE41-LABEL: combine_bitwise_ops_test2b:
330 ; SSE41-NEXT: por %xmm1, %xmm0
331 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
334 ; AVX1-LABEL: combine_bitwise_ops_test2b:
336 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
337 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
340 ; AVX2-LABEL: combine_bitwise_ops_test2b:
342 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
343 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
345 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
346 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
347 %or = or <4 x i32> %shuf1, %shuf2
351 define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
352 ; SSE2-LABEL: combine_bitwise_ops_test3b:
354 ; SSE2-NEXT: xorps %xmm1, %xmm0
355 ; SSE2-NEXT: xorps %xmm1, %xmm1
356 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
357 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
360 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
362 ; SSSE3-NEXT: xorps %xmm1, %xmm0
363 ; SSSE3-NEXT: xorps %xmm1, %xmm1
364 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
365 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
368 ; SSE41-LABEL: combine_bitwise_ops_test3b:
370 ; SSE41-NEXT: pxor %xmm1, %xmm0
371 ; SSE41-NEXT: pxor %xmm1, %xmm1
372 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
373 ; SSE41-NEXT: movdqa %xmm1, %xmm0
376 ; AVX1-LABEL: combine_bitwise_ops_test3b:
378 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
379 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
380 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
383 ; AVX2-LABEL: combine_bitwise_ops_test3b:
385 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
386 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
387 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
389 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
390 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
391 %xor = xor <4 x i32> %shuf1, %shuf2
395 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
396 ; SSE2-LABEL: combine_bitwise_ops_test4b:
398 ; SSE2-NEXT: andps %xmm1, %xmm0
399 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
400 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
401 ; SSE2-NEXT: movaps %xmm2, %xmm0
404 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
406 ; SSSE3-NEXT: andps %xmm1, %xmm0
407 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
408 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
409 ; SSSE3-NEXT: movaps %xmm2, %xmm0
412 ; SSE41-LABEL: combine_bitwise_ops_test4b:
414 ; SSE41-NEXT: pand %xmm1, %xmm0
415 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
418 ; AVX1-LABEL: combine_bitwise_ops_test4b:
420 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
421 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
424 ; AVX2-LABEL: combine_bitwise_ops_test4b:
426 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
427 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
429 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
430 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
431 %and = and <4 x i32> %shuf1, %shuf2
435 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
436 ; SSE2-LABEL: combine_bitwise_ops_test5b:
438 ; SSE2-NEXT: orps %xmm1, %xmm0
439 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
440 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
441 ; SSE2-NEXT: movaps %xmm2, %xmm0
444 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
446 ; SSSE3-NEXT: orps %xmm1, %xmm0
447 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
448 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
449 ; SSSE3-NEXT: movaps %xmm2, %xmm0
452 ; SSE41-LABEL: combine_bitwise_ops_test5b:
454 ; SSE41-NEXT: por %xmm1, %xmm0
455 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
458 ; AVX1-LABEL: combine_bitwise_ops_test5b:
460 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
461 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
464 ; AVX2-LABEL: combine_bitwise_ops_test5b:
466 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
467 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
469 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
470 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
471 %or = or <4 x i32> %shuf1, %shuf2
475 define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
476 ; SSE2-LABEL: combine_bitwise_ops_test6b:
478 ; SSE2-NEXT: xorps %xmm1, %xmm0
479 ; SSE2-NEXT: xorps %xmm1, %xmm1
480 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
481 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
482 ; SSE2-NEXT: movaps %xmm1, %xmm0
485 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
487 ; SSSE3-NEXT: xorps %xmm1, %xmm0
488 ; SSSE3-NEXT: xorps %xmm1, %xmm1
489 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
490 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
491 ; SSSE3-NEXT: movaps %xmm1, %xmm0
494 ; SSE41-LABEL: combine_bitwise_ops_test6b:
496 ; SSE41-NEXT: pxor %xmm1, %xmm0
497 ; SSE41-NEXT: pxor %xmm1, %xmm1
498 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
499 ; SSE41-NEXT: movdqa %xmm1, %xmm0
502 ; AVX1-LABEL: combine_bitwise_ops_test6b:
504 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
505 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
506 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
509 ; AVX2-LABEL: combine_bitwise_ops_test6b:
511 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
512 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
513 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
515 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
516 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
517 %xor = xor <4 x i32> %shuf1, %shuf2
521 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
522 ; SSE-LABEL: combine_bitwise_ops_test1c:
524 ; SSE-NEXT: andps %xmm1, %xmm0
525 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
528 ; AVX-LABEL: combine_bitwise_ops_test1c:
530 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
531 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
533 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
534 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
535 %and = and <4 x i32> %shuf1, %shuf2
539 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
540 ; SSE-LABEL: combine_bitwise_ops_test2c:
542 ; SSE-NEXT: orps %xmm1, %xmm0
543 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
546 ; AVX-LABEL: combine_bitwise_ops_test2c:
548 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
549 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
551 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
552 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
553 %or = or <4 x i32> %shuf1, %shuf2
557 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
558 ; SSE-LABEL: combine_bitwise_ops_test3c:
560 ; SSE-NEXT: xorps %xmm1, %xmm0
561 ; SSE-NEXT: xorps %xmm1, %xmm1
562 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
565 ; AVX-LABEL: combine_bitwise_ops_test3c:
567 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
568 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
569 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
571 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
572 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
573 %xor = xor <4 x i32> %shuf1, %shuf2
577 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
578 ; SSE-LABEL: combine_bitwise_ops_test4c:
580 ; SSE-NEXT: andps %xmm1, %xmm0
581 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
582 ; SSE-NEXT: movaps %xmm2, %xmm0
585 ; AVX-LABEL: combine_bitwise_ops_test4c:
587 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
588 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
590 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
591 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
592 %and = and <4 x i32> %shuf1, %shuf2
596 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
597 ; SSE-LABEL: combine_bitwise_ops_test5c:
599 ; SSE-NEXT: orps %xmm1, %xmm0
600 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
601 ; SSE-NEXT: movaps %xmm2, %xmm0
604 ; AVX-LABEL: combine_bitwise_ops_test5c:
606 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
607 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
609 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
610 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
611 %or = or <4 x i32> %shuf1, %shuf2
615 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
616 ; SSE-LABEL: combine_bitwise_ops_test6c:
618 ; SSE-NEXT: xorps %xmm1, %xmm0
619 ; SSE-NEXT: xorps %xmm1, %xmm1
620 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
621 ; SSE-NEXT: movaps %xmm1, %xmm0
624 ; AVX-LABEL: combine_bitwise_ops_test6c:
626 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
627 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
628 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[1,3]
630 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
631 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
632 %xor = xor <4 x i32> %shuf1, %shuf2
636 define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
637 ; SSE-LABEL: combine_nested_undef_test1:
639 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
642 ; AVX-LABEL: combine_nested_undef_test1:
644 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
646 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
647 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
651 define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
652 ; SSE-LABEL: combine_nested_undef_test2:
654 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
657 ; AVX-LABEL: combine_nested_undef_test2:
659 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
661 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
662 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
666 define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
667 ; SSE-LABEL: combine_nested_undef_test3:
669 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
672 ; AVX-LABEL: combine_nested_undef_test3:
674 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
676 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
677 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
681 define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
682 ; SSE-LABEL: combine_nested_undef_test4:
684 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
687 ; AVX1-LABEL: combine_nested_undef_test4:
689 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
692 ; AVX2-LABEL: combine_nested_undef_test4:
694 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
696 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
697 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
701 define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
702 ; SSE-LABEL: combine_nested_undef_test5:
704 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
707 ; AVX-LABEL: combine_nested_undef_test5:
709 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
711 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
712 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
716 define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
717 ; SSE-LABEL: combine_nested_undef_test6:
719 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
722 ; AVX-LABEL: combine_nested_undef_test6:
724 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
726 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
727 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
731 define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
732 ; SSE-LABEL: combine_nested_undef_test7:
734 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
737 ; AVX-LABEL: combine_nested_undef_test7:
739 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
741 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
742 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
746 define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
747 ; SSE-LABEL: combine_nested_undef_test8:
749 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
752 ; AVX-LABEL: combine_nested_undef_test8:
754 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
756 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
757 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
761 define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
762 ; SSE-LABEL: combine_nested_undef_test9:
764 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
767 ; AVX-LABEL: combine_nested_undef_test9:
769 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
771 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
772 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
776 define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
777 ; SSE-LABEL: combine_nested_undef_test10:
779 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
782 ; AVX-LABEL: combine_nested_undef_test10:
784 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
786 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
787 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
791 define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
792 ; SSE-LABEL: combine_nested_undef_test11:
794 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
797 ; AVX-LABEL: combine_nested_undef_test11:
799 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
801 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
802 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
806 define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
807 ; SSE-LABEL: combine_nested_undef_test12:
809 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
812 ; AVX1-LABEL: combine_nested_undef_test12:
814 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
817 ; AVX2-LABEL: combine_nested_undef_test12:
819 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
821 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
822 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
826 ; The following pair of shuffles is folded into vector %A.
827 define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
828 ; ALL-LABEL: combine_nested_undef_test13:
831 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
832 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
836 ; The following pair of shuffles is folded into vector %B.
837 define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
838 ; SSE-LABEL: combine_nested_undef_test14:
840 ; SSE-NEXT: movaps %xmm1, %xmm0
843 ; AVX-LABEL: combine_nested_undef_test14:
845 ; AVX-NEXT: vmovaps %xmm1, %xmm0
847 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
848 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
853 ; Verify that we don't optimize the following cases. We expect more than one shuffle.
855 ; FIXME: Many of these already don't make sense, and the rest should stop
856 ; making sense with th enew vector shuffle lowering. Revisit at least testing for
859 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
860 ; SSE-LABEL: combine_nested_undef_test15:
862 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
863 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,1]
864 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
867 ; AVX-LABEL: combine_nested_undef_test15:
869 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
870 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[3,1]
871 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
873 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
874 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
878 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
879 ; SSE2-LABEL: combine_nested_undef_test16:
881 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
882 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
883 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
886 ; SSSE3-LABEL: combine_nested_undef_test16:
888 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
889 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
890 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
893 ; SSE41-LABEL: combine_nested_undef_test16:
895 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
896 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
899 ; AVX1-LABEL: combine_nested_undef_test16:
901 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
902 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
905 ; AVX2-LABEL: combine_nested_undef_test16:
907 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
908 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
910 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
911 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
915 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
916 ; SSE-LABEL: combine_nested_undef_test17:
918 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
919 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
920 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
923 ; AVX-LABEL: combine_nested_undef_test17:
925 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
926 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
927 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
929 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
930 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
934 define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
935 ; SSE-LABEL: combine_nested_undef_test18:
937 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
940 ; AVX-LABEL: combine_nested_undef_test18:
942 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
944 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
945 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
949 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
950 ; SSE-LABEL: combine_nested_undef_test19:
952 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
953 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
954 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
957 ; AVX-LABEL: combine_nested_undef_test19:
959 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
960 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
961 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
963 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
964 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
968 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
969 ; SSE-LABEL: combine_nested_undef_test20:
971 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
972 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
975 ; AVX-LABEL: combine_nested_undef_test20:
977 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
978 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
980 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
981 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
985 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
986 ; SSE-LABEL: combine_nested_undef_test21:
988 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
989 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
990 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
993 ; AVX-LABEL: combine_nested_undef_test21:
995 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
996 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
997 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
999 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
1000 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1005 ; Test that we correctly combine shuffles according to rule
1006 ; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
1008 define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
1009 ; SSE-LABEL: combine_nested_undef_test22:
1011 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1014 ; AVX-LABEL: combine_nested_undef_test22:
1016 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1018 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1019 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
1023 define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1024 ; SSE-LABEL: combine_nested_undef_test23:
1026 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1029 ; AVX-LABEL: combine_nested_undef_test23:
1031 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1033 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1034 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1038 define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1039 ; SSE-LABEL: combine_nested_undef_test24:
1041 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1044 ; AVX-LABEL: combine_nested_undef_test24:
1046 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1048 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1049 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1053 define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1054 ; SSE-LABEL: combine_nested_undef_test25:
1056 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1059 ; AVX1-LABEL: combine_nested_undef_test25:
1061 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1064 ; AVX2-LABEL: combine_nested_undef_test25:
1066 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1068 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1069 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1073 define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1074 ; SSE-LABEL: combine_nested_undef_test26:
1076 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1079 ; AVX-LABEL: combine_nested_undef_test26:
1081 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1083 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1084 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1088 define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1089 ; SSE-LABEL: combine_nested_undef_test27:
1091 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1094 ; AVX1-LABEL: combine_nested_undef_test27:
1096 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1099 ; AVX2-LABEL: combine_nested_undef_test27:
1101 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1103 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1104 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1108 define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1109 ; SSE-LABEL: combine_nested_undef_test28:
1111 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1114 ; AVX-LABEL: combine_nested_undef_test28:
1116 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1118 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1119 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1123 define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1124 ; SSE2-LABEL: combine_test1:
1126 ; SSE2-NEXT: movaps %xmm1, %xmm2
1127 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1128 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1129 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,3]
1130 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1131 ; SSE2-NEXT: movaps %xmm2, %xmm0
1134 ; SSSE3-LABEL: combine_test1:
1136 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1139 ; SSE41-LABEL: combine_test1:
1141 ; SSE41-NEXT: movaps %xmm1, %xmm0
1144 ; AVX-LABEL: combine_test1:
1146 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1148 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1149 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1153 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1154 ; SSE2-LABEL: combine_test2:
1156 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1157 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1158 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1159 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1162 ; SSSE3-LABEL: combine_test2:
1164 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1165 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1166 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1167 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1170 ; SSE41-LABEL: combine_test2:
1172 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1175 ; AVX-LABEL: combine_test2:
1177 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1179 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1180 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1184 define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1185 ; SSE-LABEL: combine_test3:
1187 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1190 ; AVX-LABEL: combine_test3:
1192 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1194 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1195 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1199 define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1200 ; SSE-LABEL: combine_test4:
1202 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1203 ; SSE-NEXT: movapd %xmm1, %xmm0
1206 ; AVX-LABEL: combine_test4:
1208 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1210 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1211 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1215 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1216 ; SSE2-LABEL: combine_test5:
1218 ; SSE2-NEXT: movaps %xmm1, %xmm2
1219 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1220 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1221 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1222 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1223 ; SSE2-NEXT: movaps %xmm2, %xmm0
1226 ; SSSE3-LABEL: combine_test5:
1228 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1229 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1230 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1231 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1232 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1233 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1236 ; SSE41-LABEL: combine_test5:
1238 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1241 ; AVX-LABEL: combine_test5:
1243 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1245 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1246 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1250 define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1251 ; SSE2-LABEL: combine_test6:
1253 ; SSE2-NEXT: movaps %xmm1, %xmm2
1254 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1255 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1256 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,3]
1257 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1258 ; SSE2-NEXT: movaps %xmm2, %xmm0
1261 ; SSSE3-LABEL: combine_test6:
1263 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1266 ; SSE41-LABEL: combine_test6:
1268 ; SSE41-NEXT: movaps %xmm1, %xmm0
1271 ; AVX-LABEL: combine_test6:
1273 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1275 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1276 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1280 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1281 ; SSE2-LABEL: combine_test7:
1283 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1284 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1285 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1286 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1289 ; SSSE3-LABEL: combine_test7:
1291 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1292 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1293 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1294 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1297 ; SSE41-LABEL: combine_test7:
1299 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1302 ; AVX1-LABEL: combine_test7:
1304 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1307 ; AVX2-LABEL: combine_test7:
1309 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1311 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1312 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1316 define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1317 ; SSE-LABEL: combine_test8:
1319 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1322 ; AVX-LABEL: combine_test8:
1324 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1326 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1327 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1331 define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1332 ; SSE-LABEL: combine_test9:
1334 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1335 ; SSE-NEXT: movdqa %xmm1, %xmm0
1338 ; AVX-LABEL: combine_test9:
1340 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1342 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1343 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1347 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1348 ; SSE2-LABEL: combine_test10:
1350 ; SSE2-NEXT: movaps %xmm1, %xmm2
1351 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1352 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1353 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1354 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1355 ; SSE2-NEXT: movaps %xmm2, %xmm0
1358 ; SSSE3-LABEL: combine_test10:
1360 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1361 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1362 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1363 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1364 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1365 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1368 ; SSE41-LABEL: combine_test10:
1370 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1373 ; AVX1-LABEL: combine_test10:
1375 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1378 ; AVX2-LABEL: combine_test10:
1380 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1382 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1383 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1387 define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1388 ; ALL-LABEL: combine_test11:
1391 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1392 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1396 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1397 ; SSE2-LABEL: combine_test12:
1399 ; SSE2-NEXT: movss %xmm0, %xmm1
1400 ; SSE2-NEXT: movss %xmm0, %xmm1
1401 ; SSE2-NEXT: movaps %xmm1, %xmm0
1404 ; SSSE3-LABEL: combine_test12:
1406 ; SSSE3-NEXT: movss %xmm0, %xmm1
1407 ; SSSE3-NEXT: movss %xmm0, %xmm1
1408 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1411 ; SSE41-LABEL: combine_test12:
1413 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1416 ; AVX-LABEL: combine_test12:
1418 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1420 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1421 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1425 define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1426 ; SSE-LABEL: combine_test13:
1428 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1431 ; AVX-LABEL: combine_test13:
1433 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1435 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1436 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1440 define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1441 ; SSE-LABEL: combine_test14:
1443 ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1446 ; AVX-LABEL: combine_test14:
1448 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1450 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1451 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1455 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1456 ; SSE2-LABEL: combine_test15:
1458 ; SSE2-NEXT: movaps %xmm0, %xmm2
1459 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1460 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1461 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1462 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1465 ; SSSE3-LABEL: combine_test15:
1467 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1468 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1469 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1470 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1471 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1474 ; SSE41-LABEL: combine_test15:
1476 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1479 ; AVX-LABEL: combine_test15:
1481 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1483 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1484 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1488 define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1489 ; ALL-LABEL: combine_test16:
1492 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1493 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1497 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1498 ; SSE2-LABEL: combine_test17:
1500 ; SSE2-NEXT: movss %xmm0, %xmm1
1501 ; SSE2-NEXT: movss %xmm0, %xmm1
1502 ; SSE2-NEXT: movaps %xmm1, %xmm0
1505 ; SSSE3-LABEL: combine_test17:
1507 ; SSSE3-NEXT: movss %xmm0, %xmm1
1508 ; SSSE3-NEXT: movss %xmm0, %xmm1
1509 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1512 ; SSE41-LABEL: combine_test17:
1514 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1517 ; AVX1-LABEL: combine_test17:
1519 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1522 ; AVX2-LABEL: combine_test17:
1524 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1526 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1527 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1531 define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1532 ; SSE-LABEL: combine_test18:
1534 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1537 ; AVX-LABEL: combine_test18:
1539 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1541 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1542 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1546 define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1547 ; SSE-LABEL: combine_test19:
1549 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1552 ; AVX-LABEL: combine_test19:
1554 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1556 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1557 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1561 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1562 ; SSE2-LABEL: combine_test20:
1564 ; SSE2-NEXT: movaps %xmm0, %xmm2
1565 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1566 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1567 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1568 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1571 ; SSSE3-LABEL: combine_test20:
1573 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1574 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1575 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1576 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1577 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1580 ; SSE41-LABEL: combine_test20:
1582 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1585 ; AVX1-LABEL: combine_test20:
1587 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1590 ; AVX2-LABEL: combine_test20:
1592 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1594 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1595 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1600 ; Check some negative cases.
1601 ; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1603 define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1604 ; SSE2-LABEL: combine_test1b:
1606 ; SSE2-NEXT: movaps %xmm1, %xmm2
1607 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1608 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1609 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]
1610 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
1611 ; SSE2-NEXT: movaps %xmm1, %xmm0
1614 ; SSSE3-LABEL: combine_test1b:
1616 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1617 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1618 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1619 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]
1620 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
1621 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1624 ; SSE41-LABEL: combine_test1b:
1626 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1627 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1628 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,0]
1629 ; SSE41-NEXT: movaps %xmm1, %xmm0
1632 ; AVX-LABEL: combine_test1b:
1634 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1635 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1636 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[2,0]
1638 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1639 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1643 define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1644 ; SSE2-LABEL: combine_test2b:
1646 ; SSE2-NEXT: movaps %xmm1, %xmm2
1647 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1648 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1649 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]
1650 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1651 ; SSE2-NEXT: movaps %xmm2, %xmm0
1654 ; SSSE3-LABEL: combine_test2b:
1656 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1657 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1658 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1659 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]
1660 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1661 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1664 ; SSE41-LABEL: combine_test2b:
1666 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1667 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]
1668 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1671 ; AVX-LABEL: combine_test2b:
1673 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1674 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]
1675 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1677 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1678 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
1682 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1683 ; SSE-LABEL: combine_test3b:
1685 ; SSE-NEXT: movaps %xmm1, %xmm2
1686 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[3,0]
1687 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1688 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1689 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1692 ; AVX-LABEL: combine_test3b:
1694 ; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,0],xmm0[3,0]
1695 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1696 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1697 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1699 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1700 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1704 define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1705 ; SSE2-LABEL: combine_test4b:
1707 ; SSE2-NEXT: movaps %xmm1, %xmm2
1708 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1709 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1710 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
1711 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]
1712 ; SSE2-NEXT: movaps %xmm1, %xmm0
1715 ; SSSE3-LABEL: combine_test4b:
1717 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1718 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1719 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1720 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
1721 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]
1722 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1725 ; SSE41-LABEL: combine_test4b:
1727 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1728 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
1729 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[0,2]
1730 ; SSE41-NEXT: movaps %xmm1, %xmm0
1733 ; AVX-LABEL: combine_test4b:
1735 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1736 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
1737 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[1,1],xmm0[0,2]
1739 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1740 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1745 ; Verify that we correctly fold shuffles even when we use illegal vector types.
1747 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1748 ; SSE2-LABEL: combine_test1c:
1750 ; SSE2-NEXT: movd (%rdi), %xmm0
1751 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1752 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1753 ; SSE2-NEXT: movd (%rsi), %xmm1
1754 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1755 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1756 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1757 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1758 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1759 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1762 ; SSSE3-LABEL: combine_test1c:
1764 ; SSSE3-NEXT: movd (%rdi), %xmm0
1765 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1766 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1767 ; SSSE3-NEXT: movd (%rsi), %xmm1
1768 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1769 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1770 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1771 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1772 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1773 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1776 ; SSE41-LABEL: combine_test1c:
1778 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1779 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1780 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1783 ; AVX1-LABEL: combine_test1c:
1785 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1786 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1787 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1790 ; AVX2-LABEL: combine_test1c:
1792 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1793 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1794 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1796 %A = load <4 x i8>* %a
1797 %B = load <4 x i8>* %b
1798 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1799 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1803 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1804 ; SSE2-LABEL: combine_test2c:
1806 ; SSE2-NEXT: movd (%rdi), %xmm0
1807 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1808 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1809 ; SSE2-NEXT: movd (%rsi), %xmm1
1810 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1811 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1812 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1815 ; SSSE3-LABEL: combine_test2c:
1817 ; SSSE3-NEXT: movd (%rdi), %xmm0
1818 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1819 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1820 ; SSSE3-NEXT: movd (%rsi), %xmm1
1821 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1822 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1823 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1826 ; SSE41-LABEL: combine_test2c:
1828 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm0
1829 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm1
1830 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1833 ; AVX-LABEL: combine_test2c:
1835 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1836 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1837 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1839 %A = load <4 x i8>* %a
1840 %B = load <4 x i8>* %b
1841 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1842 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1846 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1847 ; SSE2-LABEL: combine_test3c:
1849 ; SSE2-NEXT: movd (%rdi), %xmm1
1850 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1851 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1852 ; SSE2-NEXT: movd (%rsi), %xmm0
1853 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1854 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1855 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1858 ; SSSE3-LABEL: combine_test3c:
1860 ; SSSE3-NEXT: movd (%rdi), %xmm1
1861 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1862 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1863 ; SSSE3-NEXT: movd (%rsi), %xmm0
1864 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1865 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1866 ; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1869 ; SSE41-LABEL: combine_test3c:
1871 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1872 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1873 ; SSE41-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1876 ; AVX-LABEL: combine_test3c:
1878 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1879 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1880 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1882 %A = load <4 x i8>* %a
1883 %B = load <4 x i8>* %b
1884 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1885 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1889 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
1890 ; SSE2-LABEL: combine_test4c:
1892 ; SSE2-NEXT: movd (%rdi), %xmm1
1893 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1894 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1895 ; SSE2-NEXT: movd (%rsi), %xmm2
1896 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1897 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1898 ; SSE2-NEXT: movdqa %xmm2, %xmm0
1899 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1900 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1901 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1902 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1905 ; SSSE3-LABEL: combine_test4c:
1907 ; SSSE3-NEXT: movd (%rdi), %xmm1
1908 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1909 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1910 ; SSSE3-NEXT: movd (%rsi), %xmm2
1911 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1912 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1913 ; SSSE3-NEXT: movdqa %xmm2, %xmm0
1914 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1915 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1916 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1917 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1920 ; SSE41-LABEL: combine_test4c:
1922 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1923 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1924 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1927 ; AVX1-LABEL: combine_test4c:
1929 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1930 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1931 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1934 ; AVX2-LABEL: combine_test4c:
1936 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1937 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1938 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1940 %A = load <4 x i8>* %a
1941 %B = load <4 x i8>* %b
1942 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1943 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1948 ; The following test cases are generated from this C++ code
1950 ;__m128 blend_01(__m128 a, __m128 b)
1953 ; s = _mm_blend_ps( s, b, 1<<0 );
1954 ; s = _mm_blend_ps( s, b, 1<<1 );
1958 ;__m128 blend_02(__m128 a, __m128 b)
1961 ; s = _mm_blend_ps( s, b, 1<<0 );
1962 ; s = _mm_blend_ps( s, b, 1<<2 );
1966 ;__m128 blend_123(__m128 a, __m128 b)
1969 ; s = _mm_blend_ps( s, b, 1<<1 );
1970 ; s = _mm_blend_ps( s, b, 1<<2 );
1971 ; s = _mm_blend_ps( s, b, 1<<3 );
1975 ; Ideally, we should collapse the following shuffles into a single one.
1977 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
1978 ; SSE2-LABEL: combine_blend_01:
1980 ; SSE2-NEXT: movsd %xmm1, %xmm0
1981 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1982 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
1983 ; SSE2-NEXT: movaps %xmm1, %xmm0
1986 ; SSSE3-LABEL: combine_blend_01:
1988 ; SSSE3-NEXT: movsd %xmm1, %xmm0
1989 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1990 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
1991 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1994 ; SSE41-LABEL: combine_blend_01:
1996 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1999 ; AVX-LABEL: combine_blend_01:
2001 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2003 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
2004 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
2005 ret <4 x float> %shuffle6
2008 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
2009 ; SSE2-LABEL: combine_blend_02:
2011 ; SSE2-NEXT: movss %xmm1, %xmm0
2012 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
2013 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2016 ; SSSE3-LABEL: combine_blend_02:
2018 ; SSSE3-NEXT: movss %xmm1, %xmm0
2019 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
2020 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2023 ; SSE41-LABEL: combine_blend_02:
2025 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2028 ; AVX-LABEL: combine_blend_02:
2030 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2032 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
2033 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
2034 ret <4 x float> %shuffle6
2037 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
2038 ; SSE2-LABEL: combine_blend_123:
2040 ; SSE2-NEXT: movaps %xmm1, %xmm2
2041 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[0,0]
2042 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
2043 ; SSE2-NEXT: movsd %xmm2, %xmm1
2044 ; SSE2-NEXT: movaps %xmm1, %xmm0
2047 ; SSSE3-LABEL: combine_blend_123:
2049 ; SSSE3-NEXT: movaps %xmm1, %xmm2
2050 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[0,0]
2051 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
2052 ; SSSE3-NEXT: movsd %xmm2, %xmm1
2053 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2056 ; SSE41-LABEL: combine_blend_123:
2058 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2061 ; AVX-LABEL: combine_blend_123:
2063 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2065 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
2066 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
2067 %shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2068 ret <4 x float> %shuffle12
2071 define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
2072 ; SSE-LABEL: combine_test_movhl_1:
2074 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2075 ; SSE-NEXT: movdqa %xmm1, %xmm0
2078 ; AVX-LABEL: combine_test_movhl_1:
2080 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2082 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
2083 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
2087 define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
2088 ; SSE-LABEL: combine_test_movhl_2:
2090 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2091 ; SSE-NEXT: movdqa %xmm1, %xmm0
2094 ; AVX-LABEL: combine_test_movhl_2:
2096 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2098 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
2099 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
2103 define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
2104 ; SSE-LABEL: combine_test_movhl_3:
2106 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2107 ; SSE-NEXT: movdqa %xmm1, %xmm0
2110 ; AVX-LABEL: combine_test_movhl_3:
2112 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2114 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
2115 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>
2120 ; Verify that we fold shuffles according to rule:
2121 ; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
2123 define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
2124 ; SSE2-LABEL: combine_undef_input_test1:
2126 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2127 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2128 ; SSE2-NEXT: movaps %xmm1, %xmm0
2131 ; SSSE3-LABEL: combine_undef_input_test1:
2133 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2134 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2135 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2138 ; SSE41-LABEL: combine_undef_input_test1:
2140 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2143 ; AVX-LABEL: combine_undef_input_test1:
2145 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2147 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2148 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2152 define <4 x float> @combine_undef_input_test2(<4 x float> %a, <4 x float> %b) {
2153 ; SSE-LABEL: combine_undef_input_test2:
2155 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2158 ; AVX-LABEL: combine_undef_input_test2:
2160 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2162 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2163 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2167 define <4 x float> @combine_undef_input_test3(<4 x float> %a, <4 x float> %b) {
2168 ; SSE-LABEL: combine_undef_input_test3:
2170 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2173 ; AVX-LABEL: combine_undef_input_test3:
2175 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2177 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2178 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2182 define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
2183 ; SSE-LABEL: combine_undef_input_test4:
2185 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2186 ; SSE-NEXT: movapd %xmm1, %xmm0
2189 ; AVX-LABEL: combine_undef_input_test4:
2191 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2193 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2194 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2198 define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
2199 ; SSE2-LABEL: combine_undef_input_test5:
2201 ; SSE2-NEXT: movsd %xmm0, %xmm1
2202 ; SSE2-NEXT: movaps %xmm1, %xmm0
2205 ; SSSE3-LABEL: combine_undef_input_test5:
2207 ; SSSE3-NEXT: movsd %xmm0, %xmm1
2208 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2211 ; SSE41-LABEL: combine_undef_input_test5:
2213 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2216 ; AVX-LABEL: combine_undef_input_test5:
2218 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2220 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2221 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2226 ; Verify that we fold shuffles according to rule:
2227 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2229 define <4 x float> @combine_undef_input_test6(<4 x float> %a) {
2230 ; ALL-LABEL: combine_undef_input_test6:
2233 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2234 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2238 define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
2239 ; SSE2-LABEL: combine_undef_input_test7:
2241 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2244 ; SSSE3-LABEL: combine_undef_input_test7:
2246 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2249 ; SSE41-LABEL: combine_undef_input_test7:
2251 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2254 ; AVX-LABEL: combine_undef_input_test7:
2256 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2258 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2259 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2263 define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
2264 ; SSE2-LABEL: combine_undef_input_test8:
2266 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2269 ; SSSE3-LABEL: combine_undef_input_test8:
2271 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2274 ; SSE41-LABEL: combine_undef_input_test8:
2276 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2279 ; AVX-LABEL: combine_undef_input_test8:
2281 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2283 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2284 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2288 define <4 x float> @combine_undef_input_test9(<4 x float> %a) {
2289 ; SSE-LABEL: combine_undef_input_test9:
2291 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2294 ; AVX-LABEL: combine_undef_input_test9:
2296 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2298 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2299 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2303 define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
2304 ; ALL-LABEL: combine_undef_input_test10:
2307 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2308 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2312 define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
2313 ; SSE2-LABEL: combine_undef_input_test11:
2315 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2316 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2317 ; SSE2-NEXT: movaps %xmm1, %xmm0
2320 ; SSSE3-LABEL: combine_undef_input_test11:
2322 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2323 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2324 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2327 ; SSE41-LABEL: combine_undef_input_test11:
2329 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2332 ; AVX-LABEL: combine_undef_input_test11:
2334 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2336 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2337 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 6>
2341 define <4 x float> @combine_undef_input_test12(<4 x float> %a, <4 x float> %b) {
2342 ; SSE-LABEL: combine_undef_input_test12:
2344 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2347 ; AVX-LABEL: combine_undef_input_test12:
2349 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2351 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2352 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2356 define <4 x float> @combine_undef_input_test13(<4 x float> %a, <4 x float> %b) {
2357 ; SSE-LABEL: combine_undef_input_test13:
2359 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2362 ; AVX-LABEL: combine_undef_input_test13:
2364 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2366 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2367 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 5, i32 0, i32 5>
2371 define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
2372 ; SSE-LABEL: combine_undef_input_test14:
2374 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2375 ; SSE-NEXT: movapd %xmm1, %xmm0
2378 ; AVX-LABEL: combine_undef_input_test14:
2380 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2382 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2383 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2387 define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
2388 ; SSE2-LABEL: combine_undef_input_test15:
2390 ; SSE2-NEXT: movsd %xmm0, %xmm1
2391 ; SSE2-NEXT: movaps %xmm1, %xmm0
2394 ; SSSE3-LABEL: combine_undef_input_test15:
2396 ; SSSE3-NEXT: movsd %xmm0, %xmm1
2397 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2400 ; SSE41-LABEL: combine_undef_input_test15:
2402 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2405 ; AVX-LABEL: combine_undef_input_test15:
2407 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2409 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2410 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2415 ; Verify that shuffles are canonicalized according to rules:
2416 ; shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
2418 ; This allows to trigger the following combine rule:
2419 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2421 ; As a result, all the shuffle pairs in each function below should be
2422 ; combined into a single legal shuffle operation.
2424 define <4 x float> @combine_undef_input_test16(<4 x float> %a) {
2425 ; ALL-LABEL: combine_undef_input_test16:
2428 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2429 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
2433 define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
2434 ; SSE2-LABEL: combine_undef_input_test17:
2436 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2439 ; SSSE3-LABEL: combine_undef_input_test17:
2441 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2444 ; SSE41-LABEL: combine_undef_input_test17:
2446 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2449 ; AVX-LABEL: combine_undef_input_test17:
2451 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2453 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2454 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2458 define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
2459 ; SSE2-LABEL: combine_undef_input_test18:
2461 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2464 ; SSSE3-LABEL: combine_undef_input_test18:
2466 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2469 ; SSE41-LABEL: combine_undef_input_test18:
2471 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2474 ; AVX-LABEL: combine_undef_input_test18:
2476 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2478 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2479 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
2483 define <4 x float> @combine_undef_input_test19(<4 x float> %a) {
2484 ; SSE-LABEL: combine_undef_input_test19:
2486 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2489 ; AVX-LABEL: combine_undef_input_test19:
2491 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2493 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2494 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2498 define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
2499 ; ALL-LABEL: combine_undef_input_test20:
2502 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2503 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2507 ; These tests are designed to test the ability to combine away unnecessary
2508 ; operations feeding into a shuffle. The AVX cases are the important ones as
2509 ; they leverage operations which cannot be done naturally on the entire vector
2510 ; and thus are decomposed into multiple smaller operations.
2512 define <8 x i32> @combine_unneeded_subvector1(<8 x i32> %a) {
2513 ; SSE-LABEL: combine_unneeded_subvector1:
2515 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2516 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
2517 ; SSE-NEXT: movdqa %xmm0, %xmm1
2520 ; AVX1-LABEL: combine_unneeded_subvector1:
2522 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2523 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2524 ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2525 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2528 ; AVX2-LABEL: combine_unneeded_subvector1:
2530 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2531 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
2532 ; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
2534 %b = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2535 %c = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
2539 define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
2540 ; SSE-LABEL: combine_unneeded_subvector2:
2542 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2543 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,2,1,0]
2544 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
2547 ; AVX1-LABEL: combine_unneeded_subvector2:
2549 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2550 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2551 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2552 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
2553 ; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,2,1,0]
2554 ; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2555 ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
2558 ; AVX2-LABEL: combine_unneeded_subvector2:
2560 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2561 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = <7,6,5,4,u,u,u,u>
2562 ; AVX2-NEXT: vpermd %ymm1, %ymm2, %ymm1
2563 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2564 ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
2566 %c = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2567 %d = shufflevector <8 x i32> %b, <8 x i32> %c, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>