1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=CHECK-SSE2
3 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
4 target triple = "x86_64-unknown-unknown"
6 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
7 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
9 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
10 ; CHECK-SSE2-LABEL: @combine_pshuflw1
12 ; CHECK-SSE2-NEXT: retq
13 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
14 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
18 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
19 ; CHECK-SSE2-LABEL: @combine_pshuflw2
21 ; CHECK-SSE2-NEXT: retq
22 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
23 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
24 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
28 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
29 ; CHECK-SSE2-LABEL: @combine_pshuflw3
31 ; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,7,6,5,4]
32 ; CHECK-SSE2-NEXT: retq
33 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
34 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
35 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
39 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
40 ; CHECK-SSE2-LABEL: @combine_pshufhw1
42 ; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[3,2,1,0,4,5,6,7]
43 ; CHECK-SSE2-NEXT: retq
44 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
45 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
46 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)