1 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7 ; Verify that the DAG combiner correctly folds bitwise operations across
8 ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
9 ; basic and always-safe patterns. Also test that the DAG combiner will combine
10 ; target-specific shuffle instructions where reasonable.
12 target triple = "x86_64-unknown-unknown"
14 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
15 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
16 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
18 define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
19 ; ALL-LABEL: combine_pshufd1:
20 ; ALL: # BB#0: # %entry
23 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
24 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
28 define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
29 ; ALL-LABEL: combine_pshufd2:
30 ; ALL: # BB#0: # %entry
33 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
34 %b.cast = bitcast <4 x i32> %b to <8 x i16>
35 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
36 %c.cast = bitcast <8 x i16> %c to <4 x i32>
37 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
41 define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
42 ; ALL-LABEL: combine_pshufd3:
43 ; ALL: # BB#0: # %entry
46 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
47 %b.cast = bitcast <4 x i32> %b to <8 x i16>
48 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
49 %c.cast = bitcast <8 x i16> %c to <4 x i32>
50 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
54 define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
55 ; SSE-LABEL: combine_pshufd4:
56 ; SSE: # BB#0: # %entry
57 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
60 ; AVX-LABEL: combine_pshufd4:
61 ; AVX: # BB#0: # %entry
62 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
65 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
66 %b.cast = bitcast <4 x i32> %b to <8 x i16>
67 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
68 %c.cast = bitcast <8 x i16> %c to <4 x i32>
69 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
73 define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
74 ; SSE-LABEL: combine_pshufd5:
75 ; SSE: # BB#0: # %entry
76 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
79 ; AVX-LABEL: combine_pshufd5:
80 ; AVX: # BB#0: # %entry
81 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
84 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
85 %b.cast = bitcast <4 x i32> %b to <8 x i16>
86 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
87 %c.cast = bitcast <8 x i16> %c to <4 x i32>
88 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
92 define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
93 ; SSE-LABEL: combine_pshufd6:
94 ; SSE: # BB#0: # %entry
95 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
98 ; AVX-LABEL: combine_pshufd6:
99 ; AVX: # BB#0: # %entry
100 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
103 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
104 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
108 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
109 ; ALL-LABEL: combine_pshuflw1:
110 ; ALL: # BB#0: # %entry
113 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
114 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
118 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
119 ; ALL-LABEL: combine_pshuflw2:
120 ; ALL: # BB#0: # %entry
123 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
124 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
125 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
129 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
130 ; SSE-LABEL: combine_pshuflw3:
131 ; SSE: # BB#0: # %entry
132 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
135 ; AVX-LABEL: combine_pshuflw3:
136 ; AVX: # BB#0: # %entry
137 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
140 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
141 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
142 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
146 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
147 ; SSE-LABEL: combine_pshufhw1:
148 ; SSE: # BB#0: # %entry
149 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
152 ; AVX-LABEL: combine_pshufhw1:
153 ; AVX: # BB#0: # %entry
154 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
157 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
158 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
159 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
163 define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164 ; SSE-LABEL: combine_bitwise_ops_test1:
166 ; SSE-NEXT: pand %xmm1, %xmm0
167 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
170 ; AVX-LABEL: combine_bitwise_ops_test1:
172 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
173 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
175 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
176 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177 %and = and <4 x i32> %shuf1, %shuf2
181 define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
182 ; SSE-LABEL: combine_bitwise_ops_test2:
184 ; SSE-NEXT: por %xmm1, %xmm0
185 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
188 ; AVX-LABEL: combine_bitwise_ops_test2:
190 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
191 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
193 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
194 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195 %or = or <4 x i32> %shuf1, %shuf2
199 define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
200 ; SSE-LABEL: combine_bitwise_ops_test3:
202 ; SSE-NEXT: pxor %xmm1, %xmm0
203 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
206 ; AVX-LABEL: combine_bitwise_ops_test3:
208 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
209 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
211 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
212 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213 %xor = xor <4 x i32> %shuf1, %shuf2
217 define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218 ; SSE-LABEL: combine_bitwise_ops_test4:
220 ; SSE-NEXT: pand %xmm1, %xmm0
221 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
224 ; AVX-LABEL: combine_bitwise_ops_test4:
226 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
227 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
229 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
230 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231 %and = and <4 x i32> %shuf1, %shuf2
235 define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
236 ; SSE-LABEL: combine_bitwise_ops_test5:
238 ; SSE-NEXT: por %xmm1, %xmm0
239 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
242 ; AVX-LABEL: combine_bitwise_ops_test5:
244 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
245 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
247 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
248 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249 %or = or <4 x i32> %shuf1, %shuf2
253 define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
254 ; SSE-LABEL: combine_bitwise_ops_test6:
256 ; SSE-NEXT: pxor %xmm1, %xmm0
257 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
260 ; AVX-LABEL: combine_bitwise_ops_test6:
262 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
263 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
265 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
266 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267 %xor = xor <4 x i32> %shuf1, %shuf2
272 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
273 ; are not performing a swizzle operations.
275 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
276 ; SSE2-LABEL: combine_bitwise_ops_test1b:
278 ; SSE2-NEXT: pand %xmm1, %xmm0
279 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
280 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
281 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
284 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
286 ; SSSE3-NEXT: pand %xmm1, %xmm0
287 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
288 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
289 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
292 ; SSE41-LABEL: combine_bitwise_ops_test1b:
294 ; SSE41-NEXT: pand %xmm1, %xmm0
295 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
298 ; AVX1-LABEL: combine_bitwise_ops_test1b:
300 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
301 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
304 ; AVX2-LABEL: combine_bitwise_ops_test1b:
306 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
307 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
309 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
310 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
311 %and = and <4 x i32> %shuf1, %shuf2
315 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
316 ; SSE2-LABEL: combine_bitwise_ops_test2b:
318 ; SSE2-NEXT: por %xmm1, %xmm0
319 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
320 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
321 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
324 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
326 ; SSSE3-NEXT: por %xmm1, %xmm0
327 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
328 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
329 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
332 ; SSE41-LABEL: combine_bitwise_ops_test2b:
334 ; SSE41-NEXT: por %xmm1, %xmm0
335 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
338 ; AVX1-LABEL: combine_bitwise_ops_test2b:
340 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
341 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
344 ; AVX2-LABEL: combine_bitwise_ops_test2b:
346 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
347 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
349 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
350 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
351 %or = or <4 x i32> %shuf1, %shuf2
355 define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
356 ; SSE2-LABEL: combine_bitwise_ops_test3b:
358 ; SSE2-NEXT: xorps %xmm1, %xmm0
359 ; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
362 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
364 ; SSSE3-NEXT: xorps %xmm1, %xmm0
365 ; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
368 ; SSE41-LABEL: combine_bitwise_ops_test3b:
370 ; SSE41-NEXT: pxor %xmm1, %xmm0
371 ; SSE41-NEXT: pxor %xmm1, %xmm1
372 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
375 ; AVX1-LABEL: combine_bitwise_ops_test3b:
377 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
378 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
379 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
382 ; AVX2-LABEL: combine_bitwise_ops_test3b:
384 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
385 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
386 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
388 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
389 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
390 %xor = xor <4 x i32> %shuf1, %shuf2
394 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
395 ; SSE2-LABEL: combine_bitwise_ops_test4b:
397 ; SSE2-NEXT: pand %xmm1, %xmm0
398 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
399 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
400 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
403 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
405 ; SSSE3-NEXT: pand %xmm1, %xmm0
406 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
407 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
408 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
411 ; SSE41-LABEL: combine_bitwise_ops_test4b:
413 ; SSE41-NEXT: pand %xmm1, %xmm0
414 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
417 ; AVX1-LABEL: combine_bitwise_ops_test4b:
419 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
420 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
423 ; AVX2-LABEL: combine_bitwise_ops_test4b:
425 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
426 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
428 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
429 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
430 %and = and <4 x i32> %shuf1, %shuf2
434 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
435 ; SSE2-LABEL: combine_bitwise_ops_test5b:
437 ; SSE2-NEXT: por %xmm1, %xmm0
438 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
439 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
440 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
443 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
445 ; SSSE3-NEXT: por %xmm1, %xmm0
446 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
447 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
448 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
451 ; SSE41-LABEL: combine_bitwise_ops_test5b:
453 ; SSE41-NEXT: por %xmm1, %xmm0
454 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
457 ; AVX1-LABEL: combine_bitwise_ops_test5b:
459 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
460 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
463 ; AVX2-LABEL: combine_bitwise_ops_test5b:
465 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
466 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
468 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
469 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
470 %or = or <4 x i32> %shuf1, %shuf2
474 define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
475 ; SSE2-LABEL: combine_bitwise_ops_test6b:
477 ; SSE2-NEXT: xorps %xmm1, %xmm0
478 ; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
481 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
483 ; SSSE3-NEXT: xorps %xmm1, %xmm0
484 ; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
487 ; SSE41-LABEL: combine_bitwise_ops_test6b:
489 ; SSE41-NEXT: pxor %xmm1, %xmm0
490 ; SSE41-NEXT: pxor %xmm1, %xmm1
491 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
494 ; AVX1-LABEL: combine_bitwise_ops_test6b:
496 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
497 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
498 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
501 ; AVX2-LABEL: combine_bitwise_ops_test6b:
503 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
504 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
505 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
507 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
508 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
509 %xor = xor <4 x i32> %shuf1, %shuf2
513 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
514 ; SSE2-LABEL: combine_bitwise_ops_test1c:
516 ; SSE2-NEXT: pand %xmm1, %xmm0
517 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
518 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
519 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
522 ; SSSE3-LABEL: combine_bitwise_ops_test1c:
524 ; SSSE3-NEXT: pand %xmm1, %xmm0
525 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
526 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
527 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
530 ; SSE41-LABEL: combine_bitwise_ops_test1c:
532 ; SSE41-NEXT: pand %xmm1, %xmm0
533 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
534 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
537 ; AVX1-LABEL: combine_bitwise_ops_test1c:
539 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
540 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
541 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
544 ; AVX2-LABEL: combine_bitwise_ops_test1c:
546 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
547 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
548 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
550 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
551 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
552 %and = and <4 x i32> %shuf1, %shuf2
556 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
557 ; SSE2-LABEL: combine_bitwise_ops_test2c:
559 ; SSE2-NEXT: por %xmm1, %xmm0
560 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
561 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
562 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
565 ; SSSE3-LABEL: combine_bitwise_ops_test2c:
567 ; SSSE3-NEXT: por %xmm1, %xmm0
568 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
569 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
570 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
573 ; SSE41-LABEL: combine_bitwise_ops_test2c:
575 ; SSE41-NEXT: por %xmm1, %xmm0
576 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
577 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
580 ; AVX1-LABEL: combine_bitwise_ops_test2c:
582 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
583 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
584 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
587 ; AVX2-LABEL: combine_bitwise_ops_test2c:
589 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
590 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
591 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
593 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
594 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
595 %or = or <4 x i32> %shuf1, %shuf2
599 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
600 ; SSE2-LABEL: combine_bitwise_ops_test3c:
602 ; SSE2-NEXT: pxor %xmm1, %xmm0
603 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
604 ; SSE2-NEXT: pxor %xmm1, %xmm1
605 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
608 ; SSSE3-LABEL: combine_bitwise_ops_test3c:
610 ; SSSE3-NEXT: pxor %xmm1, %xmm0
611 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
612 ; SSSE3-NEXT: pxor %xmm1, %xmm1
613 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
616 ; SSE41-LABEL: combine_bitwise_ops_test3c:
618 ; SSE41-NEXT: pxor %xmm1, %xmm0
619 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
620 ; SSE41-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
623 ; AVX-LABEL: combine_bitwise_ops_test3c:
625 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
626 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
627 ; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
629 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
630 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
631 %xor = xor <4 x i32> %shuf1, %shuf2
635 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
636 ; SSE2-LABEL: combine_bitwise_ops_test4c:
638 ; SSE2-NEXT: pand %xmm1, %xmm0
639 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
640 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
641 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
644 ; SSSE3-LABEL: combine_bitwise_ops_test4c:
646 ; SSSE3-NEXT: pand %xmm1, %xmm0
647 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
648 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
649 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
652 ; SSE41-LABEL: combine_bitwise_ops_test4c:
654 ; SSE41-NEXT: pand %xmm1, %xmm0
655 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
656 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
659 ; AVX1-LABEL: combine_bitwise_ops_test4c:
661 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
662 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
663 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
666 ; AVX2-LABEL: combine_bitwise_ops_test4c:
668 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
669 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
670 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
672 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
673 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
674 %and = and <4 x i32> %shuf1, %shuf2
678 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
679 ; SSE2-LABEL: combine_bitwise_ops_test5c:
681 ; SSE2-NEXT: por %xmm1, %xmm0
682 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
683 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
684 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
687 ; SSSE3-LABEL: combine_bitwise_ops_test5c:
689 ; SSSE3-NEXT: por %xmm1, %xmm0
690 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
691 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
692 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
695 ; SSE41-LABEL: combine_bitwise_ops_test5c:
697 ; SSE41-NEXT: por %xmm1, %xmm0
698 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
699 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
702 ; AVX1-LABEL: combine_bitwise_ops_test5c:
704 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
705 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
706 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
709 ; AVX2-LABEL: combine_bitwise_ops_test5c:
711 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
712 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
713 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
715 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
716 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
717 %or = or <4 x i32> %shuf1, %shuf2
721 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
722 ; SSE2-LABEL: combine_bitwise_ops_test6c:
724 ; SSE2-NEXT: pxor %xmm1, %xmm0
725 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
726 ; SSE2-NEXT: pxor %xmm0, %xmm0
727 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
730 ; SSSE3-LABEL: combine_bitwise_ops_test6c:
732 ; SSSE3-NEXT: pxor %xmm1, %xmm0
733 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
734 ; SSSE3-NEXT: pxor %xmm0, %xmm0
735 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
738 ; SSE41-LABEL: combine_bitwise_ops_test6c:
740 ; SSE41-NEXT: pxor %xmm1, %xmm0
741 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
742 ; SSE41-NEXT: pxor %xmm0, %xmm0
743 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
746 ; AVX1-LABEL: combine_bitwise_ops_test6c:
748 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
749 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
750 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
751 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
754 ; AVX2-LABEL: combine_bitwise_ops_test6c:
756 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
757 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
758 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
759 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
761 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
762 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
763 %xor = xor <4 x i32> %shuf1, %shuf2
767 define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
768 ; SSE-LABEL: combine_nested_undef_test1:
770 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
773 ; AVX-LABEL: combine_nested_undef_test1:
775 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
777 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
778 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
782 define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
783 ; SSE-LABEL: combine_nested_undef_test2:
785 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
788 ; AVX-LABEL: combine_nested_undef_test2:
790 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
792 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
793 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
797 define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
798 ; SSE-LABEL: combine_nested_undef_test3:
800 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
803 ; AVX-LABEL: combine_nested_undef_test3:
805 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
807 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
808 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
812 define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
813 ; SSE-LABEL: combine_nested_undef_test4:
815 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
818 ; AVX1-LABEL: combine_nested_undef_test4:
820 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
823 ; AVX2-LABEL: combine_nested_undef_test4:
825 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
827 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
828 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
832 define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
833 ; SSE-LABEL: combine_nested_undef_test5:
835 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
838 ; AVX-LABEL: combine_nested_undef_test5:
840 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
842 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
843 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
847 define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
848 ; SSE-LABEL: combine_nested_undef_test6:
850 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
853 ; AVX-LABEL: combine_nested_undef_test6:
855 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
857 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
858 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
862 define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
863 ; SSE-LABEL: combine_nested_undef_test7:
865 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
868 ; AVX-LABEL: combine_nested_undef_test7:
870 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
872 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
873 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
877 define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
878 ; SSE-LABEL: combine_nested_undef_test8:
880 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
883 ; AVX-LABEL: combine_nested_undef_test8:
885 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
887 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
888 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
892 define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
893 ; SSE-LABEL: combine_nested_undef_test9:
895 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
898 ; AVX-LABEL: combine_nested_undef_test9:
900 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
902 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
903 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
907 define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
908 ; SSE-LABEL: combine_nested_undef_test10:
910 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
913 ; AVX-LABEL: combine_nested_undef_test10:
915 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
917 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
918 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
922 define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
923 ; SSE-LABEL: combine_nested_undef_test11:
925 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
928 ; AVX-LABEL: combine_nested_undef_test11:
930 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
932 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
933 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
937 define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
938 ; SSE-LABEL: combine_nested_undef_test12:
940 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
943 ; AVX1-LABEL: combine_nested_undef_test12:
945 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
948 ; AVX2-LABEL: combine_nested_undef_test12:
950 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
952 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
953 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
957 ; The following pair of shuffles is folded into vector %A.
958 define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
959 ; ALL-LABEL: combine_nested_undef_test13:
962 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
963 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
967 ; The following pair of shuffles is folded into vector %B.
968 define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
969 ; SSE-LABEL: combine_nested_undef_test14:
971 ; SSE-NEXT: movaps %xmm1, %xmm0
974 ; AVX-LABEL: combine_nested_undef_test14:
976 ; AVX-NEXT: vmovaps %xmm1, %xmm0
978 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
979 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
984 ; Verify that we don't optimize the following cases. We expect more than one shuffle.
986 ; FIXME: Many of these already don't make sense, and the rest should stop
987 ; making sense with th enew vector shuffle lowering. Revisit at least testing for
990 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
991 ; SSE2-LABEL: combine_nested_undef_test15:
993 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
994 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,1]
995 ; SSE2-NEXT: movaps %xmm1, %xmm0
998 ; SSSE3-LABEL: combine_nested_undef_test15:
1000 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
1001 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,1]
1002 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1005 ; SSE41-LABEL: combine_nested_undef_test15:
1007 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
1008 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1009 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1012 ; AVX1-LABEL: combine_nested_undef_test15:
1014 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
1015 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1016 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1019 ; AVX2-LABEL: combine_nested_undef_test15:
1021 ; AVX2-NEXT: vpbroadcastd %xmm1, %xmm1
1022 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1023 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
1025 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
1026 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1030 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
1031 ; SSE2-LABEL: combine_nested_undef_test16:
1033 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
1034 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,2,3]
1035 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1038 ; SSSE3-LABEL: combine_nested_undef_test16:
1040 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
1041 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,2,3]
1042 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1045 ; SSE41-LABEL: combine_nested_undef_test16:
1047 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
1048 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
1051 ; AVX1-LABEL: combine_nested_undef_test16:
1053 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
1054 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
1057 ; AVX2-LABEL: combine_nested_undef_test16:
1059 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
1060 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
1062 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1063 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1067 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
1068 ; SSE2-LABEL: combine_nested_undef_test17:
1070 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
1071 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
1074 ; SSSE3-LABEL: combine_nested_undef_test17:
1076 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
1077 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
1080 ; SSE41-LABEL: combine_nested_undef_test17:
1082 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1083 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1086 ; AVX1-LABEL: combine_nested_undef_test17:
1088 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1089 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1092 ; AVX2-LABEL: combine_nested_undef_test17:
1094 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1095 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1097 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
1098 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1102 define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
1103 ; SSE-LABEL: combine_nested_undef_test18:
1105 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
1108 ; AVX-LABEL: combine_nested_undef_test18:
1110 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
1112 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1113 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
1117 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
1118 ; SSE2-LABEL: combine_nested_undef_test19:
1120 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1121 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[0,0]
1122 ; SSE2-NEXT: movaps %xmm1, %xmm0
1125 ; SSSE3-LABEL: combine_nested_undef_test19:
1127 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1128 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[0,0]
1129 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1132 ; SSE41-LABEL: combine_nested_undef_test19:
1134 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1135 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
1138 ; AVX1-LABEL: combine_nested_undef_test19:
1140 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1141 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
1144 ; AVX2-LABEL: combine_nested_undef_test19:
1146 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
1147 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
1149 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
1150 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
1154 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
1155 ; SSE2-LABEL: combine_nested_undef_test20:
1157 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
1158 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
1159 ; SSE2-NEXT: movaps %xmm1, %xmm0
1162 ; SSSE3-LABEL: combine_nested_undef_test20:
1164 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
1165 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
1166 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1169 ; SSE41-LABEL: combine_nested_undef_test20:
1171 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
1172 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,3,0]
1175 ; AVX1-LABEL: combine_nested_undef_test20:
1177 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
1178 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,3,0]
1181 ; AVX2-LABEL: combine_nested_undef_test20:
1183 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
1184 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,3,0]
1186 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
1187 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1191 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
1192 ; SSE2-LABEL: combine_nested_undef_test21:
1194 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,2,3]
1195 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,1,1]
1196 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
1199 ; SSSE3-LABEL: combine_nested_undef_test21:
1201 ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,2,3]
1202 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,1,1]
1203 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
1206 ; SSE41-LABEL: combine_nested_undef_test21:
1208 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1209 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1212 ; AVX1-LABEL: combine_nested_undef_test21:
1214 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1215 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1218 ; AVX2-LABEL: combine_nested_undef_test21:
1220 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1221 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1223 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
1224 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1229 ; Test that we correctly combine shuffles according to rule
1230 ; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
1232 define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
1233 ; SSE-LABEL: combine_nested_undef_test22:
1235 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1238 ; AVX-LABEL: combine_nested_undef_test22:
1240 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1242 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1243 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
1247 define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1248 ; SSE-LABEL: combine_nested_undef_test23:
1250 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1253 ; AVX-LABEL: combine_nested_undef_test23:
1255 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1257 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1258 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1262 define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1263 ; SSE-LABEL: combine_nested_undef_test24:
1265 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1268 ; AVX-LABEL: combine_nested_undef_test24:
1270 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1272 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1273 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1277 define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1278 ; SSE-LABEL: combine_nested_undef_test25:
1280 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1283 ; AVX1-LABEL: combine_nested_undef_test25:
1285 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1288 ; AVX2-LABEL: combine_nested_undef_test25:
1290 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1292 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1293 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1297 define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1298 ; SSE-LABEL: combine_nested_undef_test26:
1300 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1303 ; AVX-LABEL: combine_nested_undef_test26:
1305 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1307 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1308 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1312 define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1313 ; SSE-LABEL: combine_nested_undef_test27:
1315 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1318 ; AVX1-LABEL: combine_nested_undef_test27:
1320 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1323 ; AVX2-LABEL: combine_nested_undef_test27:
1325 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1327 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1328 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1332 define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1333 ; SSE-LABEL: combine_nested_undef_test28:
1335 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1338 ; AVX-LABEL: combine_nested_undef_test28:
1340 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1342 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1343 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1347 define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1348 ; SSE-LABEL: combine_test1:
1350 ; SSE-NEXT: movaps %xmm1, %xmm0
1353 ; AVX-LABEL: combine_test1:
1355 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1357 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1358 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1362 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1363 ; SSE2-LABEL: combine_test2:
1365 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1366 ; SSE2-NEXT: movaps %xmm1, %xmm0
1369 ; SSSE3-LABEL: combine_test2:
1371 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1372 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1375 ; SSE41-LABEL: combine_test2:
1377 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1380 ; AVX-LABEL: combine_test2:
1382 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1384 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1385 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1389 define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1390 ; SSE-LABEL: combine_test3:
1392 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1395 ; AVX-LABEL: combine_test3:
1397 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1399 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1400 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1404 define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1405 ; SSE-LABEL: combine_test4:
1407 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1408 ; SSE-NEXT: movapd %xmm1, %xmm0
1411 ; AVX-LABEL: combine_test4:
1413 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1415 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1416 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1420 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1421 ; SSE2-LABEL: combine_test5:
1423 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1424 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1427 ; SSSE3-LABEL: combine_test5:
1429 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1430 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1433 ; SSE41-LABEL: combine_test5:
1435 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1438 ; AVX-LABEL: combine_test5:
1440 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1442 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1443 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1447 define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1448 ; SSE-LABEL: combine_test6:
1450 ; SSE-NEXT: movaps %xmm1, %xmm0
1453 ; AVX-LABEL: combine_test6:
1455 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1457 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1458 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1462 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1463 ; SSE2-LABEL: combine_test7:
1465 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1466 ; SSE2-NEXT: movaps %xmm1, %xmm0
1469 ; SSSE3-LABEL: combine_test7:
1471 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1472 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1475 ; SSE41-LABEL: combine_test7:
1477 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1480 ; AVX1-LABEL: combine_test7:
1482 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1485 ; AVX2-LABEL: combine_test7:
1487 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1489 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1490 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1494 define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1495 ; SSE-LABEL: combine_test8:
1497 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1500 ; AVX-LABEL: combine_test8:
1502 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1504 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1505 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1509 define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1510 ; SSE-LABEL: combine_test9:
1512 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1513 ; SSE-NEXT: movdqa %xmm1, %xmm0
1516 ; AVX-LABEL: combine_test9:
1518 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1520 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1521 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1525 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1526 ; SSE2-LABEL: combine_test10:
1528 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1529 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1532 ; SSSE3-LABEL: combine_test10:
1534 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1535 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1538 ; SSE41-LABEL: combine_test10:
1540 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1543 ; AVX1-LABEL: combine_test10:
1545 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1548 ; AVX2-LABEL: combine_test10:
1550 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1552 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1553 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1557 define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1558 ; ALL-LABEL: combine_test11:
1561 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1562 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1566 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1567 ; SSE2-LABEL: combine_test12:
1569 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1570 ; SSE2-NEXT: movaps %xmm1, %xmm0
1573 ; SSSE3-LABEL: combine_test12:
1575 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1576 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1579 ; SSE41-LABEL: combine_test12:
1581 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1584 ; AVX-LABEL: combine_test12:
1586 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1588 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1589 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1593 define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1594 ; SSE-LABEL: combine_test13:
1596 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1599 ; AVX-LABEL: combine_test13:
1601 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1603 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1604 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1608 define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1609 ; SSE-LABEL: combine_test14:
1611 ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1614 ; AVX-LABEL: combine_test14:
1616 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1618 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1619 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1623 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1624 ; SSE2-LABEL: combine_test15:
1626 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1627 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1630 ; SSSE3-LABEL: combine_test15:
1632 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1633 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1636 ; SSE41-LABEL: combine_test15:
1638 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1641 ; AVX-LABEL: combine_test15:
1643 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1645 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1646 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1650 define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1651 ; ALL-LABEL: combine_test16:
1654 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1655 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1659 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1660 ; SSE2-LABEL: combine_test17:
1662 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1663 ; SSE2-NEXT: movaps %xmm1, %xmm0
1666 ; SSSE3-LABEL: combine_test17:
1668 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1669 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1672 ; SSE41-LABEL: combine_test17:
1674 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1677 ; AVX1-LABEL: combine_test17:
1679 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1682 ; AVX2-LABEL: combine_test17:
1684 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1686 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1687 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1691 define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1692 ; SSE-LABEL: combine_test18:
1694 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1697 ; AVX-LABEL: combine_test18:
1699 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1701 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1702 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1706 define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1707 ; SSE-LABEL: combine_test19:
1709 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1712 ; AVX-LABEL: combine_test19:
1714 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1716 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1717 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1721 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1722 ; SSE2-LABEL: combine_test20:
1724 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1725 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1728 ; SSSE3-LABEL: combine_test20:
1730 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1731 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1734 ; SSE41-LABEL: combine_test20:
1736 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1739 ; AVX1-LABEL: combine_test20:
1741 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1744 ; AVX2-LABEL: combine_test20:
1746 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1748 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1749 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1753 define <4 x i32> @combine_test21(<8 x i32> %a, <4 x i32>* %ptr) {
1754 ; SSE-LABEL: combine_test21:
1756 ; SSE-NEXT: movdqa %xmm0, %xmm2
1757 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
1758 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1759 ; SSE-NEXT: movdqa %xmm2, (%rdi)
1762 ; AVX1-LABEL: combine_test21:
1764 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
1765 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1766 ; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1767 ; AVX1-NEXT: vmovdqa %xmm2, (%rdi)
1768 ; AVX1-NEXT: vzeroupper
1771 ; AVX2-LABEL: combine_test21:
1773 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1774 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1775 ; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1776 ; AVX2-NEXT: vmovdqa %xmm2, (%rdi)
1777 ; AVX2-NEXT: vzeroupper
1779 %1 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1780 %2 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
1781 store <4 x i32> %1, <4 x i32>* %ptr, align 16
1785 define <8 x float> @combine_test22(<2 x float>* %a, <2 x float>* %b) {
1786 ; SSE-LABEL: combine_test22:
1788 ; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
1789 ; SSE-NEXT: movhpd (%rsi), %xmm0
1792 ; AVX-LABEL: combine_test22:
1794 ; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
1795 ; AVX-NEXT: vmovhpd (%rsi), %xmm0, %xmm0
1797 ; Current AVX2 lowering of this is still awful, not adding a test case.
1798 %1 = load <2 x float>* %a, align 8
1799 %2 = load <2 x float>* %b, align 8
1800 %3 = shufflevector <2 x float> %1, <2 x float> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
1804 ; Check some negative cases.
1805 ; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1807 define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1808 ; SSE-LABEL: combine_test1b:
1810 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,2,0]
1811 ; SSE-NEXT: movaps %xmm1, %xmm0
1814 ; AVX-LABEL: combine_test1b:
1816 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[0,1,2,0]
1818 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1819 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1823 define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1824 ; SSE2-LABEL: combine_test2b:
1826 ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0,0]
1827 ; SSE2-NEXT: movaps %xmm1, %xmm0
1830 ; SSSE3-LABEL: combine_test2b:
1832 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
1835 ; SSE41-LABEL: combine_test2b:
1837 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
1840 ; AVX-LABEL: combine_test2b:
1842 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm1[0,0]
1844 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1845 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
1849 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1850 ; SSE2-LABEL: combine_test3b:
1852 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
1853 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
1856 ; SSSE3-LABEL: combine_test3b:
1858 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
1859 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
1862 ; SSE41-LABEL: combine_test3b:
1864 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
1865 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3,2,3]
1868 ; AVX-LABEL: combine_test3b:
1870 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
1871 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,3,2,3]
1873 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1874 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1878 define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1879 ; SSE-LABEL: combine_test4b:
1881 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
1882 ; SSE-NEXT: movaps %xmm1, %xmm0
1885 ; AVX-LABEL: combine_test4b:
1887 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[1,1,2,3]
1889 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1890 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1895 ; Verify that we correctly fold shuffles even when we use illegal vector types.
1897 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1898 ; SSE2-LABEL: combine_test1c:
1900 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1901 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1902 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1903 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1904 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1905 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1906 ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1909 ; SSSE3-LABEL: combine_test1c:
1911 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1912 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1913 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1914 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1915 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1916 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1917 ; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1920 ; SSE41-LABEL: combine_test1c:
1922 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1923 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1924 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1927 ; AVX1-LABEL: combine_test1c:
1929 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1930 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1931 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1934 ; AVX2-LABEL: combine_test1c:
1936 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1937 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1938 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1940 %A = load <4 x i8>* %a
1941 %B = load <4 x i8>* %b
1942 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1943 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1947 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1948 ; SSE2-LABEL: combine_test2c:
1950 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1951 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1952 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1953 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1954 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1955 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1956 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1959 ; SSSE3-LABEL: combine_test2c:
1961 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1962 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1963 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1964 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1965 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1966 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1967 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1970 ; SSE41-LABEL: combine_test2c:
1972 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1973 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1974 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1977 ; AVX-LABEL: combine_test2c:
1979 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1980 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1981 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1983 %A = load <4 x i8>* %a
1984 %B = load <4 x i8>* %b
1985 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1986 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1990 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1991 ; SSE2-LABEL: combine_test3c:
1993 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1994 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1995 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1996 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1997 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1998 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1999 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
2002 ; SSSE3-LABEL: combine_test3c:
2004 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
2005 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
2006 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
2007 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
2008 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
2009 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
2010 ; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
2013 ; SSE41-LABEL: combine_test3c:
2015 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2016 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2017 ; SSE41-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
2020 ; AVX-LABEL: combine_test3c:
2022 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2023 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2024 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2026 %A = load <4 x i8>* %a
2027 %B = load <4 x i8>* %b
2028 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2029 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2033 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
2034 ; SSE2-LABEL: combine_test4c:
2036 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
2037 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
2038 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
2039 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
2040 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
2041 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
2042 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
2043 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
2046 ; SSSE3-LABEL: combine_test4c:
2048 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
2049 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
2050 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
2051 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
2052 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
2053 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
2054 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
2055 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
2058 ; SSE41-LABEL: combine_test4c:
2060 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2061 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2062 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
2065 ; AVX1-LABEL: combine_test4c:
2067 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2068 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2069 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
2072 ; AVX2-LABEL: combine_test4c:
2074 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2075 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2076 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
2078 %A = load <4 x i8>* %a
2079 %B = load <4 x i8>* %b
2080 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
2081 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2086 ; The following test cases are generated from this C++ code
2088 ;__m128 blend_01(__m128 a, __m128 b)
2091 ; s = _mm_blend_ps( s, b, 1<<0 );
2092 ; s = _mm_blend_ps( s, b, 1<<1 );
2096 ;__m128 blend_02(__m128 a, __m128 b)
2099 ; s = _mm_blend_ps( s, b, 1<<0 );
2100 ; s = _mm_blend_ps( s, b, 1<<2 );
2104 ;__m128 blend_123(__m128 a, __m128 b)
2107 ; s = _mm_blend_ps( s, b, 1<<1 );
2108 ; s = _mm_blend_ps( s, b, 1<<2 );
2109 ; s = _mm_blend_ps( s, b, 1<<3 );
2113 ; Ideally, we should collapse the following shuffles into a single one.
2115 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
2116 ; SSE2-LABEL: combine_blend_01:
2118 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2121 ; SSSE3-LABEL: combine_blend_01:
2123 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2126 ; SSE41-LABEL: combine_blend_01:
2128 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2131 ; AVX-LABEL: combine_blend_01:
2133 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2135 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
2136 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
2137 ret <4 x float> %shuffle6
2140 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
2141 ; SSE2-LABEL: combine_blend_02:
2143 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
2144 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
2145 ; SSE2-NEXT: movaps %xmm1, %xmm0
2148 ; SSSE3-LABEL: combine_blend_02:
2150 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
2151 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
2152 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2155 ; SSE41-LABEL: combine_blend_02:
2157 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2160 ; AVX-LABEL: combine_blend_02:
2162 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2164 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
2165 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
2166 ret <4 x float> %shuffle6
2169 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
2170 ; SSE2-LABEL: combine_blend_123:
2172 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
2173 ; SSE2-NEXT: movaps %xmm1, %xmm0
2176 ; SSSE3-LABEL: combine_blend_123:
2178 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
2179 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2182 ; SSE41-LABEL: combine_blend_123:
2184 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2187 ; AVX-LABEL: combine_blend_123:
2189 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2191 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
2192 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
2193 %shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2194 ret <4 x float> %shuffle12
2197 define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
2198 ; SSE-LABEL: combine_test_movhl_1:
2200 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2201 ; SSE-NEXT: movdqa %xmm1, %xmm0
2204 ; AVX-LABEL: combine_test_movhl_1:
2206 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2208 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
2209 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
2213 define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
2214 ; SSE-LABEL: combine_test_movhl_2:
2216 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2217 ; SSE-NEXT: movdqa %xmm1, %xmm0
2220 ; AVX-LABEL: combine_test_movhl_2:
2222 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2224 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
2225 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
2229 define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
2230 ; SSE-LABEL: combine_test_movhl_3:
2232 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2233 ; SSE-NEXT: movdqa %xmm1, %xmm0
2236 ; AVX-LABEL: combine_test_movhl_3:
2238 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2240 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
2241 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>
2246 ; Verify that we fold shuffles according to rule:
2247 ; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
2249 define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
2250 ; SSE2-LABEL: combine_undef_input_test1:
2252 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2255 ; SSSE3-LABEL: combine_undef_input_test1:
2257 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2260 ; SSE41-LABEL: combine_undef_input_test1:
2262 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2265 ; AVX-LABEL: combine_undef_input_test1:
2267 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2269 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2270 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2274 define <4 x float> @combine_undef_input_test2(<4 x float> %a, <4 x float> %b) {
2275 ; SSE-LABEL: combine_undef_input_test2:
2277 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2280 ; AVX-LABEL: combine_undef_input_test2:
2282 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2284 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2285 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2289 define <4 x float> @combine_undef_input_test3(<4 x float> %a, <4 x float> %b) {
2290 ; SSE-LABEL: combine_undef_input_test3:
2292 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2295 ; AVX-LABEL: combine_undef_input_test3:
2297 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2299 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2300 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2304 define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
2305 ; SSE-LABEL: combine_undef_input_test4:
2307 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2308 ; SSE-NEXT: movapd %xmm1, %xmm0
2311 ; AVX-LABEL: combine_undef_input_test4:
2313 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2315 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2316 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2320 define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
2321 ; SSE2-LABEL: combine_undef_input_test5:
2323 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2324 ; SSE2-NEXT: movapd %xmm1, %xmm0
2327 ; SSSE3-LABEL: combine_undef_input_test5:
2329 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2330 ; SSSE3-NEXT: movapd %xmm1, %xmm0
2333 ; SSE41-LABEL: combine_undef_input_test5:
2335 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2338 ; AVX-LABEL: combine_undef_input_test5:
2340 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2342 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2343 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2348 ; Verify that we fold shuffles according to rule:
2349 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2351 define <4 x float> @combine_undef_input_test6(<4 x float> %a) {
2352 ; ALL-LABEL: combine_undef_input_test6:
2355 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2356 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2360 define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
2361 ; SSE2-LABEL: combine_undef_input_test7:
2363 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2366 ; SSSE3-LABEL: combine_undef_input_test7:
2368 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2371 ; SSE41-LABEL: combine_undef_input_test7:
2373 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2376 ; AVX-LABEL: combine_undef_input_test7:
2378 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2380 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2381 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2385 define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
2386 ; SSE2-LABEL: combine_undef_input_test8:
2388 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2391 ; SSSE3-LABEL: combine_undef_input_test8:
2393 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2396 ; SSE41-LABEL: combine_undef_input_test8:
2398 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2401 ; AVX-LABEL: combine_undef_input_test8:
2403 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2405 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2406 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2410 define <4 x float> @combine_undef_input_test9(<4 x float> %a) {
2411 ; SSE-LABEL: combine_undef_input_test9:
2413 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2416 ; AVX-LABEL: combine_undef_input_test9:
2418 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2420 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2421 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2425 define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
2426 ; ALL-LABEL: combine_undef_input_test10:
2429 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2430 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2434 define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
2435 ; SSE2-LABEL: combine_undef_input_test11:
2437 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2440 ; SSSE3-LABEL: combine_undef_input_test11:
2442 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2445 ; SSE41-LABEL: combine_undef_input_test11:
2447 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2450 ; AVX-LABEL: combine_undef_input_test11:
2452 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2454 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2455 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 6>
2459 define <4 x float> @combine_undef_input_test12(<4 x float> %a, <4 x float> %b) {
2460 ; SSE-LABEL: combine_undef_input_test12:
2462 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2465 ; AVX-LABEL: combine_undef_input_test12:
2467 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2469 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2470 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2474 define <4 x float> @combine_undef_input_test13(<4 x float> %a, <4 x float> %b) {
2475 ; SSE-LABEL: combine_undef_input_test13:
2477 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2480 ; AVX-LABEL: combine_undef_input_test13:
2482 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2484 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2485 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 5, i32 0, i32 5>
2489 define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
2490 ; SSE-LABEL: combine_undef_input_test14:
2492 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2493 ; SSE-NEXT: movapd %xmm1, %xmm0
2496 ; AVX-LABEL: combine_undef_input_test14:
2498 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2500 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2501 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2505 define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
2506 ; SSE2-LABEL: combine_undef_input_test15:
2508 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2509 ; SSE2-NEXT: movapd %xmm1, %xmm0
2512 ; SSSE3-LABEL: combine_undef_input_test15:
2514 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2515 ; SSSE3-NEXT: movapd %xmm1, %xmm0
2518 ; SSE41-LABEL: combine_undef_input_test15:
2520 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2523 ; AVX-LABEL: combine_undef_input_test15:
2525 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2527 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2528 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2533 ; Verify that shuffles are canonicalized according to rules:
2534 ; shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
2536 ; This allows to trigger the following combine rule:
2537 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2539 ; As a result, all the shuffle pairs in each function below should be
2540 ; combined into a single legal shuffle operation.
2542 define <4 x float> @combine_undef_input_test16(<4 x float> %a) {
2543 ; ALL-LABEL: combine_undef_input_test16:
2546 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2547 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
2551 define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
2552 ; SSE2-LABEL: combine_undef_input_test17:
2554 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2557 ; SSSE3-LABEL: combine_undef_input_test17:
2559 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2562 ; SSE41-LABEL: combine_undef_input_test17:
2564 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2567 ; AVX-LABEL: combine_undef_input_test17:
2569 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2571 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2572 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2576 define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
2577 ; SSE2-LABEL: combine_undef_input_test18:
2579 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2582 ; SSSE3-LABEL: combine_undef_input_test18:
2584 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2587 ; SSE41-LABEL: combine_undef_input_test18:
2589 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2592 ; AVX-LABEL: combine_undef_input_test18:
2594 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2596 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2597 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
2601 define <4 x float> @combine_undef_input_test19(<4 x float> %a) {
2602 ; SSE-LABEL: combine_undef_input_test19:
2604 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2607 ; AVX-LABEL: combine_undef_input_test19:
2609 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2611 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2612 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2616 define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
2617 ; ALL-LABEL: combine_undef_input_test20:
2620 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2621 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2625 ; These tests are designed to test the ability to combine away unnecessary
2626 ; operations feeding into a shuffle. The AVX cases are the important ones as
2627 ; they leverage operations which cannot be done naturally on the entire vector
2628 ; and thus are decomposed into multiple smaller operations.
2630 define <8 x i32> @combine_unneeded_subvector1(<8 x i32> %a) {
2631 ; SSE-LABEL: combine_unneeded_subvector1:
2633 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2634 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
2635 ; SSE-NEXT: movdqa %xmm0, %xmm1
2638 ; AVX1-LABEL: combine_unneeded_subvector1:
2640 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2641 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2642 ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2643 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2646 ; AVX2-LABEL: combine_unneeded_subvector1:
2648 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2649 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
2650 ; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
2652 %b = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2653 %c = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
2657 define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
2658 ; SSE-LABEL: combine_unneeded_subvector2:
2660 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2661 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,2,1,0]
2662 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
2665 ; AVX1-LABEL: combine_unneeded_subvector2:
2667 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2668 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2669 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2670 ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2671 ; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2674 ; AVX2-LABEL: combine_unneeded_subvector2:
2676 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2677 ; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2678 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2680 %c = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2681 %d = shufflevector <8 x i32> %b, <8 x i32> %c, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>
2685 define <4 x float> @combine_insertps1(<4 x float> %a, <4 x float> %b) {
2686 ; SSE2-LABEL: combine_insertps1:
2688 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,0]
2689 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
2690 ; SSE2-NEXT: movaps %xmm1, %xmm0
2693 ; SSSE3-LABEL: combine_insertps1:
2695 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,0]
2696 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
2697 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2700 ; SSE41-LABEL: combine_insertps1:
2702 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2705 ; AVX-LABEL: combine_insertps1:
2707 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2710 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 6, i32 2, i32 4>
2711 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 5, i32 1, i32 6, i32 3>
2715 define <4 x float> @combine_insertps2(<4 x float> %a, <4 x float> %b) {
2716 ; SSE2-LABEL: combine_insertps2:
2718 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,0]
2719 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
2720 ; SSE2-NEXT: movaps %xmm1, %xmm0
2723 ; SSSE3-LABEL: combine_insertps2:
2725 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,0]
2726 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
2727 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2730 ; SSE41-LABEL: combine_insertps2:
2732 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2735 ; AVX-LABEL: combine_insertps2:
2737 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2740 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 1, i32 6, i32 7>
2741 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2745 define <4 x float> @combine_insertps3(<4 x float> %a, <4 x float> %b) {
2746 ; SSE2-LABEL: combine_insertps3:
2748 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
2749 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2752 ; SSSE3-LABEL: combine_insertps3:
2754 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
2755 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2758 ; SSE41-LABEL: combine_insertps3:
2760 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2763 ; AVX-LABEL: combine_insertps3:
2765 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2768 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2769 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 5, i32 3>
2773 define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) {
2774 ; SSE2-LABEL: combine_insertps4:
2776 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
2777 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2780 ; SSSE3-LABEL: combine_insertps4:
2782 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
2783 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2786 ; SSE41-LABEL: combine_insertps4:
2788 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2791 ; AVX-LABEL: combine_insertps4:
2793 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2796 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2797 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 6, i32 5>
2801 define <4 x float> @PR22377(<4 x float> %a, <4 x float> %b) {
2802 ; SSE-LABEL: PR22377:
2803 ; SSE: # BB#0: # %entry
2804 ; SSE-NEXT: movaps %xmm0, %xmm1
2805 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3,1,3]
2806 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,0,2]
2807 ; SSE-NEXT: addps %xmm0, %xmm1
2808 ; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
2811 ; AVX-LABEL: PR22377:
2812 ; AVX: # BB#0: # %entry
2813 ; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[1,3,1,3]
2814 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2]
2815 ; AVX-NEXT: vaddps %xmm0, %xmm1, %xmm1
2816 ; AVX-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
2819 %s1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 1, i32 3>
2820 %s2 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
2821 %r2 = fadd <4 x float> %s1, %s2
2822 %s3 = shufflevector <4 x float> %s2, <4 x float> %r2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
2826 define <4 x float> @PR22390(<4 x float> %a, <4 x float> %b) {
2827 ; SSE2-LABEL: PR22390:
2828 ; SSE2: # BB#0: # %entry
2829 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2830 ; SSE2-NEXT: movaps %xmm0, %xmm2
2831 ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
2832 ; SSE2-NEXT: addps %xmm0, %xmm2
2833 ; SSE2-NEXT: movaps %xmm2, %xmm0
2836 ; SSSE3-LABEL: PR22390:
2837 ; SSSE3: # BB#0: # %entry
2838 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2839 ; SSSE3-NEXT: movaps %xmm0, %xmm2
2840 ; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
2841 ; SSSE3-NEXT: addps %xmm0, %xmm2
2842 ; SSSE3-NEXT: movaps %xmm2, %xmm0
2845 ; SSE41-LABEL: PR22390:
2846 ; SSE41: # BB#0: # %entry
2847 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2848 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3]
2849 ; SSE41-NEXT: addps %xmm1, %xmm0
2852 ; AVX-LABEL: PR22390:
2853 ; AVX: # BB#0: # %entry
2854 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2855 ; AVX-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3]
2856 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
2859 %s1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
2860 %s2 = shufflevector <4 x float> %s1, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
2861 %r2 = fadd <4 x float> %s1, %s2
2865 define <8 x float> @PR22412(<8 x float> %a, <8 x float> %b) {
2866 ; SSE2-LABEL: PR22412:
2867 ; SSE2: # BB#0: # %entry
2868 ; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
2869 ; SSE2-NEXT: movapd %xmm2, %xmm0
2870 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm3[3,2]
2871 ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm2[3,2]
2872 ; SSE2-NEXT: movaps %xmm3, %xmm1
2875 ; SSSE3-LABEL: PR22412:
2876 ; SSSE3: # BB#0: # %entry
2877 ; SSSE3-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
2878 ; SSSE3-NEXT: movapd %xmm2, %xmm0
2879 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm3[3,2]
2880 ; SSSE3-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm2[3,2]
2881 ; SSSE3-NEXT: movaps %xmm3, %xmm1
2884 ; SSE41-LABEL: PR22412:
2885 ; SSE41: # BB#0: # %entry
2886 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm2[1]
2887 ; SSE41-NEXT: movapd %xmm0, %xmm1
2888 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm3[3,2]
2889 ; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm0[3,2]
2890 ; SSE41-NEXT: movaps %xmm1, %xmm0
2891 ; SSE41-NEXT: movaps %xmm3, %xmm1
2894 ; AVX1-LABEL: PR22412:
2895 ; AVX1: # BB#0: # %entry
2896 ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
2897 ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
2898 ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,0],ymm1[3,2],ymm0[5,4],ymm1[7,6]
2901 ; AVX2-LABEL: PR22412:
2902 ; AVX2: # BB#0: # %entry
2903 ; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
2904 ; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [1,0,7,6,5,4,3,2]
2905 ; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
2908 %s1 = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
2909 %s2 = shufflevector <8 x float> %s1, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2>