1 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7 ; Verify that the DAG combiner correctly folds bitwise operations across
8 ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
9 ; basic and always-safe patterns. Also test that the DAG combiner will combine
10 ; target-specific shuffle instructions where reasonable.
12 target triple = "x86_64-unknown-unknown"
14 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
15 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
16 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
18 define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
19 ; ALL-LABEL: combine_pshufd1:
20 ; ALL: # BB#0: # %entry
23 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
24 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
28 define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
29 ; ALL-LABEL: combine_pshufd2:
30 ; ALL: # BB#0: # %entry
33 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
34 %b.cast = bitcast <4 x i32> %b to <8 x i16>
35 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
36 %c.cast = bitcast <8 x i16> %c to <4 x i32>
37 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
41 define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
42 ; ALL-LABEL: combine_pshufd3:
43 ; ALL: # BB#0: # %entry
46 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
47 %b.cast = bitcast <4 x i32> %b to <8 x i16>
48 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
49 %c.cast = bitcast <8 x i16> %c to <4 x i32>
50 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
54 define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
55 ; SSE-LABEL: combine_pshufd4:
56 ; SSE: # BB#0: # %entry
57 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
60 ; AVX-LABEL: combine_pshufd4:
61 ; AVX: # BB#0: # %entry
62 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
65 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
66 %b.cast = bitcast <4 x i32> %b to <8 x i16>
67 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
68 %c.cast = bitcast <8 x i16> %c to <4 x i32>
69 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
73 define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
74 ; SSE-LABEL: combine_pshufd5:
75 ; SSE: # BB#0: # %entry
76 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
79 ; AVX-LABEL: combine_pshufd5:
80 ; AVX: # BB#0: # %entry
81 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
84 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
85 %b.cast = bitcast <4 x i32> %b to <8 x i16>
86 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
87 %c.cast = bitcast <8 x i16> %c to <4 x i32>
88 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
92 define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
93 ; SSE-LABEL: combine_pshufd6:
94 ; SSE: # BB#0: # %entry
95 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
98 ; AVX-LABEL: combine_pshufd6:
99 ; AVX: # BB#0: # %entry
100 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
103 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
104 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
108 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
109 ; ALL-LABEL: combine_pshuflw1:
110 ; ALL: # BB#0: # %entry
113 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
114 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
118 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
119 ; ALL-LABEL: combine_pshuflw2:
120 ; ALL: # BB#0: # %entry
123 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
124 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
125 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
129 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
130 ; SSE-LABEL: combine_pshuflw3:
131 ; SSE: # BB#0: # %entry
132 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
135 ; AVX-LABEL: combine_pshuflw3:
136 ; AVX: # BB#0: # %entry
137 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
140 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
141 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
142 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
146 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
147 ; SSE-LABEL: combine_pshufhw1:
148 ; SSE: # BB#0: # %entry
149 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
152 ; AVX-LABEL: combine_pshufhw1:
153 ; AVX: # BB#0: # %entry
154 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
157 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
158 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
159 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
163 define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164 ; SSE-LABEL: combine_bitwise_ops_test1:
166 ; SSE-NEXT: pand %xmm1, %xmm0
167 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
170 ; AVX-LABEL: combine_bitwise_ops_test1:
172 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
173 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
175 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
176 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177 %and = and <4 x i32> %shuf1, %shuf2
181 define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
182 ; SSE-LABEL: combine_bitwise_ops_test2:
184 ; SSE-NEXT: por %xmm1, %xmm0
185 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
188 ; AVX-LABEL: combine_bitwise_ops_test2:
190 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
191 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
193 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
194 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195 %or = or <4 x i32> %shuf1, %shuf2
199 define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
200 ; SSE-LABEL: combine_bitwise_ops_test3:
202 ; SSE-NEXT: pxor %xmm1, %xmm0
203 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
206 ; AVX-LABEL: combine_bitwise_ops_test3:
208 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
209 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
211 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
212 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213 %xor = xor <4 x i32> %shuf1, %shuf2
217 define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218 ; SSE-LABEL: combine_bitwise_ops_test4:
220 ; SSE-NEXT: pand %xmm1, %xmm0
221 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
224 ; AVX-LABEL: combine_bitwise_ops_test4:
226 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
227 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
229 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
230 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231 %and = and <4 x i32> %shuf1, %shuf2
235 define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
236 ; SSE-LABEL: combine_bitwise_ops_test5:
238 ; SSE-NEXT: por %xmm1, %xmm0
239 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
242 ; AVX-LABEL: combine_bitwise_ops_test5:
244 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
245 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
247 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
248 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249 %or = or <4 x i32> %shuf1, %shuf2
253 define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
254 ; SSE-LABEL: combine_bitwise_ops_test6:
256 ; SSE-NEXT: pxor %xmm1, %xmm0
257 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
260 ; AVX-LABEL: combine_bitwise_ops_test6:
262 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
263 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
265 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
266 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267 %xor = xor <4 x i32> %shuf1, %shuf2
272 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
273 ; are not performing a swizzle operations.
275 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
276 ; SSE2-LABEL: combine_bitwise_ops_test1b:
278 ; SSE2-NEXT: andps %xmm1, %xmm0
279 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
280 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
283 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
285 ; SSSE3-NEXT: andps %xmm1, %xmm0
286 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
287 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
290 ; SSE41-LABEL: combine_bitwise_ops_test1b:
292 ; SSE41-NEXT: pand %xmm1, %xmm0
293 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
296 ; AVX1-LABEL: combine_bitwise_ops_test1b:
298 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
299 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
302 ; AVX2-LABEL: combine_bitwise_ops_test1b:
304 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
305 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
307 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
308 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
309 %and = and <4 x i32> %shuf1, %shuf2
313 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
314 ; SSE2-LABEL: combine_bitwise_ops_test2b:
316 ; SSE2-NEXT: orps %xmm1, %xmm0
317 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
318 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
321 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
323 ; SSSE3-NEXT: orps %xmm1, %xmm0
324 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
325 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
328 ; SSE41-LABEL: combine_bitwise_ops_test2b:
330 ; SSE41-NEXT: por %xmm1, %xmm0
331 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
334 ; AVX1-LABEL: combine_bitwise_ops_test2b:
336 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
337 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
340 ; AVX2-LABEL: combine_bitwise_ops_test2b:
342 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
343 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
345 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
346 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
347 %or = or <4 x i32> %shuf1, %shuf2
351 define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
352 ; SSE2-LABEL: combine_bitwise_ops_test3b:
354 ; SSE2-NEXT: xorps %xmm1, %xmm0
355 ; SSE2-NEXT: xorps %xmm1, %xmm1
356 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
357 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
360 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
362 ; SSSE3-NEXT: xorps %xmm1, %xmm0
363 ; SSSE3-NEXT: xorps %xmm1, %xmm1
364 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
365 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
368 ; SSE41-LABEL: combine_bitwise_ops_test3b:
370 ; SSE41-NEXT: pxor %xmm1, %xmm0
371 ; SSE41-NEXT: pxor %xmm1, %xmm1
372 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
375 ; AVX1-LABEL: combine_bitwise_ops_test3b:
377 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
378 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
379 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
382 ; AVX2-LABEL: combine_bitwise_ops_test3b:
384 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
385 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
386 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
388 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
389 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
390 %xor = xor <4 x i32> %shuf1, %shuf2
394 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
395 ; SSE2-LABEL: combine_bitwise_ops_test4b:
397 ; SSE2-NEXT: andps %xmm1, %xmm0
398 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
399 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
402 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
404 ; SSSE3-NEXT: andps %xmm1, %xmm0
405 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
406 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
409 ; SSE41-LABEL: combine_bitwise_ops_test4b:
411 ; SSE41-NEXT: pand %xmm1, %xmm0
412 ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
413 ; SSE41-NEXT: movdqa %xmm2, %xmm0
416 ; AVX1-LABEL: combine_bitwise_ops_test4b:
418 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
419 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
422 ; AVX2-LABEL: combine_bitwise_ops_test4b:
424 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
425 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
427 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
428 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
429 %and = and <4 x i32> %shuf1, %shuf2
433 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
434 ; SSE2-LABEL: combine_bitwise_ops_test5b:
436 ; SSE2-NEXT: orps %xmm1, %xmm0
437 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
438 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
441 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
443 ; SSSE3-NEXT: orps %xmm1, %xmm0
444 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
445 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
448 ; SSE41-LABEL: combine_bitwise_ops_test5b:
450 ; SSE41-NEXT: por %xmm1, %xmm0
451 ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
452 ; SSE41-NEXT: movdqa %xmm2, %xmm0
455 ; AVX1-LABEL: combine_bitwise_ops_test5b:
457 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
458 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
461 ; AVX2-LABEL: combine_bitwise_ops_test5b:
463 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
464 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
466 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
467 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
468 %or = or <4 x i32> %shuf1, %shuf2
472 define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
473 ; SSE2-LABEL: combine_bitwise_ops_test6b:
475 ; SSE2-NEXT: xorps %xmm1, %xmm0
476 ; SSE2-NEXT: xorps %xmm1, %xmm1
477 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
478 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
479 ; SSE2-NEXT: movaps %xmm1, %xmm0
482 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
484 ; SSSE3-NEXT: xorps %xmm1, %xmm0
485 ; SSSE3-NEXT: xorps %xmm1, %xmm1
486 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
487 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
488 ; SSSE3-NEXT: movaps %xmm1, %xmm0
491 ; SSE41-LABEL: combine_bitwise_ops_test6b:
493 ; SSE41-NEXT: pxor %xmm1, %xmm0
494 ; SSE41-NEXT: pxor %xmm1, %xmm1
495 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
496 ; SSE41-NEXT: movdqa %xmm1, %xmm0
499 ; AVX1-LABEL: combine_bitwise_ops_test6b:
501 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
502 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
503 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
506 ; AVX2-LABEL: combine_bitwise_ops_test6b:
508 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
509 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
510 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
512 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
513 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
514 %xor = xor <4 x i32> %shuf1, %shuf2
518 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
519 ; SSE-LABEL: combine_bitwise_ops_test1c:
521 ; SSE-NEXT: andps %xmm1, %xmm0
522 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
525 ; AVX-LABEL: combine_bitwise_ops_test1c:
527 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
528 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
530 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
531 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
532 %and = and <4 x i32> %shuf1, %shuf2
536 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
537 ; SSE-LABEL: combine_bitwise_ops_test2c:
539 ; SSE-NEXT: orps %xmm1, %xmm0
540 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
543 ; AVX-LABEL: combine_bitwise_ops_test2c:
545 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
546 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
548 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
549 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
550 %or = or <4 x i32> %shuf1, %shuf2
554 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
555 ; SSE-LABEL: combine_bitwise_ops_test3c:
557 ; SSE-NEXT: xorps %xmm1, %xmm0
558 ; SSE-NEXT: xorps %xmm1, %xmm1
559 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
562 ; AVX-LABEL: combine_bitwise_ops_test3c:
564 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
565 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
566 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
568 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
569 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
570 %xor = xor <4 x i32> %shuf1, %shuf2
574 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
575 ; SSE-LABEL: combine_bitwise_ops_test4c:
577 ; SSE-NEXT: andps %xmm1, %xmm0
578 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
579 ; SSE-NEXT: movaps %xmm2, %xmm0
582 ; AVX-LABEL: combine_bitwise_ops_test4c:
584 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
585 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
587 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
588 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
589 %and = and <4 x i32> %shuf1, %shuf2
593 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
594 ; SSE-LABEL: combine_bitwise_ops_test5c:
596 ; SSE-NEXT: orps %xmm1, %xmm0
597 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
598 ; SSE-NEXT: movaps %xmm2, %xmm0
601 ; AVX-LABEL: combine_bitwise_ops_test5c:
603 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
604 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
606 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
607 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
608 %or = or <4 x i32> %shuf1, %shuf2
612 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
613 ; SSE-LABEL: combine_bitwise_ops_test6c:
615 ; SSE-NEXT: xorps %xmm1, %xmm0
616 ; SSE-NEXT: xorps %xmm1, %xmm1
617 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
618 ; SSE-NEXT: movaps %xmm1, %xmm0
621 ; AVX-LABEL: combine_bitwise_ops_test6c:
623 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
624 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
625 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[1,3]
627 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
628 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
629 %xor = xor <4 x i32> %shuf1, %shuf2
633 define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
634 ; SSE-LABEL: combine_nested_undef_test1:
636 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
639 ; AVX-LABEL: combine_nested_undef_test1:
641 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
643 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
644 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
648 define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
649 ; SSE-LABEL: combine_nested_undef_test2:
651 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
654 ; AVX-LABEL: combine_nested_undef_test2:
656 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
658 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
659 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
663 define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
664 ; SSE-LABEL: combine_nested_undef_test3:
666 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
669 ; AVX-LABEL: combine_nested_undef_test3:
671 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
673 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
674 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
678 define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
679 ; SSE-LABEL: combine_nested_undef_test4:
681 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
684 ; AVX1-LABEL: combine_nested_undef_test4:
686 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
689 ; AVX2-LABEL: combine_nested_undef_test4:
691 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
693 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
694 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
698 define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
699 ; SSE-LABEL: combine_nested_undef_test5:
701 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
704 ; AVX-LABEL: combine_nested_undef_test5:
706 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
708 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
709 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
713 define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
714 ; SSE-LABEL: combine_nested_undef_test6:
716 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
719 ; AVX-LABEL: combine_nested_undef_test6:
721 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
723 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
724 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
728 define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
729 ; SSE-LABEL: combine_nested_undef_test7:
731 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
734 ; AVX-LABEL: combine_nested_undef_test7:
736 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
738 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
739 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
743 define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
744 ; SSE-LABEL: combine_nested_undef_test8:
746 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
749 ; AVX-LABEL: combine_nested_undef_test8:
751 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
753 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
754 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
758 define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
759 ; SSE-LABEL: combine_nested_undef_test9:
761 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
764 ; AVX-LABEL: combine_nested_undef_test9:
766 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
768 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
769 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
773 define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
774 ; SSE-LABEL: combine_nested_undef_test10:
776 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
779 ; AVX-LABEL: combine_nested_undef_test10:
781 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
783 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
784 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
788 define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
789 ; SSE-LABEL: combine_nested_undef_test11:
791 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
794 ; AVX-LABEL: combine_nested_undef_test11:
796 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
798 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
799 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
803 define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
804 ; SSE-LABEL: combine_nested_undef_test12:
806 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
809 ; AVX1-LABEL: combine_nested_undef_test12:
811 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
814 ; AVX2-LABEL: combine_nested_undef_test12:
816 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
818 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
819 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
823 ; The following pair of shuffles is folded into vector %A.
824 define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
825 ; ALL-LABEL: combine_nested_undef_test13:
828 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
829 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
833 ; The following pair of shuffles is folded into vector %B.
834 define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
835 ; SSE-LABEL: combine_nested_undef_test14:
837 ; SSE-NEXT: movaps %xmm1, %xmm0
840 ; AVX-LABEL: combine_nested_undef_test14:
842 ; AVX-NEXT: vmovaps %xmm1, %xmm0
844 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
845 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
850 ; Verify that we don't optimize the following cases. We expect more than one shuffle.
852 ; FIXME: Many of these already don't make sense, and the rest should stop
853 ; making sense with th enew vector shuffle lowering. Revisit at least testing for
856 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
857 ; SSE-LABEL: combine_nested_undef_test15:
859 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
860 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,1]
861 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
864 ; AVX-LABEL: combine_nested_undef_test15:
866 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
867 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[3,1]
868 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
870 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
871 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
875 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
876 ; SSE2-LABEL: combine_nested_undef_test16:
878 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
879 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
880 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
883 ; SSSE3-LABEL: combine_nested_undef_test16:
885 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
886 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
887 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
890 ; SSE41-LABEL: combine_nested_undef_test16:
892 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
893 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
896 ; AVX1-LABEL: combine_nested_undef_test16:
898 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
899 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
902 ; AVX2-LABEL: combine_nested_undef_test16:
904 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
905 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
907 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
908 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
912 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
913 ; SSE-LABEL: combine_nested_undef_test17:
915 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
916 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
917 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
920 ; AVX-LABEL: combine_nested_undef_test17:
922 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
923 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
924 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
926 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
927 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
931 define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
932 ; SSE-LABEL: combine_nested_undef_test18:
934 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
937 ; AVX-LABEL: combine_nested_undef_test18:
939 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
941 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
942 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
946 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
947 ; SSE-LABEL: combine_nested_undef_test19:
949 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
950 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
951 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
954 ; AVX-LABEL: combine_nested_undef_test19:
956 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
957 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
958 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
960 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
961 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
965 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
966 ; SSE-LABEL: combine_nested_undef_test20:
968 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
969 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
972 ; AVX-LABEL: combine_nested_undef_test20:
974 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
975 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
977 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
978 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
982 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
983 ; SSE-LABEL: combine_nested_undef_test21:
985 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
986 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
987 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
990 ; AVX-LABEL: combine_nested_undef_test21:
992 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
993 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
994 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
996 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
997 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1002 ; Test that we correctly combine shuffles according to rule
1003 ; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
1005 define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
1006 ; SSE-LABEL: combine_nested_undef_test22:
1008 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1011 ; AVX-LABEL: combine_nested_undef_test22:
1013 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1015 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1016 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
1020 define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1021 ; SSE-LABEL: combine_nested_undef_test23:
1023 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1026 ; AVX-LABEL: combine_nested_undef_test23:
1028 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1030 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1031 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1035 define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1036 ; SSE-LABEL: combine_nested_undef_test24:
1038 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1041 ; AVX-LABEL: combine_nested_undef_test24:
1043 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1045 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1046 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1050 define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1051 ; SSE-LABEL: combine_nested_undef_test25:
1053 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1056 ; AVX1-LABEL: combine_nested_undef_test25:
1058 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1061 ; AVX2-LABEL: combine_nested_undef_test25:
1063 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1065 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1066 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1070 define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1071 ; SSE-LABEL: combine_nested_undef_test26:
1073 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1076 ; AVX-LABEL: combine_nested_undef_test26:
1078 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1080 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1081 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1085 define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1086 ; SSE-LABEL: combine_nested_undef_test27:
1088 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1091 ; AVX1-LABEL: combine_nested_undef_test27:
1093 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1096 ; AVX2-LABEL: combine_nested_undef_test27:
1098 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1100 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1101 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1105 define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1106 ; SSE-LABEL: combine_nested_undef_test28:
1108 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1111 ; AVX-LABEL: combine_nested_undef_test28:
1113 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1115 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1116 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1120 define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1121 ; SSE2-LABEL: combine_test1:
1123 ; SSE2-NEXT: movaps %xmm1, %xmm2
1124 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1125 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1126 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,3]
1127 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
1130 ; SSSE3-LABEL: combine_test1:
1132 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1135 ; SSE41-LABEL: combine_test1:
1137 ; SSE41-NEXT: movaps %xmm1, %xmm0
1140 ; AVX-LABEL: combine_test1:
1142 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1144 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1145 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1149 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1150 ; SSE2-LABEL: combine_test2:
1152 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1153 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1154 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1155 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1158 ; SSSE3-LABEL: combine_test2:
1160 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1161 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1162 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1163 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1166 ; SSE41-LABEL: combine_test2:
1168 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1169 ; SSE41-NEXT: movaps %xmm1, %xmm0
1172 ; AVX-LABEL: combine_test2:
1174 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1176 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1177 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1181 define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1182 ; SSE-LABEL: combine_test3:
1184 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1187 ; AVX-LABEL: combine_test3:
1189 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1191 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1192 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1196 define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1197 ; SSE-LABEL: combine_test4:
1199 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1200 ; SSE-NEXT: movapd %xmm1, %xmm0
1203 ; AVX-LABEL: combine_test4:
1205 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1207 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1208 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1212 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1213 ; SSE2-LABEL: combine_test5:
1215 ; SSE2-NEXT: movaps %xmm1, %xmm2
1216 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1217 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1218 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1219 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1220 ; SSE2-NEXT: movaps %xmm2, %xmm0
1223 ; SSSE3-LABEL: combine_test5:
1225 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1226 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1227 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1228 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1229 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1230 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1233 ; SSE41-LABEL: combine_test5:
1235 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1],xmm1[2,3]
1236 ; SSE41-NEXT: movaps %xmm1, %xmm0
1239 ; AVX-LABEL: combine_test5:
1241 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1243 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1244 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1248 define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1249 ; SSE2-LABEL: combine_test6:
1251 ; SSE2-NEXT: movaps %xmm1, %xmm2
1252 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1253 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1254 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,3]
1255 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
1258 ; SSSE3-LABEL: combine_test6:
1260 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1263 ; SSE41-LABEL: combine_test6:
1265 ; SSE41-NEXT: movaps %xmm1, %xmm0
1268 ; AVX-LABEL: combine_test6:
1270 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1272 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1273 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1277 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1278 ; SSE2-LABEL: combine_test7:
1280 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1281 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1282 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1283 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1286 ; SSSE3-LABEL: combine_test7:
1288 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1289 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1290 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1291 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1294 ; SSE41-LABEL: combine_test7:
1296 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1297 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1300 ; AVX1-LABEL: combine_test7:
1302 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1305 ; AVX2-LABEL: combine_test7:
1307 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1309 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1310 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1314 define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1315 ; SSE-LABEL: combine_test8:
1317 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1320 ; AVX-LABEL: combine_test8:
1322 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1324 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1325 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1329 define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1330 ; SSE-LABEL: combine_test9:
1332 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1333 ; SSE-NEXT: movdqa %xmm1, %xmm0
1336 ; AVX-LABEL: combine_test9:
1338 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1340 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1341 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1345 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1346 ; SSE2-LABEL: combine_test10:
1348 ; SSE2-NEXT: movaps %xmm1, %xmm2
1349 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1350 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1351 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1352 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1353 ; SSE2-NEXT: movaps %xmm2, %xmm0
1356 ; SSSE3-LABEL: combine_test10:
1358 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1359 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1360 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1361 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1362 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1363 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1366 ; SSE41-LABEL: combine_test10:
1368 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1369 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1372 ; AVX1-LABEL: combine_test10:
1374 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1377 ; AVX2-LABEL: combine_test10:
1379 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1381 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1382 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1386 define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1387 ; ALL-LABEL: combine_test11:
1390 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1391 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1395 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1396 ; SSE2-LABEL: combine_test12:
1398 ; SSE2-NEXT: movss %xmm0, %xmm1
1399 ; SSE2-NEXT: movss %xmm0, %xmm1
1400 ; SSE2-NEXT: movaps %xmm1, %xmm0
1403 ; SSSE3-LABEL: combine_test12:
1405 ; SSSE3-NEXT: movss %xmm0, %xmm1
1406 ; SSSE3-NEXT: movss %xmm0, %xmm1
1407 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1410 ; SSE41-LABEL: combine_test12:
1412 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1413 ; SSE41-NEXT: movaps %xmm1, %xmm0
1416 ; AVX-LABEL: combine_test12:
1418 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1420 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1421 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1425 define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1426 ; SSE-LABEL: combine_test13:
1428 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1431 ; AVX-LABEL: combine_test13:
1433 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1435 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1436 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1440 define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1441 ; SSE-LABEL: combine_test14:
1443 ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1446 ; AVX-LABEL: combine_test14:
1448 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1450 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1451 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1455 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1456 ; SSE2-LABEL: combine_test15:
1458 ; SSE2-NEXT: movaps %xmm0, %xmm2
1459 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1460 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1461 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1462 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1465 ; SSSE3-LABEL: combine_test15:
1467 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1468 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1469 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1470 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1471 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1474 ; SSE41-LABEL: combine_test15:
1476 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1],xmm1[2,3]
1477 ; SSE41-NEXT: movaps %xmm1, %xmm0
1480 ; AVX-LABEL: combine_test15:
1482 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1484 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1485 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1489 define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1490 ; ALL-LABEL: combine_test16:
1493 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1494 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1498 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1499 ; SSE2-LABEL: combine_test17:
1501 ; SSE2-NEXT: movss %xmm0, %xmm1
1502 ; SSE2-NEXT: movss %xmm0, %xmm1
1503 ; SSE2-NEXT: movaps %xmm1, %xmm0
1506 ; SSSE3-LABEL: combine_test17:
1508 ; SSSE3-NEXT: movss %xmm0, %xmm1
1509 ; SSSE3-NEXT: movss %xmm0, %xmm1
1510 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1513 ; SSE41-LABEL: combine_test17:
1515 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1516 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1519 ; AVX1-LABEL: combine_test17:
1521 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1524 ; AVX2-LABEL: combine_test17:
1526 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1528 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1529 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1533 define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1534 ; SSE-LABEL: combine_test18:
1536 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1539 ; AVX-LABEL: combine_test18:
1541 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1543 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1544 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1548 define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1549 ; SSE-LABEL: combine_test19:
1551 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1554 ; AVX-LABEL: combine_test19:
1556 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1558 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1559 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1563 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1564 ; SSE2-LABEL: combine_test20:
1566 ; SSE2-NEXT: movaps %xmm0, %xmm2
1567 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1568 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1569 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1570 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1573 ; SSSE3-LABEL: combine_test20:
1575 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1576 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1577 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1578 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1579 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1582 ; SSE41-LABEL: combine_test20:
1584 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1585 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1588 ; AVX1-LABEL: combine_test20:
1590 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1593 ; AVX2-LABEL: combine_test20:
1595 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1597 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1598 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1603 ; Check some negative cases.
1604 ; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1606 define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1607 ; SSE2-LABEL: combine_test1b:
1609 ; SSE2-NEXT: movaps %xmm1, %xmm2
1610 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1611 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1612 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]
1613 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
1614 ; SSE2-NEXT: movaps %xmm1, %xmm0
1617 ; SSSE3-LABEL: combine_test1b:
1619 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1620 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1621 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1622 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]
1623 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
1624 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1627 ; SSE41-LABEL: combine_test1b:
1629 ; SSE41-NEXT: movaps %xmm1, %xmm2
1630 ; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
1631 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]
1632 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
1633 ; SSE41-NEXT: movaps %xmm1, %xmm0
1636 ; AVX-LABEL: combine_test1b:
1638 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1639 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1640 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[2,0]
1642 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1643 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1647 define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1648 ; SSE2-LABEL: combine_test2b:
1650 ; SSE2-NEXT: movaps %xmm1, %xmm2
1651 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1652 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1653 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]
1654 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
1657 ; SSSE3-LABEL: combine_test2b:
1659 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1660 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1661 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1662 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]
1663 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
1666 ; SSE41-LABEL: combine_test2b:
1668 ; SSE41-NEXT: movaps %xmm1, %xmm2
1669 ; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
1670 ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]
1671 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
1674 ; AVX-LABEL: combine_test2b:
1676 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1677 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]
1678 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1680 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1681 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
1685 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1686 ; SSE-LABEL: combine_test3b:
1688 ; SSE-NEXT: movaps %xmm1, %xmm2
1689 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[3,0]
1690 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1691 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1692 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1695 ; AVX-LABEL: combine_test3b:
1697 ; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,0],xmm0[3,0]
1698 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1699 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1700 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1702 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1703 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1707 define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1708 ; SSE2-LABEL: combine_test4b:
1710 ; SSE2-NEXT: movaps %xmm1, %xmm2
1711 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1712 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1713 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
1714 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]
1715 ; SSE2-NEXT: movaps %xmm1, %xmm0
1718 ; SSSE3-LABEL: combine_test4b:
1720 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1721 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1722 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1723 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
1724 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]
1725 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1728 ; SSE41-LABEL: combine_test4b:
1730 ; SSE41-NEXT: movaps %xmm1, %xmm2
1731 ; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
1732 ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
1733 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]
1734 ; SSE41-NEXT: movaps %xmm1, %xmm0
1737 ; AVX-LABEL: combine_test4b:
1739 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1740 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
1741 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[1,1],xmm0[0,2]
1743 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1744 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1749 ; Verify that we correctly fold shuffles even when we use illegal vector types.
1751 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1752 ; SSE2-LABEL: combine_test1c:
1754 ; SSE2-NEXT: movd (%rdi), %xmm0
1755 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1756 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1757 ; SSE2-NEXT: movd (%rsi), %xmm1
1758 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1759 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1760 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1761 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1762 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1763 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1766 ; SSSE3-LABEL: combine_test1c:
1768 ; SSSE3-NEXT: movd (%rdi), %xmm0
1769 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1770 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1771 ; SSSE3-NEXT: movd (%rsi), %xmm1
1772 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1773 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1774 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1775 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1776 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1777 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1780 ; SSE41-LABEL: combine_test1c:
1782 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1783 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1784 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1787 ; AVX1-LABEL: combine_test1c:
1789 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1790 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1791 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1794 ; AVX2-LABEL: combine_test1c:
1796 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1797 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1798 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1800 %A = load <4 x i8>* %a
1801 %B = load <4 x i8>* %b
1802 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1803 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1807 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1808 ; SSE2-LABEL: combine_test2c:
1810 ; SSE2-NEXT: movd (%rdi), %xmm0
1811 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1812 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1813 ; SSE2-NEXT: movd (%rsi), %xmm1
1814 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1815 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1816 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1819 ; SSSE3-LABEL: combine_test2c:
1821 ; SSSE3-NEXT: movd (%rdi), %xmm0
1822 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1823 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1824 ; SSSE3-NEXT: movd (%rsi), %xmm1
1825 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1826 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1827 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1830 ; SSE41-LABEL: combine_test2c:
1832 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm0
1833 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm1
1834 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1837 ; AVX-LABEL: combine_test2c:
1839 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1840 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1841 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1843 %A = load <4 x i8>* %a
1844 %B = load <4 x i8>* %b
1845 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1846 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1850 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1851 ; SSE2-LABEL: combine_test3c:
1853 ; SSE2-NEXT: movd (%rdi), %xmm1
1854 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1855 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1856 ; SSE2-NEXT: movd (%rsi), %xmm0
1857 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1858 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1859 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1862 ; SSSE3-LABEL: combine_test3c:
1864 ; SSSE3-NEXT: movd (%rdi), %xmm1
1865 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1866 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1867 ; SSSE3-NEXT: movd (%rsi), %xmm0
1868 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1869 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1870 ; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1873 ; SSE41-LABEL: combine_test3c:
1875 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1876 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1877 ; SSE41-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1880 ; AVX-LABEL: combine_test3c:
1882 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1883 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1884 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1886 %A = load <4 x i8>* %a
1887 %B = load <4 x i8>* %b
1888 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1889 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1893 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
1894 ; SSE2-LABEL: combine_test4c:
1896 ; SSE2-NEXT: movd (%rdi), %xmm1
1897 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1898 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1899 ; SSE2-NEXT: movd (%rsi), %xmm2
1900 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1901 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1902 ; SSE2-NEXT: movdqa %xmm2, %xmm0
1903 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1904 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1905 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1906 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1909 ; SSSE3-LABEL: combine_test4c:
1911 ; SSSE3-NEXT: movd (%rdi), %xmm1
1912 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1913 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1914 ; SSSE3-NEXT: movd (%rsi), %xmm2
1915 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1916 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1917 ; SSSE3-NEXT: movdqa %xmm2, %xmm0
1918 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1919 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1920 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1921 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1924 ; SSE41-LABEL: combine_test4c:
1926 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1927 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1928 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1931 ; AVX1-LABEL: combine_test4c:
1933 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1934 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1935 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1938 ; AVX2-LABEL: combine_test4c:
1940 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1941 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1942 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1944 %A = load <4 x i8>* %a
1945 %B = load <4 x i8>* %b
1946 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1947 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1952 ; The following test cases are generated from this C++ code
1954 ;__m128 blend_01(__m128 a, __m128 b)
1957 ; s = _mm_blend_ps( s, b, 1<<0 );
1958 ; s = _mm_blend_ps( s, b, 1<<1 );
1962 ;__m128 blend_02(__m128 a, __m128 b)
1965 ; s = _mm_blend_ps( s, b, 1<<0 );
1966 ; s = _mm_blend_ps( s, b, 1<<2 );
1970 ;__m128 blend_123(__m128 a, __m128 b)
1973 ; s = _mm_blend_ps( s, b, 1<<1 );
1974 ; s = _mm_blend_ps( s, b, 1<<2 );
1975 ; s = _mm_blend_ps( s, b, 1<<3 );
1979 ; Ideally, we should collapse the following shuffles into a single one.
1981 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
1982 ; SSE2-LABEL: combine_blend_01:
1984 ; SSE2-NEXT: movsd %xmm1, %xmm0
1985 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1986 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
1987 ; SSE2-NEXT: movaps %xmm1, %xmm0
1990 ; SSSE3-LABEL: combine_blend_01:
1992 ; SSSE3-NEXT: movsd %xmm1, %xmm0
1993 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1994 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
1995 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1998 ; SSE41-LABEL: combine_blend_01:
2000 ; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm1[0],xmm0[1]
2001 ; SSE41-NEXT: movapd %xmm1, %xmm0
2004 ; AVX-LABEL: combine_blend_01:
2006 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2008 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
2009 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
2010 ret <4 x float> %shuffle6
2013 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
2014 ; SSE2-LABEL: combine_blend_02:
2016 ; SSE2-NEXT: movss %xmm1, %xmm0
2017 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
2018 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2021 ; SSSE3-LABEL: combine_blend_02:
2023 ; SSSE3-NEXT: movss %xmm1, %xmm0
2024 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
2025 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2028 ; SSE41-LABEL: combine_blend_02:
2030 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2031 ; SSE41-NEXT: movaps %xmm1, %xmm0
2034 ; AVX-LABEL: combine_blend_02:
2036 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2038 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
2039 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
2040 ret <4 x float> %shuffle6
2043 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
2044 ; SSE2-LABEL: combine_blend_123:
2046 ; SSE2-NEXT: movaps %xmm1, %xmm2
2047 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[0,0]
2048 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
2049 ; SSE2-NEXT: movsd %xmm2, %xmm1
2050 ; SSE2-NEXT: movaps %xmm1, %xmm0
2053 ; SSSE3-LABEL: combine_blend_123:
2055 ; SSSE3-NEXT: movaps %xmm1, %xmm2
2056 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[0,0]
2057 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
2058 ; SSSE3-NEXT: movsd %xmm2, %xmm1
2059 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2062 ; SSE41-LABEL: combine_blend_123:
2064 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
2065 ; SSE41-NEXT: movaps %xmm1, %xmm0
2068 ; AVX-LABEL: combine_blend_123:
2070 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2072 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
2073 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
2074 %shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2075 ret <4 x float> %shuffle12
2078 define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
2079 ; SSE-LABEL: combine_test_movhl_1:
2081 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2082 ; SSE-NEXT: movdqa %xmm1, %xmm0
2085 ; AVX-LABEL: combine_test_movhl_1:
2087 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2089 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
2090 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
2094 define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
2095 ; SSE-LABEL: combine_test_movhl_2:
2097 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2098 ; SSE-NEXT: movdqa %xmm1, %xmm0
2101 ; AVX-LABEL: combine_test_movhl_2:
2103 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2105 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
2106 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
2110 define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
2111 ; SSE-LABEL: combine_test_movhl_3:
2113 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2114 ; SSE-NEXT: movdqa %xmm1, %xmm0
2117 ; AVX-LABEL: combine_test_movhl_3:
2119 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2121 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
2122 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>
2127 ; Verify that we fold shuffles according to rule:
2128 ; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
2130 define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
2131 ; SSE2-LABEL: combine_undef_input_test1:
2133 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2134 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2135 ; SSE2-NEXT: movaps %xmm1, %xmm0
2138 ; SSSE3-LABEL: combine_undef_input_test1:
2140 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2141 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2142 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2145 ; SSE41-LABEL: combine_undef_input_test1:
2147 ; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm1[0],xmm0[1]
2148 ; SSE41-NEXT: movapd %xmm1, %xmm0
2151 ; AVX-LABEL: combine_undef_input_test1:
2153 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2155 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2156 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2160 define <4 x float> @combine_undef_input_test2(<4 x float> %a, <4 x float> %b) {
2161 ; SSE-LABEL: combine_undef_input_test2:
2163 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2166 ; AVX-LABEL: combine_undef_input_test2:
2168 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2170 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2171 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2175 define <4 x float> @combine_undef_input_test3(<4 x float> %a, <4 x float> %b) {
2176 ; SSE-LABEL: combine_undef_input_test3:
2178 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2181 ; AVX-LABEL: combine_undef_input_test3:
2183 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2185 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2186 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2190 define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
2191 ; SSE-LABEL: combine_undef_input_test4:
2193 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2194 ; SSE-NEXT: movapd %xmm1, %xmm0
2197 ; AVX-LABEL: combine_undef_input_test4:
2199 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2201 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2202 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2206 define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
2207 ; SSE2-LABEL: combine_undef_input_test5:
2209 ; SSE2-NEXT: movsd %xmm0, %xmm1
2210 ; SSE2-NEXT: movaps %xmm1, %xmm0
2213 ; SSSE3-LABEL: combine_undef_input_test5:
2215 ; SSSE3-NEXT: movsd %xmm0, %xmm1
2216 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2219 ; SSE41-LABEL: combine_undef_input_test5:
2221 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2224 ; AVX-LABEL: combine_undef_input_test5:
2226 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2228 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2229 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2234 ; Verify that we fold shuffles according to rule:
2235 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2237 define <4 x float> @combine_undef_input_test6(<4 x float> %a) {
2238 ; ALL-LABEL: combine_undef_input_test6:
2241 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2242 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2246 define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
2247 ; SSE2-LABEL: combine_undef_input_test7:
2249 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2252 ; SSSE3-LABEL: combine_undef_input_test7:
2254 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2257 ; SSE41-LABEL: combine_undef_input_test7:
2259 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2262 ; AVX-LABEL: combine_undef_input_test7:
2264 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2266 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2267 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2271 define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
2272 ; SSE2-LABEL: combine_undef_input_test8:
2274 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2277 ; SSSE3-LABEL: combine_undef_input_test8:
2279 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2282 ; SSE41-LABEL: combine_undef_input_test8:
2284 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2287 ; AVX-LABEL: combine_undef_input_test8:
2289 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2291 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2292 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2296 define <4 x float> @combine_undef_input_test9(<4 x float> %a) {
2297 ; SSE-LABEL: combine_undef_input_test9:
2299 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2302 ; AVX-LABEL: combine_undef_input_test9:
2304 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2306 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2307 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2311 define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
2312 ; ALL-LABEL: combine_undef_input_test10:
2315 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2316 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2320 define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
2321 ; SSE2-LABEL: combine_undef_input_test11:
2323 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2324 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2325 ; SSE2-NEXT: movaps %xmm1, %xmm0
2328 ; SSSE3-LABEL: combine_undef_input_test11:
2330 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2331 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2332 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2335 ; SSE41-LABEL: combine_undef_input_test11:
2337 ; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm1[0],xmm0[1]
2338 ; SSE41-NEXT: movapd %xmm1, %xmm0
2341 ; AVX-LABEL: combine_undef_input_test11:
2343 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2345 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2346 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 6>
2350 define <4 x float> @combine_undef_input_test12(<4 x float> %a, <4 x float> %b) {
2351 ; SSE-LABEL: combine_undef_input_test12:
2353 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2356 ; AVX-LABEL: combine_undef_input_test12:
2358 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2360 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2361 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2365 define <4 x float> @combine_undef_input_test13(<4 x float> %a, <4 x float> %b) {
2366 ; SSE-LABEL: combine_undef_input_test13:
2368 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2371 ; AVX-LABEL: combine_undef_input_test13:
2373 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2375 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2376 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 5, i32 0, i32 5>
2380 define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
2381 ; SSE-LABEL: combine_undef_input_test14:
2383 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2384 ; SSE-NEXT: movapd %xmm1, %xmm0
2387 ; AVX-LABEL: combine_undef_input_test14:
2389 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2391 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2392 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2396 define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
2397 ; SSE2-LABEL: combine_undef_input_test15:
2399 ; SSE2-NEXT: movsd %xmm0, %xmm1
2400 ; SSE2-NEXT: movaps %xmm1, %xmm0
2403 ; SSSE3-LABEL: combine_undef_input_test15:
2405 ; SSSE3-NEXT: movsd %xmm0, %xmm1
2406 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2409 ; SSE41-LABEL: combine_undef_input_test15:
2411 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2414 ; AVX-LABEL: combine_undef_input_test15:
2416 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2418 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2419 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2424 ; Verify that shuffles are canonicalized according to rules:
2425 ; shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
2427 ; This allows to trigger the following combine rule:
2428 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2430 ; As a result, all the shuffle pairs in each function below should be
2431 ; combined into a single legal shuffle operation.
2433 define <4 x float> @combine_undef_input_test16(<4 x float> %a) {
2434 ; ALL-LABEL: combine_undef_input_test16:
2437 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2438 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
2442 define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
2443 ; SSE2-LABEL: combine_undef_input_test17:
2445 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2448 ; SSSE3-LABEL: combine_undef_input_test17:
2450 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2453 ; SSE41-LABEL: combine_undef_input_test17:
2455 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2458 ; AVX-LABEL: combine_undef_input_test17:
2460 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2462 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2463 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2467 define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
2468 ; SSE2-LABEL: combine_undef_input_test18:
2470 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2473 ; SSSE3-LABEL: combine_undef_input_test18:
2475 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2478 ; SSE41-LABEL: combine_undef_input_test18:
2480 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2483 ; AVX-LABEL: combine_undef_input_test18:
2485 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2487 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2488 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
2492 define <4 x float> @combine_undef_input_test19(<4 x float> %a) {
2493 ; SSE-LABEL: combine_undef_input_test19:
2495 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2498 ; AVX-LABEL: combine_undef_input_test19:
2500 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2502 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2503 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2507 define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
2508 ; ALL-LABEL: combine_undef_input_test20:
2511 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2512 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>