1 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7 ; Verify that the DAG combiner correctly folds bitwise operations across
8 ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
9 ; basic and always-safe patterns. Also test that the DAG combiner will combine
10 ; target-specific shuffle instructions where reasonable.
12 target triple = "x86_64-unknown-unknown"
14 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
15 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
16 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
18 define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
19 ; ALL-LABEL: combine_pshufd1:
20 ; ALL: # BB#0: # %entry
23 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
24 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
28 define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
29 ; ALL-LABEL: combine_pshufd2:
30 ; ALL: # BB#0: # %entry
33 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
34 %b.cast = bitcast <4 x i32> %b to <8 x i16>
35 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
36 %c.cast = bitcast <8 x i16> %c to <4 x i32>
37 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
41 define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
42 ; ALL-LABEL: combine_pshufd3:
43 ; ALL: # BB#0: # %entry
46 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
47 %b.cast = bitcast <4 x i32> %b to <8 x i16>
48 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
49 %c.cast = bitcast <8 x i16> %c to <4 x i32>
50 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
54 define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
55 ; SSE-LABEL: combine_pshufd4:
56 ; SSE: # BB#0: # %entry
57 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
60 ; AVX-LABEL: combine_pshufd4:
61 ; AVX: # BB#0: # %entry
62 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
65 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
66 %b.cast = bitcast <4 x i32> %b to <8 x i16>
67 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
68 %c.cast = bitcast <8 x i16> %c to <4 x i32>
69 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
73 define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
74 ; SSE-LABEL: combine_pshufd5:
75 ; SSE: # BB#0: # %entry
76 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
79 ; AVX-LABEL: combine_pshufd5:
80 ; AVX: # BB#0: # %entry
81 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
84 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
85 %b.cast = bitcast <4 x i32> %b to <8 x i16>
86 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
87 %c.cast = bitcast <8 x i16> %c to <4 x i32>
88 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
92 define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
93 ; SSE-LABEL: combine_pshufd6:
94 ; SSE: # BB#0: # %entry
95 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
98 ; AVX-LABEL: combine_pshufd6:
99 ; AVX: # BB#0: # %entry
100 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
103 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
104 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
108 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
109 ; ALL-LABEL: combine_pshuflw1:
110 ; ALL: # BB#0: # %entry
113 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
114 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
118 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
119 ; ALL-LABEL: combine_pshuflw2:
120 ; ALL: # BB#0: # %entry
123 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
124 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
125 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
129 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
130 ; SSE-LABEL: combine_pshuflw3:
131 ; SSE: # BB#0: # %entry
132 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
135 ; AVX-LABEL: combine_pshuflw3:
136 ; AVX: # BB#0: # %entry
137 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
140 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
141 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
142 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
146 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
147 ; SSE-LABEL: combine_pshufhw1:
148 ; SSE: # BB#0: # %entry
149 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
152 ; AVX-LABEL: combine_pshufhw1:
153 ; AVX: # BB#0: # %entry
154 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
157 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
158 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
159 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
163 define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164 ; SSE-LABEL: combine_bitwise_ops_test1:
166 ; SSE-NEXT: pand %xmm1, %xmm0
167 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
170 ; AVX-LABEL: combine_bitwise_ops_test1:
172 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
173 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
175 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
176 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177 %and = and <4 x i32> %shuf1, %shuf2
181 define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
182 ; SSE-LABEL: combine_bitwise_ops_test2:
184 ; SSE-NEXT: por %xmm1, %xmm0
185 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
188 ; AVX-LABEL: combine_bitwise_ops_test2:
190 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
191 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
193 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
194 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195 %or = or <4 x i32> %shuf1, %shuf2
199 define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
200 ; SSE-LABEL: combine_bitwise_ops_test3:
202 ; SSE-NEXT: pxor %xmm1, %xmm0
203 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
206 ; AVX-LABEL: combine_bitwise_ops_test3:
208 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
209 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
211 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
212 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213 %xor = xor <4 x i32> %shuf1, %shuf2
217 define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218 ; SSE-LABEL: combine_bitwise_ops_test4:
220 ; SSE-NEXT: pand %xmm1, %xmm0
221 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
224 ; AVX-LABEL: combine_bitwise_ops_test4:
226 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
227 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
229 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
230 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231 %and = and <4 x i32> %shuf1, %shuf2
235 define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
236 ; SSE-LABEL: combine_bitwise_ops_test5:
238 ; SSE-NEXT: por %xmm1, %xmm0
239 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
242 ; AVX-LABEL: combine_bitwise_ops_test5:
244 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
245 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
247 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
248 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249 %or = or <4 x i32> %shuf1, %shuf2
253 define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
254 ; SSE-LABEL: combine_bitwise_ops_test6:
256 ; SSE-NEXT: pxor %xmm1, %xmm0
257 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
260 ; AVX-LABEL: combine_bitwise_ops_test6:
262 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
263 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
265 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
266 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267 %xor = xor <4 x i32> %shuf1, %shuf2
272 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
273 ; are not performing a swizzle operations.
275 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
276 ; SSE2-LABEL: combine_bitwise_ops_test1b:
278 ; SSE2-NEXT: andps %xmm1, %xmm0
279 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
280 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
283 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
285 ; SSSE3-NEXT: andps %xmm1, %xmm0
286 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
287 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
290 ; SSE41-LABEL: combine_bitwise_ops_test1b:
292 ; SSE41-NEXT: pand %xmm1, %xmm0
293 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
296 ; AVX1-LABEL: combine_bitwise_ops_test1b:
298 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
299 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
302 ; AVX2-LABEL: combine_bitwise_ops_test1b:
304 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
305 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
307 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
308 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
309 %and = and <4 x i32> %shuf1, %shuf2
313 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
314 ; SSE2-LABEL: combine_bitwise_ops_test2b:
316 ; SSE2-NEXT: orps %xmm1, %xmm0
317 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
318 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
321 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
323 ; SSSE3-NEXT: orps %xmm1, %xmm0
324 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
325 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
328 ; SSE41-LABEL: combine_bitwise_ops_test2b:
330 ; SSE41-NEXT: por %xmm1, %xmm0
331 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
334 ; AVX1-LABEL: combine_bitwise_ops_test2b:
336 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
337 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
340 ; AVX2-LABEL: combine_bitwise_ops_test2b:
342 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
343 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
345 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
346 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
347 %or = or <4 x i32> %shuf1, %shuf2
351 define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
352 ; SSE2-LABEL: combine_bitwise_ops_test3b:
354 ; SSE2-NEXT: xorps %xmm1, %xmm0
355 ; SSE2-NEXT: xorps %xmm1, %xmm1
356 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
357 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
360 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
362 ; SSSE3-NEXT: xorps %xmm1, %xmm0
363 ; SSSE3-NEXT: xorps %xmm1, %xmm1
364 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
365 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
368 ; SSE41-LABEL: combine_bitwise_ops_test3b:
370 ; SSE41-NEXT: pxor %xmm1, %xmm0
371 ; SSE41-NEXT: pxor %xmm1, %xmm1
372 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
375 ; AVX1-LABEL: combine_bitwise_ops_test3b:
377 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
378 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
379 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
382 ; AVX2-LABEL: combine_bitwise_ops_test3b:
384 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
385 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
386 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
388 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
389 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
390 %xor = xor <4 x i32> %shuf1, %shuf2
394 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
395 ; SSE2-LABEL: combine_bitwise_ops_test4b:
397 ; SSE2-NEXT: andps %xmm1, %xmm0
398 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
399 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
400 ; SSE2-NEXT: movaps %xmm2, %xmm0
403 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
405 ; SSSE3-NEXT: andps %xmm1, %xmm0
406 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
407 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
408 ; SSSE3-NEXT: movaps %xmm2, %xmm0
411 ; SSE41-LABEL: combine_bitwise_ops_test4b:
413 ; SSE41-NEXT: pand %xmm1, %xmm0
414 ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
415 ; SSE41-NEXT: movdqa %xmm2, %xmm0
418 ; AVX1-LABEL: combine_bitwise_ops_test4b:
420 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
421 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
424 ; AVX2-LABEL: combine_bitwise_ops_test4b:
426 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
427 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
429 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
430 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
431 %and = and <4 x i32> %shuf1, %shuf2
435 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
436 ; SSE2-LABEL: combine_bitwise_ops_test5b:
438 ; SSE2-NEXT: orps %xmm1, %xmm0
439 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
440 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
441 ; SSE2-NEXT: movaps %xmm2, %xmm0
444 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
446 ; SSSE3-NEXT: orps %xmm1, %xmm0
447 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
448 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
449 ; SSSE3-NEXT: movaps %xmm2, %xmm0
452 ; SSE41-LABEL: combine_bitwise_ops_test5b:
454 ; SSE41-NEXT: por %xmm1, %xmm0
455 ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
456 ; SSE41-NEXT: movdqa %xmm2, %xmm0
459 ; AVX1-LABEL: combine_bitwise_ops_test5b:
461 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
462 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
465 ; AVX2-LABEL: combine_bitwise_ops_test5b:
467 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
468 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
470 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
471 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
472 %or = or <4 x i32> %shuf1, %shuf2
476 define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
477 ; SSE2-LABEL: combine_bitwise_ops_test6b:
479 ; SSE2-NEXT: xorps %xmm1, %xmm0
480 ; SSE2-NEXT: xorps %xmm1, %xmm1
481 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
482 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
483 ; SSE2-NEXT: movaps %xmm1, %xmm0
486 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
488 ; SSSE3-NEXT: xorps %xmm1, %xmm0
489 ; SSSE3-NEXT: xorps %xmm1, %xmm1
490 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
491 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
492 ; SSSE3-NEXT: movaps %xmm1, %xmm0
495 ; SSE41-LABEL: combine_bitwise_ops_test6b:
497 ; SSE41-NEXT: pxor %xmm1, %xmm0
498 ; SSE41-NEXT: pxor %xmm1, %xmm1
499 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
500 ; SSE41-NEXT: movdqa %xmm1, %xmm0
503 ; AVX1-LABEL: combine_bitwise_ops_test6b:
505 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
506 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
507 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
510 ; AVX2-LABEL: combine_bitwise_ops_test6b:
512 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
513 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
514 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
516 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
517 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
518 %xor = xor <4 x i32> %shuf1, %shuf2
522 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
523 ; SSE-LABEL: combine_bitwise_ops_test1c:
525 ; SSE-NEXT: andps %xmm1, %xmm0
526 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
529 ; AVX-LABEL: combine_bitwise_ops_test1c:
531 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
532 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
534 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
535 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
536 %and = and <4 x i32> %shuf1, %shuf2
540 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
541 ; SSE-LABEL: combine_bitwise_ops_test2c:
543 ; SSE-NEXT: orps %xmm1, %xmm0
544 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
547 ; AVX-LABEL: combine_bitwise_ops_test2c:
549 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
550 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
552 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
553 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
554 %or = or <4 x i32> %shuf1, %shuf2
558 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
559 ; SSE-LABEL: combine_bitwise_ops_test3c:
561 ; SSE-NEXT: xorps %xmm1, %xmm0
562 ; SSE-NEXT: xorps %xmm1, %xmm1
563 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
566 ; AVX-LABEL: combine_bitwise_ops_test3c:
568 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
569 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
570 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
572 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
573 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
574 %xor = xor <4 x i32> %shuf1, %shuf2
578 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
579 ; SSE-LABEL: combine_bitwise_ops_test4c:
581 ; SSE-NEXT: andps %xmm1, %xmm0
582 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
583 ; SSE-NEXT: movaps %xmm2, %xmm0
586 ; AVX-LABEL: combine_bitwise_ops_test4c:
588 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
589 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
591 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
592 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
593 %and = and <4 x i32> %shuf1, %shuf2
597 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
598 ; SSE-LABEL: combine_bitwise_ops_test5c:
600 ; SSE-NEXT: orps %xmm1, %xmm0
601 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
602 ; SSE-NEXT: movaps %xmm2, %xmm0
605 ; AVX-LABEL: combine_bitwise_ops_test5c:
607 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
608 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
610 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
611 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
612 %or = or <4 x i32> %shuf1, %shuf2
616 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
617 ; SSE-LABEL: combine_bitwise_ops_test6c:
619 ; SSE-NEXT: xorps %xmm1, %xmm0
620 ; SSE-NEXT: xorps %xmm1, %xmm1
621 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
622 ; SSE-NEXT: movaps %xmm1, %xmm0
625 ; AVX-LABEL: combine_bitwise_ops_test6c:
627 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
628 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
629 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[1,3]
631 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
632 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
633 %xor = xor <4 x i32> %shuf1, %shuf2
637 define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
638 ; SSE-LABEL: combine_nested_undef_test1:
640 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
643 ; AVX-LABEL: combine_nested_undef_test1:
645 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
647 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
648 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
652 define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
653 ; SSE-LABEL: combine_nested_undef_test2:
655 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
658 ; AVX-LABEL: combine_nested_undef_test2:
660 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
662 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
663 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
667 define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
668 ; SSE-LABEL: combine_nested_undef_test3:
670 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
673 ; AVX-LABEL: combine_nested_undef_test3:
675 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
677 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
678 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
682 define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
683 ; SSE-LABEL: combine_nested_undef_test4:
685 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
688 ; AVX1-LABEL: combine_nested_undef_test4:
690 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
693 ; AVX2-LABEL: combine_nested_undef_test4:
695 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
697 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
698 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
702 define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
703 ; SSE-LABEL: combine_nested_undef_test5:
705 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
708 ; AVX-LABEL: combine_nested_undef_test5:
710 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
712 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
713 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
717 define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
718 ; SSE-LABEL: combine_nested_undef_test6:
720 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
723 ; AVX-LABEL: combine_nested_undef_test6:
725 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
727 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
728 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
732 define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
733 ; SSE-LABEL: combine_nested_undef_test7:
735 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
738 ; AVX-LABEL: combine_nested_undef_test7:
740 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
742 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
743 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
747 define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
748 ; SSE-LABEL: combine_nested_undef_test8:
750 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
753 ; AVX-LABEL: combine_nested_undef_test8:
755 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
757 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
758 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
762 define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
763 ; SSE-LABEL: combine_nested_undef_test9:
765 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
768 ; AVX-LABEL: combine_nested_undef_test9:
770 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
772 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
773 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
777 define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
778 ; SSE-LABEL: combine_nested_undef_test10:
780 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
783 ; AVX-LABEL: combine_nested_undef_test10:
785 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
787 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
788 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
792 define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
793 ; SSE-LABEL: combine_nested_undef_test11:
795 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
798 ; AVX-LABEL: combine_nested_undef_test11:
800 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
802 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
803 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
807 define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
808 ; SSE-LABEL: combine_nested_undef_test12:
810 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
813 ; AVX1-LABEL: combine_nested_undef_test12:
815 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
818 ; AVX2-LABEL: combine_nested_undef_test12:
820 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
822 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
823 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
827 ; The following pair of shuffles is folded into vector %A.
828 define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
829 ; ALL-LABEL: combine_nested_undef_test13:
832 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
833 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
837 ; The following pair of shuffles is folded into vector %B.
838 define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
839 ; SSE-LABEL: combine_nested_undef_test14:
841 ; SSE-NEXT: movaps %xmm1, %xmm0
844 ; AVX-LABEL: combine_nested_undef_test14:
846 ; AVX-NEXT: vmovaps %xmm1, %xmm0
848 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
849 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
854 ; Verify that we don't optimize the following cases. We expect more than one shuffle.
856 ; FIXME: Many of these already don't make sense, and the rest should stop
857 ; making sense with th enew vector shuffle lowering. Revisit at least testing for
860 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
861 ; SSE-LABEL: combine_nested_undef_test15:
863 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
864 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,1]
865 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
868 ; AVX-LABEL: combine_nested_undef_test15:
870 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
871 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[3,1]
872 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
874 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
875 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
879 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
880 ; SSE2-LABEL: combine_nested_undef_test16:
882 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
883 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
884 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
887 ; SSSE3-LABEL: combine_nested_undef_test16:
889 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
890 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
891 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
894 ; SSE41-LABEL: combine_nested_undef_test16:
896 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
897 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
900 ; AVX1-LABEL: combine_nested_undef_test16:
902 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
903 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
906 ; AVX2-LABEL: combine_nested_undef_test16:
908 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
909 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
911 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
912 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
916 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
917 ; SSE-LABEL: combine_nested_undef_test17:
919 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
920 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
921 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
924 ; AVX-LABEL: combine_nested_undef_test17:
926 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
927 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
928 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
930 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
931 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
935 define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
936 ; SSE-LABEL: combine_nested_undef_test18:
938 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
941 ; AVX-LABEL: combine_nested_undef_test18:
943 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
945 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
946 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
950 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
951 ; SSE-LABEL: combine_nested_undef_test19:
953 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
954 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
955 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
958 ; AVX-LABEL: combine_nested_undef_test19:
960 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
961 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
962 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
964 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
965 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
969 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
970 ; SSE-LABEL: combine_nested_undef_test20:
972 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
973 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
976 ; AVX-LABEL: combine_nested_undef_test20:
978 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
979 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
981 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
982 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
986 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
987 ; SSE-LABEL: combine_nested_undef_test21:
989 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
990 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
991 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
994 ; AVX-LABEL: combine_nested_undef_test21:
996 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
997 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
998 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
1000 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
1001 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1006 ; Test that we correctly combine shuffles according to rule
1007 ; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
1009 define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
1010 ; SSE-LABEL: combine_nested_undef_test22:
1012 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1015 ; AVX-LABEL: combine_nested_undef_test22:
1017 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1019 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1020 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
1024 define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1025 ; SSE-LABEL: combine_nested_undef_test23:
1027 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1030 ; AVX-LABEL: combine_nested_undef_test23:
1032 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1034 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1035 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1039 define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1040 ; SSE-LABEL: combine_nested_undef_test24:
1042 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1045 ; AVX-LABEL: combine_nested_undef_test24:
1047 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1049 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1050 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1054 define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1055 ; SSE-LABEL: combine_nested_undef_test25:
1057 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1060 ; AVX1-LABEL: combine_nested_undef_test25:
1062 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1065 ; AVX2-LABEL: combine_nested_undef_test25:
1067 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1069 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1070 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1074 define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1075 ; SSE-LABEL: combine_nested_undef_test26:
1077 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1080 ; AVX-LABEL: combine_nested_undef_test26:
1082 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1084 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1085 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1089 define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1090 ; SSE-LABEL: combine_nested_undef_test27:
1092 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1095 ; AVX1-LABEL: combine_nested_undef_test27:
1097 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1100 ; AVX2-LABEL: combine_nested_undef_test27:
1102 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1104 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1105 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1109 define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1110 ; SSE-LABEL: combine_nested_undef_test28:
1112 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1115 ; AVX-LABEL: combine_nested_undef_test28:
1117 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1119 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1120 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1124 define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1125 ; SSE2-LABEL: combine_test1:
1127 ; SSE2-NEXT: movaps %xmm1, %xmm2
1128 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1129 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1130 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,3]
1131 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1132 ; SSE2-NEXT: movaps %xmm2, %xmm0
1135 ; SSSE3-LABEL: combine_test1:
1137 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1140 ; SSE41-LABEL: combine_test1:
1142 ; SSE41-NEXT: movaps %xmm1, %xmm0
1145 ; AVX-LABEL: combine_test1:
1147 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1149 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1150 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1154 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1155 ; SSE2-LABEL: combine_test2:
1157 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1158 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1159 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1160 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1163 ; SSSE3-LABEL: combine_test2:
1165 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1166 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1167 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1168 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1171 ; SSE41-LABEL: combine_test2:
1173 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1174 ; SSE41-NEXT: movaps %xmm1, %xmm0
1177 ; AVX-LABEL: combine_test2:
1179 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1181 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1182 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1186 define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1187 ; SSE-LABEL: combine_test3:
1189 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1192 ; AVX-LABEL: combine_test3:
1194 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1196 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1197 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1201 define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1202 ; SSE-LABEL: combine_test4:
1204 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1205 ; SSE-NEXT: movapd %xmm1, %xmm0
1208 ; AVX-LABEL: combine_test4:
1210 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1212 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1213 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1217 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1218 ; SSE2-LABEL: combine_test5:
1220 ; SSE2-NEXT: movaps %xmm1, %xmm2
1221 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1222 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1223 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1224 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1225 ; SSE2-NEXT: movaps %xmm2, %xmm0
1228 ; SSSE3-LABEL: combine_test5:
1230 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1231 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1232 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1233 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1234 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1235 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1238 ; SSE41-LABEL: combine_test5:
1240 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1],xmm1[2,3]
1241 ; SSE41-NEXT: movaps %xmm1, %xmm0
1244 ; AVX-LABEL: combine_test5:
1246 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1248 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1249 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1253 define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1254 ; SSE2-LABEL: combine_test6:
1256 ; SSE2-NEXT: movaps %xmm1, %xmm2
1257 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1258 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1259 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,3]
1260 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1261 ; SSE2-NEXT: movaps %xmm2, %xmm0
1264 ; SSSE3-LABEL: combine_test6:
1266 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1269 ; SSE41-LABEL: combine_test6:
1271 ; SSE41-NEXT: movaps %xmm1, %xmm0
1274 ; AVX-LABEL: combine_test6:
1276 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1278 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1279 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1283 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1284 ; SSE2-LABEL: combine_test7:
1286 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1287 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1288 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1289 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1292 ; SSSE3-LABEL: combine_test7:
1294 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1295 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1296 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1297 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1300 ; SSE41-LABEL: combine_test7:
1302 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1303 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1306 ; AVX1-LABEL: combine_test7:
1308 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1311 ; AVX2-LABEL: combine_test7:
1313 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1315 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1316 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1320 define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1321 ; SSE-LABEL: combine_test8:
1323 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1326 ; AVX-LABEL: combine_test8:
1328 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1330 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1331 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1335 define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1336 ; SSE-LABEL: combine_test9:
1338 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1339 ; SSE-NEXT: movdqa %xmm1, %xmm0
1342 ; AVX-LABEL: combine_test9:
1344 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1346 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1347 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1351 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1352 ; SSE2-LABEL: combine_test10:
1354 ; SSE2-NEXT: movaps %xmm1, %xmm2
1355 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1356 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1357 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1358 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1359 ; SSE2-NEXT: movaps %xmm2, %xmm0
1362 ; SSSE3-LABEL: combine_test10:
1364 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1365 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1366 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1367 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1368 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1369 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1372 ; SSE41-LABEL: combine_test10:
1374 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1375 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1378 ; AVX1-LABEL: combine_test10:
1380 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1383 ; AVX2-LABEL: combine_test10:
1385 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1387 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1388 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1392 define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1393 ; ALL-LABEL: combine_test11:
1396 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1397 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1401 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1402 ; SSE2-LABEL: combine_test12:
1404 ; SSE2-NEXT: movss %xmm0, %xmm1
1405 ; SSE2-NEXT: movss %xmm0, %xmm1
1406 ; SSE2-NEXT: movaps %xmm1, %xmm0
1409 ; SSSE3-LABEL: combine_test12:
1411 ; SSSE3-NEXT: movss %xmm0, %xmm1
1412 ; SSSE3-NEXT: movss %xmm0, %xmm1
1413 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1416 ; SSE41-LABEL: combine_test12:
1418 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1419 ; SSE41-NEXT: movaps %xmm1, %xmm0
1422 ; AVX-LABEL: combine_test12:
1424 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1426 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1427 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1431 define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1432 ; SSE-LABEL: combine_test13:
1434 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1437 ; AVX-LABEL: combine_test13:
1439 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1441 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1442 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1446 define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1447 ; SSE-LABEL: combine_test14:
1449 ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1452 ; AVX-LABEL: combine_test14:
1454 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1456 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1457 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1461 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1462 ; SSE2-LABEL: combine_test15:
1464 ; SSE2-NEXT: movaps %xmm0, %xmm2
1465 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1466 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1467 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1468 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1471 ; SSSE3-LABEL: combine_test15:
1473 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1474 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1475 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1476 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1477 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1480 ; SSE41-LABEL: combine_test15:
1482 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1],xmm1[2,3]
1483 ; SSE41-NEXT: movaps %xmm1, %xmm0
1486 ; AVX-LABEL: combine_test15:
1488 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1490 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1491 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1495 define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1496 ; ALL-LABEL: combine_test16:
1499 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1500 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1504 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1505 ; SSE2-LABEL: combine_test17:
1507 ; SSE2-NEXT: movss %xmm0, %xmm1
1508 ; SSE2-NEXT: movss %xmm0, %xmm1
1509 ; SSE2-NEXT: movaps %xmm1, %xmm0
1512 ; SSSE3-LABEL: combine_test17:
1514 ; SSSE3-NEXT: movss %xmm0, %xmm1
1515 ; SSSE3-NEXT: movss %xmm0, %xmm1
1516 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1519 ; SSE41-LABEL: combine_test17:
1521 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1522 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1525 ; AVX1-LABEL: combine_test17:
1527 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1530 ; AVX2-LABEL: combine_test17:
1532 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1534 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1535 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1539 define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1540 ; SSE-LABEL: combine_test18:
1542 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1545 ; AVX-LABEL: combine_test18:
1547 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1549 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1550 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1554 define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1555 ; SSE-LABEL: combine_test19:
1557 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1560 ; AVX-LABEL: combine_test19:
1562 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1564 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1565 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1569 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1570 ; SSE2-LABEL: combine_test20:
1572 ; SSE2-NEXT: movaps %xmm0, %xmm2
1573 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1574 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1575 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1576 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1579 ; SSSE3-LABEL: combine_test20:
1581 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1582 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1583 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1584 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1585 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1588 ; SSE41-LABEL: combine_test20:
1590 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1591 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1594 ; AVX1-LABEL: combine_test20:
1596 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1599 ; AVX2-LABEL: combine_test20:
1601 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1603 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1604 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1609 ; Check some negative cases.
1610 ; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1612 define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1613 ; SSE2-LABEL: combine_test1b:
1615 ; SSE2-NEXT: movaps %xmm1, %xmm2
1616 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1617 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1618 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]
1619 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
1620 ; SSE2-NEXT: movaps %xmm1, %xmm0
1623 ; SSSE3-LABEL: combine_test1b:
1625 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1626 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1627 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1628 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]
1629 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
1630 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1633 ; SSE41-LABEL: combine_test1b:
1635 ; SSE41-NEXT: movaps %xmm1, %xmm2
1636 ; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
1637 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]
1638 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
1639 ; SSE41-NEXT: movaps %xmm1, %xmm0
1642 ; AVX-LABEL: combine_test1b:
1644 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1645 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1646 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[2,0]
1648 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1649 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1653 define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1654 ; SSE2-LABEL: combine_test2b:
1656 ; SSE2-NEXT: movaps %xmm1, %xmm2
1657 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1658 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1659 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]
1660 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1661 ; SSE2-NEXT: movaps %xmm2, %xmm0
1664 ; SSSE3-LABEL: combine_test2b:
1666 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1667 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1668 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1669 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]
1670 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1671 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1674 ; SSE41-LABEL: combine_test2b:
1676 ; SSE41-NEXT: movaps %xmm1, %xmm2
1677 ; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
1678 ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]
1679 ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1680 ; SSE41-NEXT: movaps %xmm2, %xmm0
1683 ; AVX-LABEL: combine_test2b:
1685 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1686 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]
1687 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1689 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1690 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
1694 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1695 ; SSE-LABEL: combine_test3b:
1697 ; SSE-NEXT: movaps %xmm1, %xmm2
1698 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[3,0]
1699 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1700 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1701 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1704 ; AVX-LABEL: combine_test3b:
1706 ; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,0],xmm0[3,0]
1707 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1708 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1709 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1711 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1712 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1716 define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1717 ; SSE2-LABEL: combine_test4b:
1719 ; SSE2-NEXT: movaps %xmm1, %xmm2
1720 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1721 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1722 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
1723 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]
1724 ; SSE2-NEXT: movaps %xmm1, %xmm0
1727 ; SSSE3-LABEL: combine_test4b:
1729 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1730 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1731 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1732 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
1733 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]
1734 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1737 ; SSE41-LABEL: combine_test4b:
1739 ; SSE41-NEXT: movaps %xmm1, %xmm2
1740 ; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
1741 ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
1742 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]
1743 ; SSE41-NEXT: movaps %xmm1, %xmm0
1746 ; AVX-LABEL: combine_test4b:
1748 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1749 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
1750 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[1,1],xmm0[0,2]
1752 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1753 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1758 ; Verify that we correctly fold shuffles even when we use illegal vector types.
1760 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1761 ; SSE2-LABEL: combine_test1c:
1763 ; SSE2-NEXT: movd (%rdi), %xmm0
1764 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1765 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1766 ; SSE2-NEXT: movd (%rsi), %xmm1
1767 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1768 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1769 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1770 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1771 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1772 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1775 ; SSSE3-LABEL: combine_test1c:
1777 ; SSSE3-NEXT: movd (%rdi), %xmm0
1778 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1779 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1780 ; SSSE3-NEXT: movd (%rsi), %xmm1
1781 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1782 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1783 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1784 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1785 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1786 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1789 ; SSE41-LABEL: combine_test1c:
1791 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1792 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1793 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1796 ; AVX1-LABEL: combine_test1c:
1798 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1799 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1800 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1803 ; AVX2-LABEL: combine_test1c:
1805 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1806 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1807 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1809 %A = load <4 x i8>* %a
1810 %B = load <4 x i8>* %b
1811 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1812 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1816 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1817 ; SSE2-LABEL: combine_test2c:
1819 ; SSE2-NEXT: movd (%rdi), %xmm0
1820 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1821 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1822 ; SSE2-NEXT: movd (%rsi), %xmm1
1823 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1824 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1825 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1828 ; SSSE3-LABEL: combine_test2c:
1830 ; SSSE3-NEXT: movd (%rdi), %xmm0
1831 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1832 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1833 ; SSSE3-NEXT: movd (%rsi), %xmm1
1834 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1835 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1836 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1839 ; SSE41-LABEL: combine_test2c:
1841 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm0
1842 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm1
1843 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1846 ; AVX-LABEL: combine_test2c:
1848 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1849 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1850 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1852 %A = load <4 x i8>* %a
1853 %B = load <4 x i8>* %b
1854 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1855 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1859 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1860 ; SSE2-LABEL: combine_test3c:
1862 ; SSE2-NEXT: movd (%rdi), %xmm1
1863 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1864 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1865 ; SSE2-NEXT: movd (%rsi), %xmm0
1866 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1867 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1868 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1871 ; SSSE3-LABEL: combine_test3c:
1873 ; SSSE3-NEXT: movd (%rdi), %xmm1
1874 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1875 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1876 ; SSSE3-NEXT: movd (%rsi), %xmm0
1877 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1878 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1879 ; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1882 ; SSE41-LABEL: combine_test3c:
1884 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1885 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1886 ; SSE41-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1889 ; AVX-LABEL: combine_test3c:
1891 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1892 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1893 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1895 %A = load <4 x i8>* %a
1896 %B = load <4 x i8>* %b
1897 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1898 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1902 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
1903 ; SSE2-LABEL: combine_test4c:
1905 ; SSE2-NEXT: movd (%rdi), %xmm1
1906 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1907 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1908 ; SSE2-NEXT: movd (%rsi), %xmm2
1909 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1910 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1911 ; SSE2-NEXT: movdqa %xmm2, %xmm0
1912 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1913 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1914 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1915 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1918 ; SSSE3-LABEL: combine_test4c:
1920 ; SSSE3-NEXT: movd (%rdi), %xmm1
1921 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1922 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1923 ; SSSE3-NEXT: movd (%rsi), %xmm2
1924 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1925 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1926 ; SSSE3-NEXT: movdqa %xmm2, %xmm0
1927 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1928 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1929 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1930 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1933 ; SSE41-LABEL: combine_test4c:
1935 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1936 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1937 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1940 ; AVX1-LABEL: combine_test4c:
1942 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1943 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1944 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1947 ; AVX2-LABEL: combine_test4c:
1949 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1950 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1951 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1953 %A = load <4 x i8>* %a
1954 %B = load <4 x i8>* %b
1955 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1956 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1961 ; The following test cases are generated from this C++ code
1963 ;__m128 blend_01(__m128 a, __m128 b)
1966 ; s = _mm_blend_ps( s, b, 1<<0 );
1967 ; s = _mm_blend_ps( s, b, 1<<1 );
1971 ;__m128 blend_02(__m128 a, __m128 b)
1974 ; s = _mm_blend_ps( s, b, 1<<0 );
1975 ; s = _mm_blend_ps( s, b, 1<<2 );
1979 ;__m128 blend_123(__m128 a, __m128 b)
1982 ; s = _mm_blend_ps( s, b, 1<<1 );
1983 ; s = _mm_blend_ps( s, b, 1<<2 );
1984 ; s = _mm_blend_ps( s, b, 1<<3 );
1988 ; Ideally, we should collapse the following shuffles into a single one.
1990 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
1991 ; SSE2-LABEL: combine_blend_01:
1993 ; SSE2-NEXT: movsd %xmm1, %xmm0
1994 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1995 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
1996 ; SSE2-NEXT: movaps %xmm1, %xmm0
1999 ; SSSE3-LABEL: combine_blend_01:
2001 ; SSSE3-NEXT: movsd %xmm1, %xmm0
2002 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
2003 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
2004 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2007 ; SSE41-LABEL: combine_blend_01:
2009 ; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm1[0],xmm0[1]
2010 ; SSE41-NEXT: movapd %xmm1, %xmm0
2013 ; AVX-LABEL: combine_blend_01:
2015 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2017 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
2018 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
2019 ret <4 x float> %shuffle6
2022 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
2023 ; SSE2-LABEL: combine_blend_02:
2025 ; SSE2-NEXT: movss %xmm1, %xmm0
2026 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
2027 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2030 ; SSSE3-LABEL: combine_blend_02:
2032 ; SSSE3-NEXT: movss %xmm1, %xmm0
2033 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
2034 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2037 ; SSE41-LABEL: combine_blend_02:
2039 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2040 ; SSE41-NEXT: movaps %xmm1, %xmm0
2043 ; AVX-LABEL: combine_blend_02:
2045 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2047 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
2048 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
2049 ret <4 x float> %shuffle6
2052 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
2053 ; SSE2-LABEL: combine_blend_123:
2055 ; SSE2-NEXT: movaps %xmm1, %xmm2
2056 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[0,0]
2057 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
2058 ; SSE2-NEXT: movsd %xmm2, %xmm1
2059 ; SSE2-NEXT: movaps %xmm1, %xmm0
2062 ; SSSE3-LABEL: combine_blend_123:
2064 ; SSSE3-NEXT: movaps %xmm1, %xmm2
2065 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[0,0]
2066 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
2067 ; SSSE3-NEXT: movsd %xmm2, %xmm1
2068 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2071 ; SSE41-LABEL: combine_blend_123:
2073 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
2074 ; SSE41-NEXT: movaps %xmm1, %xmm0
2077 ; AVX-LABEL: combine_blend_123:
2079 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2081 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
2082 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
2083 %shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2084 ret <4 x float> %shuffle12
2087 define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
2088 ; SSE-LABEL: combine_test_movhl_1:
2090 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2091 ; SSE-NEXT: movdqa %xmm1, %xmm0
2094 ; AVX-LABEL: combine_test_movhl_1:
2096 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2098 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
2099 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
2103 define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
2104 ; SSE-LABEL: combine_test_movhl_2:
2106 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2107 ; SSE-NEXT: movdqa %xmm1, %xmm0
2110 ; AVX-LABEL: combine_test_movhl_2:
2112 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2114 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
2115 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
2119 define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
2120 ; SSE-LABEL: combine_test_movhl_3:
2122 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2123 ; SSE-NEXT: movdqa %xmm1, %xmm0
2126 ; AVX-LABEL: combine_test_movhl_3:
2128 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2130 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
2131 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>
2136 ; Verify that we fold shuffles according to rule:
2137 ; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
2139 define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
2140 ; SSE2-LABEL: combine_undef_input_test1:
2142 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2143 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2144 ; SSE2-NEXT: movaps %xmm1, %xmm0
2147 ; SSSE3-LABEL: combine_undef_input_test1:
2149 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2150 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2151 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2154 ; SSE41-LABEL: combine_undef_input_test1:
2156 ; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm1[0],xmm0[1]
2157 ; SSE41-NEXT: movapd %xmm1, %xmm0
2160 ; AVX-LABEL: combine_undef_input_test1:
2162 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2164 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2165 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2169 define <4 x float> @combine_undef_input_test2(<4 x float> %a, <4 x float> %b) {
2170 ; SSE-LABEL: combine_undef_input_test2:
2172 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2175 ; AVX-LABEL: combine_undef_input_test2:
2177 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2179 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2180 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2184 define <4 x float> @combine_undef_input_test3(<4 x float> %a, <4 x float> %b) {
2185 ; SSE-LABEL: combine_undef_input_test3:
2187 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2190 ; AVX-LABEL: combine_undef_input_test3:
2192 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2194 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2195 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2199 define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
2200 ; SSE-LABEL: combine_undef_input_test4:
2202 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2203 ; SSE-NEXT: movapd %xmm1, %xmm0
2206 ; AVX-LABEL: combine_undef_input_test4:
2208 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2210 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2211 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2215 define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
2216 ; SSE2-LABEL: combine_undef_input_test5:
2218 ; SSE2-NEXT: movsd %xmm0, %xmm1
2219 ; SSE2-NEXT: movaps %xmm1, %xmm0
2222 ; SSSE3-LABEL: combine_undef_input_test5:
2224 ; SSSE3-NEXT: movsd %xmm0, %xmm1
2225 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2228 ; SSE41-LABEL: combine_undef_input_test5:
2230 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2233 ; AVX-LABEL: combine_undef_input_test5:
2235 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2237 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2238 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2243 ; Verify that we fold shuffles according to rule:
2244 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2246 define <4 x float> @combine_undef_input_test6(<4 x float> %a) {
2247 ; ALL-LABEL: combine_undef_input_test6:
2250 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2251 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2255 define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
2256 ; SSE2-LABEL: combine_undef_input_test7:
2258 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2261 ; SSSE3-LABEL: combine_undef_input_test7:
2263 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2266 ; SSE41-LABEL: combine_undef_input_test7:
2268 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2271 ; AVX-LABEL: combine_undef_input_test7:
2273 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2275 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2276 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2280 define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
2281 ; SSE2-LABEL: combine_undef_input_test8:
2283 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2286 ; SSSE3-LABEL: combine_undef_input_test8:
2288 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2291 ; SSE41-LABEL: combine_undef_input_test8:
2293 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2296 ; AVX-LABEL: combine_undef_input_test8:
2298 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2300 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2301 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2305 define <4 x float> @combine_undef_input_test9(<4 x float> %a) {
2306 ; SSE-LABEL: combine_undef_input_test9:
2308 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2311 ; AVX-LABEL: combine_undef_input_test9:
2313 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2315 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2316 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2320 define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
2321 ; ALL-LABEL: combine_undef_input_test10:
2324 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2325 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2329 define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
2330 ; SSE2-LABEL: combine_undef_input_test11:
2332 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2333 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2334 ; SSE2-NEXT: movaps %xmm1, %xmm0
2337 ; SSSE3-LABEL: combine_undef_input_test11:
2339 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2340 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2341 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2344 ; SSE41-LABEL: combine_undef_input_test11:
2346 ; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm1[0],xmm0[1]
2347 ; SSE41-NEXT: movapd %xmm1, %xmm0
2350 ; AVX-LABEL: combine_undef_input_test11:
2352 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2354 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2355 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 6>
2359 define <4 x float> @combine_undef_input_test12(<4 x float> %a, <4 x float> %b) {
2360 ; SSE-LABEL: combine_undef_input_test12:
2362 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2365 ; AVX-LABEL: combine_undef_input_test12:
2367 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2369 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2370 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2374 define <4 x float> @combine_undef_input_test13(<4 x float> %a, <4 x float> %b) {
2375 ; SSE-LABEL: combine_undef_input_test13:
2377 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2380 ; AVX-LABEL: combine_undef_input_test13:
2382 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2384 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2385 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 5, i32 0, i32 5>
2389 define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
2390 ; SSE-LABEL: combine_undef_input_test14:
2392 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2393 ; SSE-NEXT: movapd %xmm1, %xmm0
2396 ; AVX-LABEL: combine_undef_input_test14:
2398 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2400 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2401 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2405 define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
2406 ; SSE2-LABEL: combine_undef_input_test15:
2408 ; SSE2-NEXT: movsd %xmm0, %xmm1
2409 ; SSE2-NEXT: movaps %xmm1, %xmm0
2412 ; SSSE3-LABEL: combine_undef_input_test15:
2414 ; SSSE3-NEXT: movsd %xmm0, %xmm1
2415 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2418 ; SSE41-LABEL: combine_undef_input_test15:
2420 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2423 ; AVX-LABEL: combine_undef_input_test15:
2425 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2427 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2428 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2433 ; Verify that shuffles are canonicalized according to rules:
2434 ; shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
2436 ; This allows to trigger the following combine rule:
2437 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2439 ; As a result, all the shuffle pairs in each function below should be
2440 ; combined into a single legal shuffle operation.
2442 define <4 x float> @combine_undef_input_test16(<4 x float> %a) {
2443 ; ALL-LABEL: combine_undef_input_test16:
2446 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2447 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
2451 define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
2452 ; SSE2-LABEL: combine_undef_input_test17:
2454 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2457 ; SSSE3-LABEL: combine_undef_input_test17:
2459 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2462 ; SSE41-LABEL: combine_undef_input_test17:
2464 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2467 ; AVX-LABEL: combine_undef_input_test17:
2469 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2471 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2472 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2476 define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
2477 ; SSE2-LABEL: combine_undef_input_test18:
2479 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2482 ; SSSE3-LABEL: combine_undef_input_test18:
2484 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2487 ; SSE41-LABEL: combine_undef_input_test18:
2489 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2492 ; AVX-LABEL: combine_undef_input_test18:
2494 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2496 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2497 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
2501 define <4 x float> @combine_undef_input_test19(<4 x float> %a) {
2502 ; SSE-LABEL: combine_undef_input_test19:
2504 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2507 ; AVX-LABEL: combine_undef_input_test19:
2509 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2511 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2512 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2516 define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
2517 ; ALL-LABEL: combine_undef_input_test20:
2520 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2521 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2525 ; These tests are designed to test the ability to combine away unnecessary
2526 ; operations feeding into a shuffle. The AVX cases are the important ones as
2527 ; they leverage operations which cannot be done naturally on the entire vector
2528 ; and thus are decomposed into multiple smaller operations.
2530 define <8 x i32> @combine_unneeded_subvector1(<8 x i32> %a) {
2531 ; SSE-LABEL: combine_unneeded_subvector1:
2533 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2534 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
2535 ; SSE-NEXT: movdqa %xmm0, %xmm1
2538 ; AVX1-LABEL: combine_unneeded_subvector1:
2540 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2541 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2542 ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2543 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2546 ; AVX2-LABEL: combine_unneeded_subvector1:
2548 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2549 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
2550 ; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
2552 %b = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2553 %c = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
2557 define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
2558 ; SSE-LABEL: combine_unneeded_subvector2:
2560 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2561 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,2,1,0]
2562 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
2565 ; AVX1-LABEL: combine_unneeded_subvector2:
2567 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2568 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2569 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2570 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
2571 ; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,2,1,0]
2572 ; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2573 ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
2576 ; AVX2-LABEL: combine_unneeded_subvector2:
2578 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2579 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = <7,6,5,4,u,u,u,u>
2580 ; AVX2-NEXT: vpermd %ymm1, %ymm2, %ymm1
2581 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2582 ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
2584 %c = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2585 %d = shufflevector <8 x i32> %b, <8 x i32> %c, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>