1 ; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx | FileCheck %s
2 ; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx -x86-experimental-vector-widening-legalization | FileCheck %s --check-prefix=CHECK-WIDE
4 define <8 x float> @foo1_8(<8 x i8> %src) {
7 ; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4,4,5,5,6,6,7,7]
8 ; CHECK-NEXT: vpmovzxwd %xmm0, %xmm0
9 ; CHECK-NEXT: vpslld $24, %xmm0, %xmm0
10 ; CHECK-NEXT: vpsrad $24, %xmm0, %xmm0
11 ; CHECK-NEXT: vpslld $24, %xmm1, %xmm1
12 ; CHECK-NEXT: vpsrad $24, %xmm1, %xmm1
13 ; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
14 ; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm0
17 ; CHECK-WIDE-LABEL: foo1_8:
18 ; CHECK-WIDE: ## BB#0:
19 ; CHECK-WIDE-NEXT: vpmovzxbd %xmm0, %xmm1
20 ; CHECK-WIDE-NEXT: vpslld $24, %xmm1, %xmm1
21 ; CHECK-WIDE-NEXT: vpsrad $24, %xmm1, %xmm1
22 ; CHECK-WIDE-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
23 ; CHECK-WIDE-NEXT: vpslld $24, %xmm0, %xmm0
24 ; CHECK-WIDE-NEXT: vpsrad $24, %xmm0, %xmm0
25 ; CHECK-WIDE-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
26 ; CHECK-WIDE-NEXT: vcvtdq2ps %ymm0, %ymm0
27 ; CHECK-WIDE-NEXT: retl
28 %res = sitofp <8 x i8> %src to <8 x float>
32 define <4 x float> @foo1_4(<4 x i8> %src) {
33 ; CHECK-LABEL: foo1_4:
35 ; CHECK-NEXT: vpslld $24, %xmm0, %xmm0
36 ; CHECK-NEXT: vpsrad $24, %xmm0, %xmm0
37 ; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
40 ; CHECK-WIDE-LABEL: foo1_4:
41 ; CHECK-WIDE: ## BB#0:
42 ; CHECK-WIDE-NEXT: vpmovzxbd %xmm0, %xmm0
43 ; CHECK-WIDE-NEXT: vpslld $24, %xmm0, %xmm0
44 ; CHECK-WIDE-NEXT: vpsrad $24, %xmm0, %xmm0
45 ; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
46 ; CHECK-WIDE-NEXT: retl
47 %res = sitofp <4 x i8> %src to <4 x float>
51 define <8 x float> @foo2_8(<8 x i8> %src) {
52 ; CHECK-LABEL: foo2_8:
54 ; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4,4,5,5,6,6,7,7]
55 ; CHECK-NEXT: vpmovzxwd %xmm0, %xmm0
56 ; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
57 ; CHECK-NEXT: vandps LCPI2_0, %ymm0, %ymm0
58 ; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm0
61 ; CHECK-WIDE-LABEL: foo2_8:
62 ; CHECK-WIDE: ## BB#0:
63 ; CHECK-WIDE-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
64 ; CHECK-WIDE-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
65 ; CHECK-WIDE-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
66 ; CHECK-WIDE-NEXT: vcvtdq2ps %ymm0, %ymm0
67 ; CHECK-WIDE-NEXT: retl
68 %res = uitofp <8 x i8> %src to <8 x float>
72 define <4 x float> @foo2_4(<4 x i8> %src) {
73 ; CHECK-LABEL: foo2_4:
75 ; CHECK-NEXT: vandps LCPI3_0, %xmm0, %xmm0
76 ; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
79 ; CHECK-WIDE-LABEL: foo2_4:
80 ; CHECK-WIDE: ## BB#0:
81 ; CHECK-WIDE-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
82 ; CHECK-WIDE-NEXT: vpxor %xmm1, %xmm1, %xmm1
83 ; CHECK-WIDE-NEXT: vpshufb {{.*#+}} xmm1 = zero,xmm1[1,2,3],zero,xmm1[5,6,7],zero,xmm1[9,10,11],zero,xmm1[13,14,15]
84 ; CHECK-WIDE-NEXT: vpor %xmm0, %xmm1, %xmm0
85 ; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
86 ; CHECK-WIDE-NEXT: retl
87 %res = uitofp <4 x i8> %src to <4 x float>
91 define <8 x i8> @foo3_8(<8 x float> %src) {
92 ; CHECK-LABEL: foo3_8:
94 ; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0
95 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
96 ; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,128,128,128,128,128,128,128,128]
97 ; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1
98 ; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0
99 ; CHECK-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
100 ; CHECK-NEXT: vzeroupper
103 ; CHECK-WIDE-LABEL: foo3_8:
104 ; CHECK-WIDE: ## BB#0:
105 ; CHECK-WIDE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[3,0,0,0]
106 ; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %eax
107 ; CHECK-WIDE-NEXT: shll $8, %eax
108 ; CHECK-WIDE-NEXT: vmovhlps {{.*#+}} xmm1 = xmm0[1,1]
109 ; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %ecx
110 ; CHECK-WIDE-NEXT: movzbl %cl, %ecx
111 ; CHECK-WIDE-NEXT: orl %eax, %ecx
112 ; CHECK-WIDE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,0,0,0]
113 ; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %eax
114 ; CHECK-WIDE-NEXT: shll $8, %eax
115 ; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %edx
116 ; CHECK-WIDE-NEXT: movzbl %dl, %edx
117 ; CHECK-WIDE-NEXT: orl %eax, %edx
118 ; CHECK-WIDE-NEXT: vpinsrw $0, %edx, %xmm0, %xmm1
119 ; CHECK-WIDE-NEXT: vpinsrw $1, %ecx, %xmm1, %xmm1
120 ; CHECK-WIDE-NEXT: vextractf128 $1, %ymm0, %xmm0
121 ; CHECK-WIDE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,0,0,0]
122 ; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax
123 ; CHECK-WIDE-NEXT: shll $8, %eax
124 ; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %ecx
125 ; CHECK-WIDE-NEXT: movzbl %cl, %ecx
126 ; CHECK-WIDE-NEXT: orl %eax, %ecx
127 ; CHECK-WIDE-NEXT: vpinsrw $2, %ecx, %xmm1, %xmm1
128 ; CHECK-WIDE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[3,0,0,0]
129 ; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax
130 ; CHECK-WIDE-NEXT: shll $8, %eax
131 ; CHECK-WIDE-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
132 ; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %ecx
133 ; CHECK-WIDE-NEXT: movzbl %cl, %ecx
134 ; CHECK-WIDE-NEXT: orl %eax, %ecx
135 ; CHECK-WIDE-NEXT: vpinsrw $3, %ecx, %xmm1, %xmm0
136 ; CHECK-WIDE-NEXT: vzeroupper
137 ; CHECK-WIDE-NEXT: retl
138 %res = fptosi <8 x float> %src to <8 x i8>
142 define <4 x i8> @foo3_4(<4 x float> %src) {
143 ; CHECK-LABEL: foo3_4:
145 ; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
148 ; CHECK-WIDE-LABEL: foo3_4:
149 ; CHECK-WIDE: ## BB#0:
150 ; CHECK-WIDE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[3,0,0,0]
151 ; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %eax
152 ; CHECK-WIDE-NEXT: shll $8, %eax
153 ; CHECK-WIDE-NEXT: vmovhlps {{.*#+}} xmm1 = xmm0[1,1]
154 ; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %ecx
155 ; CHECK-WIDE-NEXT: movzbl %cl, %ecx
156 ; CHECK-WIDE-NEXT: orl %eax, %ecx
157 ; CHECK-WIDE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,0,0,0]
158 ; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %eax
159 ; CHECK-WIDE-NEXT: shll $8, %eax
160 ; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %edx
161 ; CHECK-WIDE-NEXT: movzbl %dl, %edx
162 ; CHECK-WIDE-NEXT: orl %eax, %edx
163 ; CHECK-WIDE-NEXT: vpinsrw $0, %edx, %xmm0, %xmm0
164 ; CHECK-WIDE-NEXT: vpinsrw $1, %ecx, %xmm0, %xmm0
165 ; CHECK-WIDE-NEXT: retl
166 %res = fptosi <4 x float> %src to <4 x i8>