[AArch64] Fix bug in prolog clobbering live reg when shrink wrapping.
[oota-llvm.git] / test / CodeGen / SPARC / 2008-10-10-InlineAsmRegOperand.ll
1 ; RUN: llc < %s -march=sparc
2 ; PR 1557
3
4 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128"
5 module asm "\09.section\09\22.ctors\22,#alloc,#write"
6 module asm "\09.section\09\22.dtors\22,#alloc,#write"
7
8 define void @frame_dummy() nounwind {
9 entry:
10         %asmtmp = tail call void (i8*)* (void (i8*)*) asm "", "=r,0"(void (i8*)* @_Jv_RegisterClasses) nounwind         ; <void (i8*)*> [#uses=0]
11         unreachable
12 }
13
14 declare void @_Jv_RegisterClasses(i8*)