1 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s
2 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s
3 ; RUN: llc -march=mips64 -target-abi=n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s
4 ; RUN: llc -march=mips64el -target-abi=n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s
6 @v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
7 @v2f64 = global <2 x double> <double 0.0, double 0.0>
9 @f32 = global float 0.0
10 @f64 = global double 0.0
12 define void @const_v4f32() nounwind {
13 ; ALL-LABEL: const_v4f32:
15 store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
16 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
18 store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
19 ; ALL: lui [[R1:\$[0-9]+]], 16256
20 ; ALL: fill.w [[R2:\$w[0-9]+]], [[R1]]
22 store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
23 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
24 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
25 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
26 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
28 store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
29 ; ALL: lui [[R1:\$[0-9]+]], 18304
30 ; ALL: ori [[R2:\$[0-9]+]], [[R1]], 128
31 ; ALL: fill.w [[R3:\$w[0-9]+]], [[R2]]
33 store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
34 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
35 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
36 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
37 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
39 store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
40 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
41 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
42 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
43 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
48 define void @const_v2f64() nounwind {
49 ; ALL-LABEL: const_v2f64:
51 store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
52 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
54 store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
55 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
56 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
57 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
58 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
60 store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
61 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
62 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
63 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
64 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
66 store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
67 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
68 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
69 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
70 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
72 store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
73 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
74 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
75 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
76 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
78 store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
79 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
80 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
81 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
82 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
84 store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
85 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
86 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
87 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
88 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
93 define void @nonconst_v4f32() nounwind {
94 ; ALL-LABEL: nonconst_v4f32:
96 %1 = load float , float *@f32
97 %2 = insertelement <4 x float> undef, float %1, i32 0
98 %3 = insertelement <4 x float> %2, float %1, i32 1
99 %4 = insertelement <4 x float> %3, float %1, i32 2
100 %5 = insertelement <4 x float> %4, float %1, i32 3
101 store volatile <4 x float> %5, <4 x float>*@v4f32
102 ; ALL: lwc1 $f[[R1:[0-9]+]], 0(
103 ; ALL: splati.w [[R2:\$w[0-9]+]], $w[[R1]]
108 define void @nonconst_v2f64() nounwind {
109 ; ALL-LABEL: nonconst_v2f64:
111 %1 = load double , double *@f64
112 %2 = insertelement <2 x double> undef, double %1, i32 0
113 %3 = insertelement <2 x double> %2, double %1, i32 1
114 store volatile <2 x double> %3, <2 x double>*@v2f64
115 ; ALL: ldc1 $f[[R1:[0-9]+]], 0(
116 ; ALL: splati.d [[R2:\$w[0-9]+]], $w[[R1]]
121 define float @extract_v4f32() nounwind {
122 ; ALL-LABEL: extract_v4f32:
124 %1 = load <4 x float>, <4 x float>* @v4f32
125 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
127 %2 = fadd <4 x float> %1, %1
128 ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
130 %3 = extractelement <4 x float> %2, i32 1
131 ; Element 1 can be obtained by splatting it across the vector and extracting
133 ; ALL-DAG: splati.w $w0, [[R1]][1]
138 define float @extract_v4f32_elt0() nounwind {
139 ; ALL-LABEL: extract_v4f32_elt0:
141 %1 = load <4 x float>, <4 x float>* @v4f32
142 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
144 %2 = fadd <4 x float> %1, %1
145 ; ALL-DAG: fadd.w $w0, [[R1]], [[R1]]
147 %3 = extractelement <4 x float> %2, i32 0
148 ; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
155 define float @extract_v4f32_elt2() nounwind {
156 ; ALL-LABEL: extract_v4f32_elt2:
158 %1 = load <4 x float>, <4 x float>* @v4f32
159 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
161 %2 = fadd <4 x float> %1, %1
162 ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
164 %3 = extractelement <4 x float> %2, i32 2
165 ; Element 2 can be obtained by splatting it across the vector and extracting
167 ; ALL-DAG: splati.w $w0, [[R1]][2]
172 define float @extract_v4f32_vidx() nounwind {
173 ; ALL-LABEL: extract_v4f32_vidx:
175 %1 = load <4 x float>, <4 x float>* @v4f32
176 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
177 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(
178 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(
179 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
181 %2 = fadd <4 x float> %1, %1
182 ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
184 %3 = load i32, i32* @i32
185 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
186 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
187 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
188 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
190 %4 = extractelement <4 x float> %2, i32 %3
191 ; ALL-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]]
196 define double @extract_v2f64() nounwind {
197 ; ALL-LABEL: extract_v2f64:
199 %1 = load <2 x double>, <2 x double>* @v2f64
200 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
202 %2 = fadd <2 x double> %1, %1
203 ; ALL-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
205 %3 = extractelement <2 x double> %2, i32 1
206 ; Element 1 can be obtained by splatting it across the vector and extracting
208 ; ALL-DAG: splati.d $w0, [[R1]][1]
218 define double @extract_v2f64_elt0() nounwind {
219 ; ALL-LABEL: extract_v2f64_elt0:
221 %1 = load <2 x double>, <2 x double>* @v2f64
222 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
224 %2 = fadd <2 x double> %1, %1
225 ; ALL-DAG: fadd.d $w0, [[R1]], [[R1]]
227 %3 = extractelement <2 x double> %2, i32 0
228 ; Element 0 can be obtained by extracting $w0:sub_64 ($f0)
238 define double @extract_v2f64_vidx() nounwind {
239 ; ALL-LABEL: extract_v2f64_vidx:
241 %1 = load <2 x double>, <2 x double>* @v2f64
242 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
243 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(
244 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(
245 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
247 %2 = fadd <2 x double> %1, %1
248 ; ALL-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
250 %3 = load i32, i32* @i32
251 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
252 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
253 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
254 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
256 %4 = extractelement <2 x double> %2, i32 %3
257 ; ALL-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]]
262 define void @insert_v4f32(float %a) nounwind {
263 ; ALL-LABEL: insert_v4f32:
265 %1 = load <4 x float>, <4 x float>* @v4f32
266 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
268 %2 = insertelement <4 x float> %1, float %a, i32 1
269 ; float argument passed in $f12
270 ; ALL-DAG: insve.w [[R1]][1], $w12[0]
272 store <4 x float> %2, <4 x float>* @v4f32
273 ; ALL-DAG: st.w [[R1]]
278 define void @insert_v2f64(double %a) nounwind {
279 ; ALL-LABEL: insert_v2f64:
281 %1 = load <2 x double>, <2 x double>* @v2f64
282 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
284 %2 = insertelement <2 x double> %1, double %a, i32 1
285 ; double argument passed in $f12
286 ; ALL-DAG: insve.d [[R1]][1], $w12[0]
288 store <2 x double> %2, <2 x double>* @v2f64
289 ; ALL-DAG: st.d [[R1]]
294 define void @insert_v4f32_vidx(float %a) nounwind {
295 ; ALL-LABEL: insert_v4f32_vidx:
297 %1 = load <4 x float>, <4 x float>* @v4f32
298 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
299 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(
300 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(
301 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
303 %2 = load i32, i32* @i32
304 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
305 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
306 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
307 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
309 %3 = insertelement <4 x float> %1, float %a, i32 %2
310 ; float argument passed in $f12
311 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
312 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
313 ; ALL-DAG: insve.w [[R1]][0], $w12[0]
314 ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
315 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
317 store <4 x float> %3, <4 x float>* @v4f32
318 ; ALL-DAG: st.w [[R1]]
323 define void @insert_v2f64_vidx(double %a) nounwind {
324 ; ALL-LABEL: insert_v2f64_vidx:
326 %1 = load <2 x double>, <2 x double>* @v2f64
327 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
328 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(
329 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(
330 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
332 %2 = load i32, i32* @i32
333 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
334 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
335 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
336 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
338 %3 = insertelement <2 x double> %1, double %a, i32 %2
339 ; double argument passed in $f12
340 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3
341 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
342 ; ALL-DAG: insve.d [[R1]][0], $w12[0]
343 ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
344 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
346 store <2 x double> %3, <2 x double>* @v2f64
347 ; ALL-DAG: st.d [[R1]]